Unit III Casestudies 131221124123 Phpapp02

7/26/2019 Unit III Casestudies 131221124123 Phpapp02

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Dr.Y.Narasimmha Murthy [email protected]

UNIT III : CASE STUDIES

[CPLD & FPGA ARCHITECTURE & APPLICATIONS]

INTRODUCTION:

The Field Programmable Gate Arrays consist of an array of programmable logic blocks

including general logic, memory and multiplier blocks, surrounded by a programmable routing

fabric that allows blocks to be . The array is surrounded by programmable input/output blocks,

labeled I/ in the figure, that connect the chip to the outside world. !ere the term

"programmable# indicates an ability to program a function into the chip after completion of

silicon fabrication . This is possible by the programming technology, which is a method that can

cause a change in the beha$ior of the pre%fabricated chip after fabrication, in the "field,# where

system users create designs. The first programmable logic de$ices used $ery small fuses as the

programming technology. &$ery FPGA depends on a programming technology that is used to

control the programmable switches that gi$e FPGAs their programmability.

Programming Technoogie!

There are a number of programming technologies that ha$e been used for reconfigurablearchitectures. &ach of these technologies ha$e different characteristics and ha$e significant effect

on the programmable architecture. 'ome of the well%known technologies are

(i).'*A+ ased Programming Technology (ii).Flash Programming Technology(&&P*+) ,

and (iii) Anti%fuse based Programming Technology

SRA"#$a!e% Programming Technoog

'tatic memory cells are the basic cells used for '*A+%based FPGAs. +ost commercial $endors like-II-, attice and Altera etc.. use static memory ('*A+) based programming technology in their

de$ices. These de$ices use static memory cells which are di$ided throughout the FPGA to pro$ide

configurability. An e0ample of such memory cell is shown below .In an '*A+%based FPGA, '*A+

cells are mainly used for following purposes

(i). To program the routing interconnect of FPGAs which are generally steered by small multiple0ors.

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(ii). To program 1onfigurable ogic locks (1s) that are used to implement logic functions.

There are two primary uses for the '*A+ cells. +ost are used to set the select lines to

multiple0ers that steer interconnect signals. The ma2ority of the remaining '*A+ cells are used

to store the data in the lookup%tables (3Ts) that are typically used in '*A+%based FPGAs to

implement logic functions. !istorically, '*A+ cells were used to control the tri%state buffers and

simple pass transistors that were also used for programmable interconnect.

'*A+%based programming technology has become the dominant approach for FPGAs because

of its re%programmability and the use of standard 1+' process technology and therefore

leading to increased integration, higher speed and lower dynamic power consumption of new

process with smaller geometry.

There are howe$er a number of drawbacks associated with '*A+%based programming

technology. For e0ample an '*A+ cell re4uires 5 transistors which makes this technology

costly in terms of area compared to other programming technologies.

Further '*A+ cells are $olatile in nature and e0ternal de$ices are re4uired to permanently store

the configuration data. These e0ternal de$ices add to the cost and area o$erhead of '*A+%based

FPGAs.

There is a problem in terms of security of data also. 'ince the configuration information must be

loaded into the de$ice at power up, there is the possibility that the configuration information

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could be intercepted and stolen for use in a competing system. To o$ercome this problem certain

encryption techni4ues are followed.

&lectrical properties of pass transistors are not ideal. i.e '*A+%based FPGAs typically rely onthe use of pass transistors to implement multiple0ers. !owe$er, they are far from ideal switches

as they ha$e significant on%resistances and present an appreciable capaciti$e load. As FPGAs

migrate to smaller de$ice geometries these issues may be e0acerbated.

Fa!h Programming Technoog

An important alternati$e to the '*A+%based programming technology is the use of flash or

&&P*+ based programming technology. This technology in2ect charge onto a gate that

"floats# abo$e the transistor. This approach is used in flash or &&P*+ memory cells. These

cells are non%$olatile6 they do not lose information when the de$ice is powered down. 7ith

modern I1 fabrication processes, it has become possible to use the floating gate cells directly as

switches. Flash memory cells, in particular, are now used because of their impro$ed area

efficiency. The widespread use of flash memory cells for non%$olatile memory chips ensures that

flash manufacturing processes will benefit from steady decreases in process geometries.

Flash%based programming technology offers se$eral ad$antages. For e0ample, this programming

technology is non$olatile in nature. Flash%based programming technology is also more areaefficient than '*A+%based programming technology. Flash%based programming technology has

its own disad$antages also. 3nlike '*A+%based programming technology, flash based de$ices

cannot be reconfigured/reprogrammed an infinite number of times. Also, flash%based technology

uses non%standard 1+' process.

This flash%based programming technology offers se$eral uni4ue ad$antages, most importantly

non%$olatility. This feature eliminates the need for the e0ternal resources re4uired to store and

load configuration data when '*A+%based programming technology is used. Additionally,a flash%based de$ice can function immediately upon power%up instead of ha$ing to wait for the

loading of configuration data. The flash approach is also more area efficient than '*A+%based

technology which re4uires up to si0 transistors to implement the programmable storage. The

programming circuitry, such as the high and low $oltage buffers needed to program the cell,

contributes an area o$erhead not present in '*A+%based de$ices. !owe$er, this cost is relati$ely

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modest as it is amorti8ed across numerous programmable elements. In comparison to anti%fuses,

an alternati$e non%$olatile programming technology, flash%based FPGAs are reconfigurable and

can be programmed without being remo$ed from a printed circuit board. The use of a floating%gate to control the switching transistor adds design comple0ity because care must be taken to

ensure the source9drain $oltage remains sufficiently low to pre$ent charge in2ection into the

floating gate . 'ince newer processes re4uire lower $oltage le$els, this issue may become less of

a concern in the future .ne disad$antage of flash%based de$ices is that they cannot be

reprogrammed an infinite number of times. 1harge buildup in the o0ide e$entually pre$ents a

flash%based de$ice from being properly erased and programmed . :e$ices such as the Actel

ProA'I1; are useful for only


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normal circumstances but can be programmably "blown# (in reality, connected) to create a low

resistance link.

An anti%fuse is a two terminal de$ice with an unprogrammed state presenting a $ery high

resistance between its terminals. 7hen a high $oltage (from >> to ?= $olts, depending on the

type of anti%fuse) is applied across its terminals the anti%fuse will "blow# and create a low

resistance link. This link is permanent. Anti%fuses in use today are built either using an 0ygen%

itrogen%0ygen () dielectric between @ diffusion and poly%silicon or amorphous silicon

between metal layers or between polysilicon and the first layer of metal.

Programming an anti%fuse re4uires e0tra circuitry to deli$er the high programming $oltage and a

relati$ely high current of < mA or more. This is done in through fairly si8able pass transistors to

pro$ide addressing to each anti%fuse. Anti%fuse technology is used in the FPGAs from Actel ,

Buick logic , and 1ross point.

A ma2or ad$antage of the anti%fuse is its small si8e, little more than the cross%section of two

metal wires. ut this ad$antage is limited by the large si8e of the necessary programming

transistors, which handle large currents, and the inclusion of isolation transistors that are

sometimes needed to protect low $oltage transistors from high programming $oltages.

A second ma2or ad$antage of an anti%fuse is its relati$ely low series resistance. The on%resistance

of the anti%fuse is ;== to


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Com*ari!on o( Programming Technoogie!

Programmin

g Technoog

Re#Programma+e ,oa'ie

S'orage

Serie!

Re!i!'ance

Ca*aci'ance

in *(

Ce Area

'tatic *A+ In%circuit Ces >DE >< -

&&P*+ In%1ircuit o ? DE >= ?-

-ILIN- -C./// FPGA De0ice

-ilin0 introduced the first FPGA family, called the -1?=== series, in >< and ne0t offered

three more series of FPGAs namely -1;===, -1H===, and -1,=== to 5,=== gates with up to >HH user%definable I/s. :e$ice

speeds, described in terms of ma0imum guaranteed toggle fre4uencies, range from = to >?5 bits of configuration memory.

The two lookup tables can be combined with a multiple0er to produce any function of fi$e inputs

and some functions of up to se$en inputs.The -1;=== archtecture allows faster logic

implementation with minimum 1s in series.

There are now four distinct familes within the -1;=== 'eries of FPGA de$ices

J -1;===A Family

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J -1;=== Family

J -1;>==A Family

J -1;>== Family

All four families share a common architecture, de$elopment software, design and programming

methodology, and also common package pin%outs.

J -C.///A Fami :The -1;===A is an enhanced $ersion of the basic -1;=== family,

featuring additional interconnect resources and other user%friendly enhancements.

J -C.///L Fami :The -1;=== is identical in architecture and features to the -1;===A

family, but operates at a nominal supply $oltage of ;.; K. The -1;=== is the right solution for

battery%operated and low%power applications.

J -C.1//A Fami L The -1;>==A is a performance%optimi8ed relati$e of the -1;===A

family. 7hile both families are bit stream and footprint compatible, the -1;>==A family e0tends

toggle rates to ;= +!8 and in%system performance to o$er = +!8. The -1;>==A family also

offers one additional array si8e, the -1;>== is identical in architectures and features to the -1;>==A

family, but operates at a nominal supply $oltage of ;.;K

The basic 1A (ogic 1ell Array) of -1;=== consists of three components .They are

Programmable I/ locks , 1onfigurable ogic lock and Programmable Interconnect. In

addition to this a small amount of configurable memory is also present .

Programmable I/O Block

&ach user%configurable I as shown below, pro$ides an interface between the e0ternal

package pin of the de$ice and the internal user logic. &ach I includes both registered and

direct input paths. &ach I pro$ides a programmable;%state output buffer, which may be dri$en

by a registered or direct output signal. 1onfiguration options allow each I an in$ersion, a

controlled slew rate and a high impedance pull%up. &ach input circuit also pro$ides input

clamping diodes to pro$ide electrostatic protection, and circuits to inhibit latch%up produced by

input currents.

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&ach I includes input and output storage elements and I/ options selected by configuration

memory cells. A choice of two clocks is a$ailable on each die edge. The polarity of each clock

line (not each flip%flop or latch) is programmable. A clock line that triggers the flip%flop on the

rising edge is an acti$e ow atch &nable (atch transparent) signal and $ice $ersa. Passi$e pull%

up can only be enabled on inputs, not on outputs. All user inputs are programmed for TT or

1+' thresholds.

Con(ig)ra+e Logic $oc23

&ach 1 includes a combinatorial logic section, two flip%flops and a program memory

controlled multiple0er selection of function. It has the following components

Fi$e logic $ariable inputs A, , 1, :, and &

a direct data in :I

an enable clock &1

a clock (in$ertible) D

an asynchronous direct *&'&T *:

Two outputs - and C.

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-C./// CL$

&ach 1 has a combinatorial logic section, two flip%flops, and an internal control section. The

1 has fi$e logic inputs (A, , 1, : and &) 6 a common clock input(D)6 an asynchronous

direct *&'&T input (*:) and an enable clock (&1) as shown in the block diagram. &ach 1

also has two outputs (- and C) which may dri$e interconnect networks. :ata input for the flip%

flops within a 1 is supplied from the function F or G outputs of the combinatorial logic, or

the block input, :I. oth flip%flops in each 1 share the asynchronous *: which, when

enabled , is dominant o$er clocked inputs. All flip%flops are reset by the acti$e%ow chip input,

*&'&T, or during the configuration process. The flip%flops share the enable clock (&1) which,

when ow, re circulates the flip%flops present states and inhibits response to the data%in or

combinatorial function inputs on a 1. The user may enable these control inputs and select

their sources. The user may also select the clock net input (D), as well as its acti$e sense within

each 1. This programmable in$ersion eliminates the need to route both phases of a clock

signal throughout the de$ice.

Programma+e In'erconnec' :

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Programmable%interconnection resources in the Field Programmable Gate Array pro$ide routing

paths to connect inputs and outputs of the Is and 1s into logic networks. Interconnections

between blocks are composed of a two%layer grid of metal segments. 'pecially designed passtransistors, each controlled by a configuration bit, form programmable interconnect points (PIPs)

and switching matrices used to implement the necessary connections between selected metal

segments and block pins.

Three types of metal resources are pro$ided to accommodate $arious network interconnect

re4uirements.

J General Purpose Interconnect

J :irect 1onnection

J ong lines (multiple0ed busses and wide A: gates)

-C./// In'erconnec'

-ILIN- -C4/// FPGA De0ice : The -1H=== features a 1onfigurable ogic lock (1)

that is based on look%up tables (3Ts). A 3T is a small one bit wide memory array, where the

address lines for the memory are inputs of the logic block and the one bit output from the

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memory is the 3T output. A 3T with D inputs would then correspond to a ?D 0 > bit memory

and can reali8e any logic function of its D inputs by programming the logic functions truth table

directly into the memory. The -1H=== 1 contains three separate 3Ts, in the configurationas shown below. There are two H%input 3T' that are fed by 1 inputs, and the third 3T can

be used in combination with the other two. This arrangement allows the 1 to implement a

wide range of logic functions of up to nine inputs, two separate functions of four inputs or other

possibilities. &ach 1 also contains two flip%flops.

-ilin0 -1H=== 1onfigurable ogic lock (1).

To pro$ide high density de$ices that support the integration of entire systems, the -1H===

chips ha$e "system oriented# features. For e0ample, each 1 contains circuitry that allows it to

efficiently perform arithmetic (i.e., a circuit that can implement a fast carry operation for adder%

like circuits) and also the 3Ts in a 1 can be configured as read/write *A+ cells. A new

$ersion of this family, the H===&, has the additional feature that the *A+ can be configured as a

dual port *A+ with a single write and two read ports. In the H===&, *A+ blocks can be

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synchronous *A+. Also, each -1H=== chip includes $ery wide A:%planes around the

periphery of the logic block array to facilitate implementing circuit blocks such as wide

decoders.The other important feature of this FPGA is its interconnect structure. The -1H===

interconnect is arranged in hori8ontal and $ertical channels. &ach channel contains some number

of short wire segments that span a single 1 (the number of segments in each channel depends

on the specific part number), longer segments that span two 1s, and $ery long segments that

span the entire length or width of the chip. Programmable switches are a$ailable to connect the

inputs and outputs of the 1s to the wire segments, or to connect one wire segment to another..

The figure below shows only the wire segments in a hori8ontal channel, and does not show the

$ertical routing channels, the 1 inputs and outputs, or the routing switches. The salient feature

about the -ilin0 interconnect is that signals must pass through switches to reach one 1 from

another, and the total number of switches tra$ersed depends on the particular set of wire

segments used. Thus, speed%performance of an implemented circuit depends in part on how the

wire segments are allocated to indi$idual signals by 1A: tools.

Ac'e FPGA!

In contrast to -II- FPGAs the de$ices manufactured by Actel are based on anti fuse

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technology. Actel offers three main families .They are M Act >, Act ?, and Act ;. Actel de$ices are

based on a structure similar to traditional gate arrays6 the logic blocks are arranged in rows and

there are hori8ontal routing channels between ad2acent rows. This architecture is shown in figurebelow. The logic blocks in the Actel de$ices are relati$ely small in comparison to the 3T based

ones. , and are based on multiple0ers. The figure illustrates the logic block in the Act ; and

shows that it comprises an A: and * gate that are connected to a multiple0er based circuit

block. The multiple0er circuit is arranged such that, in combination with the two logic gates, a

$ery wide range of functions can be reali8ed in a single logic block. About half of the logic

blocks in an Act ; de$ice also contain a flip%flop.

Actel FPGA structure.

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Actels interconnect is organi8ed in hori8ontal routing channels. The channels consist of wire

segments of $arious lengths with anti%fuses to connect logic blocks to wire segments or one wireto another. Also, Actel chips ha$e $ertical wires that o$erlay the logic blocks, for signal paths

that span multiple rows. In terms of speed%performance, it is e$ident that Actel chips are not fully

predictable, because the number of anti%fuses tra$ersed by a signal depends on how the wire

segments are allocated during circuit implementation by 1A: tools. !owe$er, Actel pro$ides a

rich selection of wire segments of different length in each channel and has de$eloped algorithms

that guarantee strict limits on the number of anti%fuses tra$ersed by any two%point connection in

a circuit which impro$es speed%performance significantly.

5)ic2ogic *ASIC FPGA! :

The Buicklogic is the main competitor for Actel in anti%fuse %based FPGAs . It produces two

families of de$ices, called pA'I1 and pA'I1%?. The pA'I1%? is an enhanced $ersion of

pA'I1. The pA'I1, consists of a regular two%dimensional array of blocks called pA'I1 ogic

locks (ps).The logic capacities of first generation of Buick ogic FPGAs is between H and

;=ps,or


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'tructure of Buicklogic pA'I1 FPGA.

It consists of a top layer of metal, an insulating layer of amorphous silicon, and a bottom layer of

metal. 7hen compared to Actels PI1& anti%fuse, Kia ink offers a $ery low on%resistance of

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In the F&- ===, &s are grouped into sets of , called ogic Array locks (As, a term

borrowed from Alteras 1P:s). As shown in Figure below each A contains local

interconnect and each local wire can connect any & to any other & within the same A.

Architecture of Altera F&- === FPGAs.

Altera F&- === ogic &lement (&).

ocal interconnect also connects to the F&- ===s global interconnect, called Fast Track. Fast

Track is similar to -ilin0 long lines in that each Fast Track wire e0tends the full width or height

of the de$ice. !owe$er, a ma2or difference between F&- === and -ilin0 chips is that Fast

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Track consists of only long lines. This makes the F&- === easy for 1A: tools to

automatically configure. All Fast%Track wires hori8ontal wires are identical, and so interconnect

delays in the F&- === are more predictable than FPGAs that employ many smaller lengthsegments because there are fewer programmable switches in the longer paths. Predictability is

furthered aided by the fact that connections between hori8ontal and $ertical lines pass through

acti$e buffers.

The F&- === architecture has been e0tended in the state%of%the%art F&- >==== family.

F&- >==== offers all of the features of F&- ===, with the addition of $ariable%si8ed blocks

of '*A+, called &mbedded Array locks (&As) which shows that each row in a F&- >====

chip has an &A on one end. &ach &A is configurable to ser$e as an '*A+ block with a

$ariable aspect ratioM ?D 0 ?, or ?D 0 >. In addition, an &A can alternati$ely

be configured to implement a comple0 logic circuit, such as a multiplier, by employing it as a

large multi%output lookup table. Altera pro$ides, as part of their 1A: tools, se$eral macro%

functions that implement useful logic circuits in &As. 1ounting the &As as logic gates, F&-

>==== offers the highest logic capacity of any FPGA, although it is hard to pro$ide an accurate

number.

Conc)rren' Logic FPGA De0ice : The manufacturer 1oncurrent ogic offers the 1FA5==5

FPGA de$ice ,which is based on two dimensional array of identical blocks ,where each block is

symmetrical on its four sides. The array holds ;>;5 of such blocks ,pro$iding a total logic

capacity of about


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There are two direct connections A and formed by routing signals through the multiple0ers

within the blocks.ong connection is implemented using a bussing network, in which wires of

$arious lengths are superimposed on the array of logic blocks.

Cro!!*oin' So)'ion! FPGA!:

The crosspoint FPGAs are different from other FPGAs because it is configurable at the

transistor le$el as aoposed to logic block le$el in other FPGAs.asically the architecture

consists of rows of transistor pairs ,where the rows are separated by hori8ontal wiring

segments .Keritical wiring segments are also a$ailable ,for connection among the rows.

&ach transistor row comprises two lines of series connected transistors ,with one line being

+' and the other P+' .The wiring resources allow indi$idual transistor pairs tobe

interconnected to implement 1+' logic gates. The programming technology used for the

programmable switches is similar to the Kia%ink anti%fuse ,which is based on amorphoussilicon.

The structure of the transistor pair rows is shown in below diagram.The diagram shows the

implementation of a * agte and a A: gate using the transistor lines. The transistor

gates ,drains , sources can be programmable interconnected to other transistors and also to

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power and ground.The series connections across the lines is broken where necessary by

permanently holding a transistor in its FF state. A wide range of logic gates can be

implemented by the transistor lines and the interconnection patterns.

The FPGAs currently offered by 1rosspoint 'olutions has a total logic capacity of H?==

gates.The chip has ? shows the

basic array architecture, indicating both nearest neighbor and global connections to the logic

cells. In addition to these logical connections, row select lines and bit select lines which are not

shown on the figure are connected to program each cells '*A+ bits.

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ALGOTRONI- Arra Archi'ec')re

The basic building block of the Algotroni0 design is a configurable cell containing multiple0ers

and a function unit. As indicated in the figure , the function unit is preceded by multiple0ers

which select the source for the -> and -? inputs. The function unit is capable of generating any

logic function of the two inputs, or of operating as a :%type latch. ot shown in the figure arefour additional multiple0ers which select the function output or one of the e0ternal inputs for

routing to each of the four outputs (north, south, east, and west).

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A uni4ue feature in the Algotroni0 I/ pad design is its capability to pro$ide simultaneous input

and output on the same pin when communicating with another Algotroni0 chip. This is done

through a ;%le$el (ternary) logic signaling scheme in which I/ pads sense whene$er two outputs

are dri$ing each other $ia a contention scheme. &$en during contention, the pad can deduce the

correct input $alue and pass it along to the internal circuitry. This makes it easier to partition a

single design across multiple FPGAs because the increased connecti$ity reduces pin limitations

on communications bandwidth.

A"D "ach :A+: offers a 1P: family comprising fi$e subfamilies called+ach. &ach +ach

de$ice consists of multiple PA%like blocks (or optimi8edPAs). +ach > and ? consist of

optimi8ed??K>5 PAs, +ach ; and H consist of se$eral optimi8ed ;HK>5 PAs,and +ach < is

similar to +ach ; and Hbut offers enhanced speed performance .All +ach chips use &&P*+

technology, and together the fi$e subfamilies pro$ide a wide range of selection ,from small,

ine0pensi$e chips to larger, state%of%the%art ones. 7e will focus on +ach H because it representsthe most ad$anced currently a$ailable parts in the family.

Figure (a) below depicts a +ach H chip, showing the multiple ;HK>5 PA%like blocks and the

interconnect, called the central switch matri0. The in%circuit programmable chips range in si8e

from5 to >5 PA%like blocks, corresponding roughly to ?,=== to


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connections between PA%like blocks (e$en from a PA%like block to itself) pass through the

central switch matri0. Thus, the de$ice is not merely a collection of PA%like blocks but a

single ,large de$ice. 'ince all connections tra$el through the same path, circuit timing delays arepredictable. Figure (b) illustrates a +ach H PA%like block. It has >5 outputs and a total of

;Hinputs (>5 of which are the fed%back outputs), so it corresponds to a ;HK>5 PA. !owe$er,

there are two key differences between this block and a normal PAM>) a product term (PT)

allocator between the A: plane and the macro cells (the macro cells comprise an * gate, an

&-* gate, and a flip%flop), and?) an output switch matri0 between the * gates and the I/

pins. These features make a +ach H chip easier to use because they decouple sections of the

PA%like block. +ore specifically, the product term allocator distributes and shares product

terms from the A: plane to * gates that re4uire them, allowing much more fle0ibility than

thefi0ed%si8e * gates in regular PAs. The output switch matri0 enables any macrocell output

(* gate or flip%flop)to dri$e any I/ pin connected to the PA%like block, again pro$iding

greater fle0ibility than a PA, in which each macro cell can dri$e only one specific I/ pin.

+ach Hs combination of in%system programmability and high fle0ibility allow easy hardware

design changes.

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A"D "ach 4 !'r)c')re

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FPGA De!ign Fo8:

The earlier P: and FPGA designs were performed largely by hand ut to%days

comple0 programmable logic de$ices re4uires the use of an integrated 1omputer%Aided :esign

(1A:) system. oth commercial 1A: tool $endors and FPGA companies offer appropriate

tools. For e0ample, traditional &lectronic :esign Automation (&:A) $endors such as 1adence,

+entor Graphics, 'ynopsys, and Kiew ogic etc. offer tools to support FPGA design. These

tools are typically used for the front%end design entry and simulation operations and pro$ide the

necessary interfaces to $endor%specific back%end tools for chip placement and routing.

&0amples of $endor specific tools are the -ilin0 -A1T system and the Altera

+A-@P3' II software.The Alteras +A-@P3' II software supports the entire design flow

on either P1 or workstation platforms.

The first step in the design process is the description of the logic circuit,which can be done

either by schematic capture tool or with oolean e0pressions.This is followed by a translation

that con$erts the original circuit description into a standard format used by the suitable 1A:

tools (&0M -II- 1A: tools).The circuit is then passed through 1A: programs that partition it

into appropriate logic blocks. 'elect a specific location in the FPGA for each logic block and

form the re4uired interconnections.( (1adence, Kiew ogic, r1A:, etc.)

The performance of the implemented circuit can then be checked and its functionality is

$erified.Finally a bitmap is generated and downloaded in a serial fashion to configure the FPGA.

Ini'ia De!ign En'r:The detailed description of the logic circuit are entered using a schematic

capture program. In the design entry phase, *T or schematic entry is used to create the logic to

be implemented in the de$ice. Pin assignments can also be made, including pin placement

information, and timing constraints that might be necessary for building a functioning design. In

the design entry step a schematic or lock :esign File (3+%() is created that is the top%le$el

design. The library of parameteri8ed modules (P+) functions are added and Kerilog !:

code is used to add a logic block.

The library may be either supplied by the $endor of the schematic capture program or any FPGA

$endor(ike -ilin0 or Altera etc.) .An alternate way to specify the logic circuit is to use a

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oolean e0pression or state machine language.This is done without the graphical interface.'ome

times it is possible to use a mi0ture of both schematic and oolean e0pressions.

Tran!a'ion 'o -NF Forma'M After the logic circuit is successfully designed and merged into

one circuit ,it is translated into a special format that is understood by the 1A: tools.Foe -ilin0this format is called -ilin0 net list format or -F.This translation utility is supported by the

-ilin0 or by the $endor of the logic entry tool.The translation process may also in$ol$e

automatic optimi8ations of the circuit.

Par'i'ion: The -F circuit is partitioned into logic cells (this partition is also known as

Technology +apping). This technology mapping con$erts the -F circuit which is a net list of

basic logic gates ,into a net list of -ilin0 logic cells.The logic cell used depends on which -ilin0

product the circuit is to be implemented in. -A1T tools also attempt to optimi8e the circuitduring this step. For e0ample, circuitry associated with unused logic block inputs or outputs is

eliminated from the design. In addition, the partitioning program attempts to minimi8e either the

total number of 1s used or the number of logic stages in the critical delay path. The mapping

procedure attempts to optimi8e the resulting circuit, either to minimi8e the total of logic cells

re4uired or the number of stages of logic cells in time critical circuitry.

Pace an% Ro)'e: This step is performed by using the 1A: tools, manually by the user or

mi0ture of the two. The first step is placement ,in which each logic cell generated during the

partition step is assigned to a specific location in the FPGA. Automatic placement can be done

using the simulated annealing algorithm.

After the placement ,the re4uired interconnections among the logic cells must be reali8ed by

selecting wire segments and routing switches within the FPGA interconnection resources.An

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automatic routing algorithm is used for this task which is based on +a8e routing algorithm.

Generally this routing and placement must be done automatically but sometimes it is done

manually by the user also. 7ith the physical placement and routing completed, e0act timing$alues can now be used to determine chip performance. The -A1T tools pro$ide a critical path

timing analy8er which pro$ides delay information on the longest through shortest paths through

the chip.In addition, the physical layout timing information can also be back%annotated to the

schematics to get more accurate functional simulation results. The final step in the -ilin0 design

flow is the creation of the IT file which contains the binary programming data needed to

configure the '*A+ bits of the target chip. This file is then downloaded to configure the chip

for final functional and timing tests of the programmed chip.

After creating the design it must be compiled. 1ompilation con$erts the design into a bitstream

that can be downloaded into the FPGA. The most important output of compilation is an '*A+

b2ect File (3!o(), which is used to program the de$ice. The software also generates other report

files that pro$ide information about the code as it compiles

In the design flow process the simulation is $ery important to learn, and there are entire

applications de$oted to simulating hardware designs. There are two types of simulation, *T and

timing. *T (or functional) simulation allows you to $erify that your code is place%and%route)

simulation $erifies that the design meets timing and functions appropriately in the de$ice.

After completion of the design ,its performance is checked either by downloading the

configuration bits into FPGA or by using an interface to a timing simulation program.If the

performance is not satisfactory ,suitable modifications are done at some point in the design

flow.nce the timing and functionality is $erified the implementation is complete.

%%%%%%%%%%%%%%%%%%%%%000000%%%%%%%%%%%%%%%%%%

Re(erence!:

13Field Programmable Gate Arrays 9 '.: rown, *.N.Francis et al

?.FPGA and 1P: Architectures M A Tutorial %'T&P!& *7 O NAT!A *'&.

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;.FPGA ArchitectureM 'ur$ey and 1hallenges %%Ian Duon>, *ussell Tessier and Nonathan *ose>

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Unit III Casestudies 131221124123 Phpapp02