Unit - 1

Introduction

Introduction

VLSI system evolution

Transistors 1950’s

Integrated circuits 1960’s

Microprocessors 1970’s

Digital signal processors 1980’s

FPGAs/ASICs 1990’s

System on chip (SOC) 2000

Moore’s Law

Gordon Moore: co-founder of Intel

Predicted that the number of transistors per chip would grow

exponentially (double every 18 months)

Exponential improvement in technology is a natural trend

Moore’s law

VLSI Design Styles

Full Custom

Application-Specific Integrated Circuit (ASIC)-semi custom

Programmable Logic (PLD, FPGA)

System-on-a-Chip

ASIC Explosion

About 30% of all the electronic equipments consist of

semiconductor components.

About 20% of all ICs are ASIC.

In the year 2000, the world production of semiconductor

components was for $ 300 bn.

This includes 300,000 ASIC designs.

Feature size which was 0.13µ in the year 2000 reached up

to 0.07µ in the year 2010.

Application Areas

Telecommunication and Networking

High-performance computing

Multi-media

Industrial controls and Robotics

Automotive

Energy Management

Medical Electronics

Defense and space appliances

Consumer Electronics and home appliances

These are all possible because of

1. Advances in fabrication technology

2. De linking of design and fabrication

3. Advances in CAD tools.

Development of HDL’s

The development of hardware description languages (HDLs)

played the key role in bringing about an efficient and a faster

implementation of VLSI chips than is possible with schematic

circuit diagram entry.

Advantages of the HDLs are:

Design cycle time reduces dramatically.

Provides a concise representation of the design in contrast to

the schematic logic diagrams.

No need for logic optimization using Karnaugh maps, etc.

Design is portable from one vendor platform to another.

Technology independent.

Development of HDLs

Verilog and VHDL are the most popular HDLs use presently.

Using the HDL, we will see that one can design digital circuits

ranging from SSIs to VLSIs.

VHDL will be used in this course to design VLSI digital

systems.

The design methodology adopted in this course is equally

applicable for Verilog as well.

Silicon - VLSI

Silicon is an abundant element, which occurs naturally in

the form of sand.

It can be refined using well established techniques of

purification and crystal growth.

Silicon also exhibits suitable physical properties for

fabricating active devices with good electrical

characteristics.

Silicon can be easily oxidized to form an excellent

insulator, SiO2 .

Silicon – VLSI contd..

The masking properties of silicon oxide allows the

electrical properties of silicon to be easily altered in

predefined areas.

Both active and passive elements can be built on the same

piece of material ( or substrate)

The components can then be interconnected using metal

layers to form a so called monolithic IC.

IC Fabrication Steps

Wafer preparation

Oxidation

Diffusion

Ion implantation

Chemical vapor deposition

Metallization

Photolithography

Packaging

Wafer preparation The material is grown as a single-crystal ingot.

It takes the form of a steel gray solid cylinder 10cm to

30cm in diameter and can be1m to 2m in length.

This crystal is then sawed to produce circular wafers that

are 400µm to 600µm thick.

The surface of the wafer is then polished to a mirror finish

using chemical and mechanical polishing (CMP)

techniques.

The basic electrical and mechanical properties of the wafer

depend on the orientation of the crystalline planes, as well

as the concentration and type of impurities present.

Wafer preparation contd..

It is also possible to control the conduction –carrier type, either

holes ( in p-type silicon) or electrons (in n-type silicon), that is

responsible for electrical conduction.

A heavily doped (low resistivity) n-type silicon wafer would be

referred to as n+ material, while a lightly doped region may be

referred as n-.

The ability to control the type of impurity and the doping

concentration in the silicon permits the formation of diodes,

transistors and resistors in flexible integrated circuit form.

Wafer

Oxidation

Oxidation refers to the chemical process of silicon reacting

with oxygen to form silicon dioxide (SiO2).

To speed up the reaction, it is necessary to use special high

temperature (e.g. 1000-1200oC) ultra clean furnaces.

Specially filtered air is circulated in the processing area, and all

personnel must wear special lint-free clothing.

The oxygen used in the reaction can be introduced either as a

high purity gas (in a process referred to as dry oxidation) or as

steam (for wet oxidation).

Oxidation It has dielectric constant of about 3.9 and can be used to form

excellent capacitors.

Silicon dioxide serves as an effective mask against many

impurities, allowing the introduction of dopants into the silicon

only in regions that are not covered with oxide.

Silicon dioxide is thin transparent film, and the silicon surface is

highly reflective.

If white light is shone on an oxidized wafer, constructive and

destructive interference will cause certain colors to be reflected.

The same principle is used by sophisticated optical inferometers

to measure film thickness.

Diffusion

Diffusion is the process by which atoms move from a high

concentration region to a low concentration region through the

semiconductor crystal.

In fabrication, diffusion is a method by which to introduce

impurity atoms (dopants) into silicon to change its resistivity.

The rate at which dopants diffuse in silicon is a strong function

of temperature.

Thus, for speed, diffusion of impurities is carried out at high

temperatures (10000C -12000C) to obtain the desired doping

profile.

Diffusion

When the wafer is cooled to room temperature, the impurities

are essentially “frozen” in position.

The diffusion process is performed in furnaces similar to those

used for oxidation.

The depth to which the impurities diffuse depends on both the

temperature and the time allocated.

By diffusing boron into an n-type substrate a pn junction

(diode) is formed.

Ion Implantation

An ion implanter produces ions of the desired dopant,

accelerates them by electric field, and allows them to strike the

semiconductor surface.

The ions become embedded in the crystal lattice.

The depth of penetration is related to the energy of the ion

beam, which can be controlled by the accelerating field voltage.

Since both voltage and current can be accurately measured

and controlled, ion implantation results in much more accurate

and reproducible impurity profiles that can be obtained by

diffusion.

Ion Implantation

In addition ion implantation can be performed at room

temperature. Ion implantation is normally used when

accurate control of the doping profile is essential for device

operation.

Chemical vapor deposition (CVD)

It is a process by which gases or vapors are chemically

reacted, leading to the formation of solids on a substrate.

CVD can be used to deposit various materials on a silicon

substrate including SiO2, SiN4 and polysilicon.

If silane gas and oxygen are allowed to react above a silicon

substrate, the end product, silicon dioxide, will be deposited as

a solid film on the silicon wafer surface.

The advantage of a CVD layer is that the oxide deposits at a

fast rate and low temperature (below 5000).

CVD If silane gas alone is used, then a silicon layer will be deposited

on the wafer.

If the reaction temperature is high enough (above 10000), the

layer deposited will be a crystalline layer. Such a layer is called

an epitaxial layer, and the deposition process is referred to as

epitaxy, rathar than CVD.

At lower temperatures, or if the substrate is not single crystal

silicon, the atoms will not be able to align in the same

crystalline direction. Such a layer is called polycrystalline

silicon (polysi), since it contains of many crystals of silicon

whose crystalline areas are oriented in random directions.

CVD

These layers are normally doped very heavily to form highly

conductive regions that can be used for electrical

interconnections.

Metallization

The purpose of metallization is to interconnect the various

components to form the desired integrated circuit.

Metallization involves the initial deposition of a metal over the

entire surface of the silicon.

The required interconnection pattern is then selectively etched.

The metal layer is normally deposited via a sputtering process.

Photolithography The surface geometry of the various integrated circuit components is

defined photographically. First the wafer surface is coated with

photosensitive layer called photo resist using a spin on technique.

After this a photographic plate with drawn patterns will be used to

selectively expose the photo resist under ultra-violet (UV) illumination.

The exposed areas will become softened and can be removed using a

chemical developer, causing the mask pattern to appear on the wafer.

The patterned photo resist layer can be used as a effective masking

layer to protect materials below from the wet chemical etching or

reactive ion etching.

After etching steps, the photo resist is stripped away leaving behind a

permanent pattern, an image of the photo mask, on the wafer surface.

Packaging A finished silicon wafer may contain several hundred or more

finished circuits or chips.

Each chip may contain from 10 to 108 or more transistors in a

rectangular shape, typically between 1mm and 10 mm on a side.

The circuits are first tested electrically using in automatic probing

station.

Bad circuits are marked for later identification and then separated

from each other (by dicing) and the good circuits (called dies) are

mounted in packages (or headers).

Fine gold wires are normally used to connect the pins of the

package to the metallization pattern on the die.

Finally the package is sealed using plastic or epoxy under vaccum

or in an inert atmosphere.

Integrated Resistors

Resistors in integrated form are not very precise.

They can be made from various diffusion regions.

The basic technique for obtaining a resistor in integrated

circuit is by utilizing the bulk resistance of a define volume of

semiconductor region

Four different methods are available for fabricating integrated

resistors namely

Diffused resistor, Epitaxial resistor, pinched resistor and thin

film resistor.

Integrated Resistors

Integrated Capacitors Three types of capacitor structure are available in cmos process.

Mos , Interpoly (MIM-metal insulator metal ), Junction capacitor

Mos capacitor:

The Mos gate capacitance is basically the gate to source

capacitance of a MOSFET.

The capacitance value is dependent on the gate area.

The oxide thickness is same as the gate oxide thickness in the

MOSFETS.

This capacitor exhibits a large voltage dependence. To eliminate

this problem, an additional n+ implant is required to form at the

bottom plate of the capacitor.

Integrated capacitors

Interpoly:

The inter poly capacitor exhibits near ideal characteristics but

at the expense of the inclusion of a second poly silicon layer to

the cmos process.

Since the capacitor is placed on top of the thick field oxide,

parasitic effects are kept to a minimum.

Integrated capacitors

Junction capacitor:

Any PN junction under reversed bias produces a depletion

region that acts as a dielectric between the P and N regions.

This type of capacitor is often used as a varactor for tuning

circuits.

This capacitor works only with reverse bias voltages.

Integrated capacitors

Integration of Technologies

Although the silicon technology is continuously evolving to

produce smaller systems with minimized power dissipation,

eventually the integration of multiplicity of technologies will be

driving force that will create unprecedented opportunities for

realization of new systems.

Integration of Technologies

Metal oxide semiconductor (MOS) VLSI

Technology

Within the bounds of MOS technology, the possible circuit

realizations may be based on

PMOS , NMOS, CMOS and BiCMOS.

CMOS is the dominant technology.

NMOS Technology

NMOS devices are formed in a p-type substrate of moderate

doping level.

The source and drain regions are formed by diffusing n-type

impurities through suitable masks into these areas to give the

desired n-impurity concentration and give rise to depletion

regions which extend mainly in the more lightly doped p-

region.

The source and drain are isolated from one another by two

diodes.

Connections to the source and drain are made by a deposited

metal layer.

Basic MOS Transistor

Enhancement mode MOSFET

A poly silicon gate is deposited on a layer of insulation over the

region between the source and drain.

In a basic enhancement mode device channel is not established

and the device is in a non-conducting condition VD=VS=Vgs=0.

If this gate is connected to a suitable positive voltage with

respect to source, then the electric field established between the

gate and the substrate gives rise to a charge inversion region in

the substrate under the gate insulation and a conducting path or

channel is formed between the source and drain.

Depletion mode MOSFET

The channel may also be established so that it is present under

the condition Vgs=0 by implanting suitable impurities in the

region between source and drain during manufacture and prior

to depositing the insulation and the gate.

Under these circumstances, source and drain are connected by

conducting a channel, but the channel may now be closed by

applying a suitable negative voltage to the gate.

In both cases, variations of the gate voltage allow control of

any current flow between source and drain.

Depletion MOSFET

NMOS fabrication

Processing is carried out on a thin wafer cut from a single

crystal of silicon of high purity into which the required p-

impurities introduced as the crystal is grown.

Such wafers are typically 75 to 150mm in diameter and

0.4mm thick and are doped with say boron to impurity

concentrations of 1015/cm3, giving resistivity in the

approximate range 25Ω/cm to 2Ω/cm.

A layer of silicon dioxide, typically 1µm thick, is grown all over

the surface of the wafer to protect the surface, act as a barrier

to dopants during processing and provide a generally

insulating substrate onto which other layers may be

deposited and patterned.

NMOS fabrication

The surface is now covered with a photoresist which is

deposited onto the wafer and spun to achieve an even

distribution of the required thickness.

NMOS fabrication

The photoresist layer is then exposed to UV light through mask

which defines those regions into which diffusion is to take

place together with transistor channels.

NMOS fabrication

These areas are subsequently readily etched away together with

the underlying silicon dioxide so that the wafer surface is

exposed in the window defined by the mask.

NMOS fabrication

The remaining photo resist is removed and a thin layer of SiO2

(0.1µm typical) is grown over the entire chip surface and then

polysilicon is deposited on top of this to form the gate structure.

The poly silicon layer consists of heavily doped poly silicon

deposited by chemical vapor deposition.

NMOS fabrication

Photo resist coating and masking allows the poly silicon to be

patterned, and then the thin oxide is removed to expose areas into

which n-type impurities are to be diffused to form the source and

drain.

Diffusion is achieved by heating the wafer to a high temperature and

passing a gas containing the desired n-type impurity over the surface.

NMOS fabrication

Thick oxide (SiO2) is grown over all again and is then masked with photo

resist and etched to expose selected areas of polysilicon gate and the drain

and source areas where concentrations are to be made.

NMOS fabrication

The whole chip is then has metal (alluminium) deposited over its

surface to a thickness typically of 1µm. This metal layer is then

masked and etched to form the required interconnection pattern.

NMOS fabrication

Summary of NMOS process Processing takes place on a p-doped silicon crystal wafer on

which is grown a thick layer of SiO2. Mask-1: Pattern SiO2 to expose the silicon surface in areas

where paths in the diffusion layer or source, drain or gate areas of transistors are required. Deposit thin oxide over all. For this reason, this mask is often known as the thinox mask (diffusion mask).

Mask-2: Pattern the ion implantation within the thinox region where depletion mode devices are to be produced.

Mask-3: Deposit poly silicon over all (1.5µm thick typically) then pattern using mask 3. Using the same mask, remove thin oxide layer where it is not covered by poly silicon. Diffuse n+ regions into areas where thin oxide has been removed.

Mask-4: Grow thick oxide over all and then etch for contact cuts. Mask-5: Deposit metal and pattern with mask 5. Mask-6: It would be required for the over glossing process step.

CMOS fabrication

Different approaches to CMOS fabrication are

1. P-well

2. N-well

3. Twin tub or Twin well

4. SOI- silicon on insulator

P-well process

In primitive terms, the structure consists of an n-type substrate

in which p-devices may be formed by suitable masking ad

diffusion and, in order to accommodate n-type devices, a deep

p-well is diffused into the n-type substrate.

P-well process

The diffusion must be carried out with special care since the p-

well doping concentration and depth will affect the threshold

voltages. We need either deep well diffusion or high well

resistivity.

P-well process

The p-wells acts as substrate for the n-devices within the parent n

substrate, and provided the voltage polarity restrictions are

observed, the two areas are electrically isolated.

Summary of p-well process

Mask-1: Defines the areas in which the deep p-well diffusions

are to take place.

Mask-2: Defines the thinox regions, namely those areas where

the thick oxide is to be stripped and thin oxide grown to

accommodate p and n transistors and diffusion wires.

Mask-3: Used to pattern the polysilicon layer which is

deposited after the thin oxide.

Mask-4: A p plus mask is now used to define all areas where p

diffusion is to take place.

Mask-5: This is usually performed using the negative form of

the p-plus mask and, with mask-2, defines those areas where n-

type diffusion is to take place.

P-well process

Mask-6 : Contact cuts are now defined.

Mask-7: The metal layer pattern is defined by this mask.

Mask-8: An over all passivation (overglass) layer is now

applied and mask 8 is needed to define the openings for access

to bonding pads.

CMOS p-well inverter showing VDD and VSS substrate connections

N-well Process

N-well CMOS circuits are also superior to p-well because of the

lower substrate bias effects on transistor threshold voltage and

inherently lower parasitic capacitances associated with source

and drain regions.

N-well fabrication steps

Cross sectional view of n-well CMOS inverter

Twin tub process

Twin tub fabrication is a logical extension of p-well and n-well

approaches.

A high resistivity of n-type material is taken and then both n-

well and p-well are created in it.

Bi-CMOS technology

Bi-polar transistors provide higher gain.

The deficiency of MOS technology lies in the limited load

driving capabilities of MOS transistors. This is due to the

limited current sourcing and current abilities associated

with both p and n transistors.

Bi-CMOS gates may be an affecting way of speeding up

VLSI circuits.

Bi-CMOS technology