Ultra-Low Loss 600V – 1200V GaN Power Transistors for

High Efficiency Applications David C. Sheridan, D.Y. Lee, Andrew Ritenour, Volodymyr Bondarenko, Jian Yang, and Charles Coleman, RFMD Inc., USA, david.sheridan@rfmd.com

Abstract

An emerging generation of high voltage (600V – 1200V) GaN HEMTs are compared to the best in class existing technologies and are shown to maintain a significant advantage in switching performance. Compared to the latest available GaN and Si superjunction MOSFET at 650V, these GaN devices show > 5X lower switching energies with an Ron*Qg product less than 1 nC*Ω. These GaN devices are extended to show > 1200V breakdown voltages and have switching losses 4X lower than even SiC MOSFETs with similar ratings.

1. Introduction Many publications have shown demonstrations of the potential of high voltage GaN devices, but few have shown direct switching performance or measured comparisons with state of the art Si/SiC devices. Recent developments in both Si and SiC devices have significantly increased the performance level of power switching devices in the 600V to 1200V class. In the last year alone, new commercial 650V Si superjunction [1] and 1200V SiC MOSFETs [2] have been announced with near 2X increase in key figures of merit from previous generations. In this work, we will compare the ultra-low gate charge and switching energy advantages of the 650V-1200V rGaN HV process with these new devices as well as published GaN device results. GaN HEMTs can be fabricated on both SiC and Si substrates although the underlying epitaxy process can be significantly different. For high voltage GaN:SiC devices, the thinner epitaxy structure and insulating substrate results in significantly higher manufacturing throughput, thermal conductivity, packaging flexibility, and ideally lower defectivity and higher performance. Alternatively, high voltage GaN HEMTs on Si substrates require much thicker and more complex epitaxy processing along with the performance limitations of a conducting substrate, but the future promise of low cost 200-300mm substrates capable of 600V-1200V class devices drives most of the development efforts towards the Si alternative.

Fig. 1: Technology comparison plot showing rGaN:SiC technology progression (red diamonds) and rGaN:Si

(red star).

2. 650V GaN Device Performance and Comparisons Our GaN:SiC and GaN:Si HEMT technology have shown Rds,on*BV values that have far exceeded Si devices, and are now rivalling best in class SiC results (Figure 1). GaN:SiC devices for 650V applications have been measured to have specific on-resistance Rds,on(sp) values < 2mΩ-cm2, while the initial GaN:Si devices have Rds,on(sp) ~ 2.8mΩ-cm2 with breakdown voltages exceeding 1300V. The depletion mode GaN HEMTs have considerable benefits over enhancement mode HEMT devices, especially when operated in the typical cascode arrangement (Figure 2). Other than transforming the normally-on device into a normally-off switch, the cascoded low voltage MOSFET has the well known benefits of the low Qrr body diode and the low Qg of a robust LV MOS gate structure.

Typical I-V characteristics of the 650V / 45mΩ GaN cascode configuration integrated into a standard TO-247 package are shown in Figure 3. The low on-resistance is critical for high efficiency applications where switching frequencies are in the 50kHz – 100kHz range. However, it is well known that GaN HEMTs can suffer from a dynamic increase in on-resistance when switching from a high voltage blocking state to a low resistance on-state [3]. This dynamic on-resistance then results in system losses exceeding theoretical loss calculations when using datasheet DC values. In order to characterize the GaN HEMTs for dynamic on-resistance effects, we used a standard resistive switching test setup measuring IDS through a current probe and VDS,on of the switch via a custom clipping circuit that is design to limit the high voltage stress to saturate the voltage probes similar to [4]. Since the dynamic on-resistance can have multiple time constants that can affect the dynamic behaviour, the testing included a high voltage soaking time of 2 minutes at 400V followed by 6 PWM pulses at 40kHz. The calculated on-resistance was determined from the measured ID and VDS,on values and normalized to the calculated on-resistance values of the same test at low VDS.

2.1. Dynamic On-Resistance

Figures 4-5 show the resulting dynamic on-resistance test waveforms for several generations of GaN HEMT devices. While the effect is difficult to completely eliminate during high voltage operation, these results show that with careful optimization of materials, design, and processing, it can be minimized to acceptable levels. Both the GaN:SiC and GaN:Si devices show less than 10% increase in the dynamic resistance down to timescales less

Fig. 2: Schematic of cascode structure and TO-247 package used in this work.

Fig. 3: Output curves of a 650V / 45mΩ GaN integrated cascode switch.

than 1uS. Importantly, the dynamic on-resistance did not increase at elevated temperatures as critical trap dynamics accelerate.

2.2. Switching Characterization

While conduction losses in this range can be addressed with other technologies, the small die size and device design enables very low capacitance and fast switching speed. Cascoded devices in a TO247 were measured in an optimized double pulse inductive load test board. Figures 6-7 show the extremely low switching losses for a 650V/45mΩ device due to the integrated cascode structure that is not degraded due to lack of Kelvin connection even with dV/dt’s near 100V/ns.

As shown in Figure 6, the inductive turn-on transition is extremely fast even with the additional current probe’s parasitic inductance resulting in a higher than typical turn-on current peak. Eoff waveform shows no continuous oscillation behaviour due to proper sizing of the MOSFET/HEMT capacitances and optimized layout. It should also be noted that no

Fig. 4: Plot of the dynamic on-resistance of GaN:SiC device. Curve is calculated ratio of measured VDS/IDS immediately after turn-on

transition and after 2 minutes 400V soaking time.

Fig. 5: Plot of the dynamic on-resistance of GaN:Si device. Curve is calculated ratio of measured VDS/IDS immediately after turn-on

transition and after 2 minutes 400V soaking time.

Fig. 6: Measured inductive turn-on waveforms for the 650V / 45mΩ GaN integrated cascode with

Eon=4µJ. VGS=0V-10V, ID=19A, Rg=1Ω.

Fig. 7: Measured inductive turn-off waveforms for the 650V / 45mΩ GaN integrated cascode with

Eoff=11µJ. VGS=10V-0V, ID=20A, Rg=1Ω.

external snubber was needed to further dampen the fast transient waveforms. Total

switching losses are only 20µJ at VDD=400V and ID=10A, 5X lower than measured results on the latest 45mΩ superjunction device [1] or published 150mΩ GaN cascode results [5] (Figure 8). Additionally, the benefits of the fast Qrr body diode and low Qg are well known.

2.3. Boost Converter Performance To demonstrate the benefits of the 650V GaN switch, a 2.4kW boost converter was designed and evaluated (Figure 9). The converter has an input voltage range from 180 VDC to 240VDC with a regulated output voltage of 386V using a NCP1654BD133R2G PWM controller at a fixed switching frequency

of 133kHz. Operation of the converter is continuous conduction mode (CCM) except for extreme light load conditions. For dedicated analysis of the effect of switch technology on converter efficiency, a 600V 10A SiC Schottky was used in the boost diode position. Table 1. Comparison of state-of-the-art superjunction MOSFETs with a 650V rGaN cascode.

IPW65R045C7 STW69N65M5 RFSJ3006F Breakdown Voltage 650 V 650 V 650 V

On-Resistance 45 mΩ 45 mΩ 45 mΩ Co(er) 146 pF 146 pF 58 pF

Eoss @ 400V 12 uJ 13 uJ 5 uJ Qg,typ (0-10V) 93 nC 143 nC 21 nC

Qrr 13 uC 16 uC 0.04 uC Ron * Qg 4.2 6.4 0.95

The 45mΩ/650V GaN HEMT (RFJS3006F) was tested and compared with the latest generations of 650V Si superjunction devices with similar on-resistance ratings. Table 1 gives a comparison of the key device parameters for each of the evaluation transistors. For equivalent on-resistance, the GaN device has 4-7X less Qg, 300X lower Qrr, and >2X lower Eoss (0V – 400V). The lower Eoss of the GaN switch will give better light load efficiency especially in soft switching resonant topologies, while the lower Qg and overall lower capacitances translate to reduced hard switching losses across the whole output power range. Efficiency measurements were obtained using a PW3337 power meter while the output was varied using a suitable electronic load. Efficiency comparison results are shown in Figure 10. As expected from the comparison of device parameters in Table 1, the 45mΩ GaN cascode switch had the highest peak efficiency at 1.6kW output power of 98.7%, 0.4% higher than the C6 device, and 0.3% higher than the latest generation C7. This leads to a savings of up to 13W at peak output power.

Fig. 8: Comparison of measured 650V rGaN

cascode vs 45mΩ Si MOSFET [1] and published 150mΩ GaN cascode [5].

At light loads the efficiency gain for the GaN switch is even greater due to the savings in switching losses combined with fixed PWM frequency. At the lowest output power of 400W, the GaN switch achieves almost 1% efficiency gain over the C6 devices and almost 0.7% over the new C7. Since the PWM frequency was chosen to highlight the benefits of GaN technology in emerging power supply designs where higher frequencies enable density and cost savings, loss calculations have shown that peak efficiencies of 99% for this converter is possible with the substitution of the boost SiC Schottky diode with a GaN based synchronous rectifier [6].

3. Long Term Operation Critical to new technology success is reliability including stability of device performance over long periods of operation. While JEDEC testing is mandatory, application specific tests for these devices give confidence in real-world operating conditions. To test the 650V / 45mΩ GaN cascode devices, a SEPIC DC/DC converter (Figure 11) was designed to demonstrate long term operation under maximum operating conditions. The SEPIC converter is an ideal topology for long term operation due to a) the ability to recirculate the output power to the input, requiring only the losses to be supplied by the input supply, and b) impose 2X the input voltage onto the switch for maximum stress conditions. Others have used this configuration for transistor demonstration purposes [7]. The input voltage to the SEPIC converter was set at 200V DC with a PWM frequency of 108kHz and ~ 50% duty cycle to control the output voltage at a similar 200V. In this configuration the peak switch voltage is 400V and turn-off current is 20A. A thermistor embedded into the heatsink was used to control the cooling fan operation in order to maintain device near maximum junction temperature (TJ,max) of 150oC. Figure 12 shows key IDSS and RDS,on changes of the GaN device after 1000hrs and 3000hrs of operation in the converter. After 3000hrs there is only a 4% change in the device on-resistance, and a 30% reduction in leakage current measured at 650V. This demonstrates the potential for long term operating life of GaN devices under typical application modes and related stresses.

Fig. 9: 2.4kW boost converter evaluation board.

VIN = 200V, VOUT =386V, fsw=133kHz. Fig. 10: Measured efficiency at VIN=200V for 650V / 45mΩ rated GaN and Si superjunction

devices.

4. 1200V GaN Devices

While 650V is likely the first entry for GaN power devices for server and telecom applications, 1200V devices are required for applications such high voltage DC/DC converters and solar inverters. Performance of GaN devices at these high voltages has not been widely reported. Using the same base technology as the 650V products, 1200V die were fabricated with breakdown voltages exceeding 1500V as suitable margin for overvoltage protection (Figure 13). Figure 14 shows the output characteristics of a 100mΩ / 1200V integrated cascode using the same configuration as the 650V devices in the previous section. Since superjunction technology is not yet capable of 1200V devices, the switching performance was compared to similarly rated 1200V SiC MOSFETs [2] which have already shown performance advantages over Si IGBTs.

Fig. 11: SEPIC converter used for long term HTOL measurements of the TO-247

650V / 45mΩ GaN cascode.

Fig. 12: Measured RDS,on and IDSS parameters at 0,1000, and 3000 hrs during HTOL testing in the SEPIC

converter.

Fig. 13: 1500V breakdown measurement of rGaN

HEMT used in 1200V cascode switching measurements.

Fig. 14. Output characteristics of ~100mΩ / 1200V GaN Cascode used in switching tests.

A comparison of the switching energies is shown in Figure 15. At VDD=600V (test system limitation) and ID=15A, the GaN cascode has >70% lower switching losses than the SiC MOSFETs at VDD=600V (SCH2080KE) VDD=800V and ID=15A. Even for adjusted VDD, the 1200V GaN HEMT cascode has considerably lower losses. For resonant topologies, power lost in the output capacitance accounts for most of the switch losses. Due to the unique structure in GaN devices, the key output Eoss metric (Figure 16) can show appreciable improvement in these applications.

5. Summary It has been shown that high voltage GaN devices up to 1200V have the potential to offer even greater performance advantages over best in class Si and SiC devices in both soft- and hard-switching applications. The lower Qg, Qrr, and Eoss of the GaN devices compared to Si superjunction devices allow ease of operation, reduced losses, and can enable new emerging topologies for higher efficiency systems.

6. Reference [1] E. Vecino, F. Stuckler, M. Pippan, and J. Hancock, First generation of 650V super junction devices

with Rds(on)*A values below 1ohm-mm2, proc. PCIM Europe, 2013, pp. 621-628. [2] http://www.cree.com; C2M0080120D [3] W. Saito, T. Nitta, Y. Kakiuchi, Y. Saito, K. Tsuda, I. Omura, M. Yamaguchi, Suppression of

Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure, Electron Devices, IEEE Transactions on , vol.54, no.8, pp.1825,1830, Aug. 2007

[4] B. Lu, T. Palacios, D. Risbud, S. Bahl, and D.I. Anderson, Extraction of Dynamic On-Resistance in GaN Transistors: Under Soft- and Hard-Switching Conditions, Compound Semiconductor Integrated Circuit Symposium (CSICS), 2011 IEEE , vol., no., pp.1,4, 16-19 Oct. 2011

[5] R. Mitova, A. Dentela, M. Wang, R. Ghosh, U. Mhakar, and D. Klikic, Half bridge inverter with 600V GaN power switches, proc. PCIM Europe, 2013, pp. 49-56.

[6] J. Yang, Efficiency Improvement with GaN-Based SSFET as Synchronous Rectifier in PFC Boost Converter, proc. PCIM Europe, 2014.

[7] B. Callanan, and J. Rice, SiC MOSFETs under High-Frequency Hard Switched Conditions, Power Electronics Europe, Issue 4, pp. 31-34, 2012.

Fig. 15. Measured Etotal comparison of a 1200V

GaN cascode with two 80mΩ SiC MOSFEs. Fig. 16. Comparison of store energy (Eoss) in the

device output capacitance for 1200V devices.