UCC28950 600-W,Phase-Shifted,Full-Bridge Application Report...(LMAG). The following equations calculate the minimum magnetizing inductance of the primary of the transformer (T1) to

Application ReportSLUA560B–September 2010–Revised October 2010

UCC28950 600-W, Phase-Shifted, Full-BridgeApplication Report

Michael O'Loughlin ..........................................................................................................................

1 Introduction

In high-power server applications to meet high-efficiency and green standards some power-supplydesigners have found it easier to use a phase-shifted, full-bridge converter. This is because thephase-shifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converterreducing switching losses, and EMI and increasing overall efficiency. The purpose of this applicationreport is to review the design of the 600-W, phase-shifted, full-bridge converter for one of these powersystems, using TI’s new UCC28950 Phase-Shifted, Full-Bridge Controller, and was based on typicalvalues. In a production design the values need to be modified for worst case conditions. Hopefully thisinformation will aid other power supply designers in their efforts to design an efficient phase-shifted,full-bridge converter. Also note there is a MathCAD Design Tool, (TI Literature Number SLUC210), thatgoes along with this application note as well.

Table 1. Design Specifications

DESCRIPTION MIN TYP MAX

Input Voltage 370 V (VINMIN) 390 V (VIN) 410 V (VINMAX)

Output Voltage 11.4 V 12 V (VOUT) 12.6 V

Allowable Output Voltage Transient 600 mV (VTRAN)

Load Step, 90%

Output Power 600 W (POUT)

Full Load Efficiency 93% (η)

Inductor (LOUT) Switching Frequency 200 kHz (fS)

1SLUA560B–September 2010–Revised October 2010 UCC28950 600-W, Phase-Shifted, Full-Bridge Application ReportSubmit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

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V IN

+

_

CT

QB

QE QF

C IN

RRE

DA

RS

QA

Q D

QC

T1

LOUT

VOUT

+

_

COUT

UCC28950

OUTE

RSUM

COMP

SS/EN

SYNC

VREF

TMIN

VDD

OUTA

OUTC

OUTD

OUTB

GND

EA+

DELCD

DELEF

EA-

CS

ADEL

ADELEF

OUTF

DELAB

DCM

RT

C BP1

R ARB

RI

RC

C P

RF

CZ

V OUT

1

2

3

4

5

6

7

8

9

10

11

12

OUTE

23

22

21

20

19

18

17

16

15

14

13

CSS

RDELAB

RDELCD

RDELEF

RTMIN

RSUM

RT

RE

OUTF

OUTA

OUTB

OUTC

OUTD

24

OUTA

OUTB

OUTC

OUTD

OUTE

OUTF

CS

CS

CLF

330pF

RLF2

1k

CBP2

1uF

12V Bias

SYNC

VREF

VREF

RG

VREF

LS

RD

825k

RLF1

22 ohm

D B

DC

QBd QD

d

1uF

RDA1

RDA2

RCA1

RCA2

BUDGET OUT

1P P 45.2W

æ ö- h= ´ »ç ÷hè ø

Functional Schematic www.ti.com

2 Functional Schematic

Figure 1. UCC28950 Phase-Shifted, Full-Bridge Functional Schematic

3 Power Budget

To meet the efficiency goal a power budget needs to be set.

(1)

2 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B–September 2010–Revised October 2010Submit Documentation Feedback


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P

S

Na1

N=

RDSONV 0.3 V=

P

S

Na1

N=

( )INMIN RDSON MAX

OUT RDSON

V 2 V Da1 21

V V

- ´ ´= »

+

a1 21=

( )( )

OUT RDSON

TYP

IN RDSON

V V aD 0.66

V 2 V

+ ´= »

- ´

OUT

LOUT

OUT

P 0.2I 10 A

V

´D = =

IN TYP

MAG

LOUT

S

V (1 D )L 2.76mH

I 0.5f

a1

´ -³ »

D ´´

www.ti.com Preliminary Transformer Calculations (T1)

4 Preliminary Transformer Calculations (T1)

Transformer turns ratio (a1):

(2)

Estimated FET voltage drop (VRDSON):

(3)

Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will givesome room for dropout if a PFC front end is used.

(4)

(5)

Turns ratio rounded to the nearest whole turn.

(6)

Calculated typical duty cycle (DTYP) based on average input voltage.

(7)

Output inductor ripple current is set to 20% of the output current.

(8)

Care needs to be taken in selecting a transformer with the correct amount of magnetizing inductance(LMAG). The following equations calculate the minimum magnetizing inductance of the primary of thetransformer (T1) to ensure the converter operates in current-mode control. If LMAG is too small themagnetizing current could cause the converter to operate in voltage mode control instead of peak-currentmode control. This is because the magnetizing current is too large, it will act as a PWM ramp swampingout the current sense signal across RS.

(9)



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IPRIMAY

0A

0A

IQF

0A

IQE

IPS

IMS

QEg

On

Off

QFg

On

Off

IPP

IMP

D

IMP2

IMS2

( )MP2 PP LOUTI I I / 2 a1» -D ´

MS2 PS LOUTI I I /2» -D

LOUTI /2D

Preliminary Transformer Calculations (T1) www.ti.com

Figure 2 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents withrespect to the synchronous rectifier gate drive currents. Note that IQE and IQF are also T1’s secondarywinding currents as well. Variable D is the converters duty cycle.

Figure 2. T1 Primary and QE and QF FET Currents



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OUT LOUT

PS

OUT

P II 55 A

V 2

D= + »

OUT LOUT

MS

OUT

P II 45 A

V 2

D= - »

LOUTMS2 PS

ΔII I 50 A

2= - »

( )2

PS MSMAX

SRMS1 PS MS

I IDI I I 29.6 A

2 3

é ù-æ öê ú= ´ + »ç ÷

è ø ê úë û

( )2

PS MS2MAX

SRMS2 PS MS2

I I1 DI I I 20.3 A

2 3

é ù--æ öê ú= ´ + »ç ÷

è ø ê úë û

LOUT MAX

SRMS3

I 1 DI 1.1A

2 2 3

D -æ ö= »ç ÷´è ø

2 2 2

SRMS SRMS1 SRMS2 SRMS3I I I I 36.0 A= + + »

INMIN MAX

LMAG

MAG S

V DI 0.47 A

L f

´D = »

´

OUT LOUT

PP LMAG

OUT

P I 1I I 3.3 A

V 2 a1

æ öD= + + D »ç ÷

´ hè ø

( ) ( )2PP MP

PRMS1 MAX PP MP

I II D I I 2.5 A

3

é ù-ê ú= ´ + »ê úë û

LOUT

MP2 PP

I 1I I 3.0 A

2 a1

Dæ ö= - »ç ÷

è ø

www.ti.com Preliminary Transformer Calculations (T1)

Calculate T1 secondary RMS current (ISRMS):

(10)

(11)

(12)

Secondary RMS current (ISRMS1) when energy is being delivered to the secondary:

(13)

Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF areboth on.

(14)

Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding duringfreewheeling period, please refer to Figure 2.

(15)

Total secondary RMS current (ISRMS):

(16)

Calculate T1 Primary RMS Current (IPRMS):

(17)

(18)

(19)

(20)



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( ) ( )2PP MP

PRMS1 MAX PP MP

I II D I I 2.5 A

3

é ù-ê ú= ´ + »ê úë û

( ) ( )2

PP MP2

PRMS2 MAX PP MP2

I II 1 D I I 1.7 A

3

é ù-ê ú= - ´ + »ê úë û

2 2

PRMS PRMS1 PRMS2I I I 3.1A= + »

a1 21=

MAGL 2.8mH=

LKL 4 H= m

PDCR 0.215= W

SDCR 0.58= W

( )2 2

T1 PRMS P SRMS SP 2 I DCR 2 I DCR 7.0 W» ´ ´ + ´ ´ »

BUDGET BUDGET T1P P P 38.1W= - »

Preliminary Transformer Calculations (T1) www.ti.com

T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary.

(21)

T1 Primary RMS (IPRMS2) current when the converter is free wheeling.

(22)

Total T1 primary RMS current (IPRMS)

(23)

For this design a Vitec transformer was selected part number 75PR8107 that had the followingspecifications.

(24)

(25)

Measure leakage inductance on the Primary:

(26)

Transformer Primary DC resistance:

(27)

Transformer Secondary DC resistance:

(28)

Estimated transform losses (PT1) are twice the copper loss.

NOTE: This is just an estimate and the total losses may vary based on magnetic design.

(29)

Calculate remaining power budget:

(30)



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ds(on)QAR 0.220= W

OSS _ QA _ SPECC 780pF=

dsQAV 25 V=

dsQA

OSS _ QA _ AVG OSS _ QA _ SPEC

INMAX

VC C 193pF

V= »

gQA 15nC=

gV 12V=

2

QA PRMS ds(on)QA g g

fsP I R 2 QA V 2.1W

2= ´ + ´ ´ ´ »

BUDGET BUDGET QAP P 4 P 29.7 W= - ´ »

www.ti.com QA, QB, QC, QD FET Selection

5 QA, QB, QC, QD FET Selection

In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineonwere chosen for QA..QD.

FET drain to source on resistance:

(31)

FET Specified COSS:

(32)

Voltage across drain-to-source (VdsQA) where COSS was measured, data sheet parameter:

(33)

Calculate average Coss [2]:

(34)

QA FET gate charge:

(35)

Voltage applied to FET gate to activate FET:

(36)

Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg):

(37)

Recalculate power budget:

(38)



Administrator

Underline

Administrator

Underline

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( )2

INMAX

S OSS _ QA _ AVG LK2

LOUTPP

VL 2 C L 26 H

II

2 2 a1

³ ´ - » mDæ ö

-ç ÷´è ø

SL 26 H= m

LSDCR 27m= W

2

LS PRMS LSP 2 I DCR 0.5 W= ´ ´ »

BUDGET BUDGET LSP P P 29.2W= - »

Selecting LS www.ti.com

6 Selecting LS

Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltageswitching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switchnode. The following equation selects LS to achieve ZVS at 100% load down to 50% load based on theprimary FET’s average total COSS at the switch node.

NOTE: There may be more parasitic capacitance than was estimated at the switch node and LS

may have to be adjusted based on the actual parasitic capacitance in the final design.

(39)

For this design a 26-µH Vitec inductor was chosen for LS, part number 60PR964. The shim inductor hadthe following specifications.

(40)

LS DC Resistance:

(41)

Estimate LS power loss (PLS) and readjust remaining power budget:

(42)

(43)



Administrator

Underline

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OUT

LOUT

OUT

P 0.2 600 W 0.2I 10 A

V 12V

´ ´D = = »

OUT TYP

OUT

LOUT s

V (1 D )L 2 H

I f

´ -= » m

D ´

2 2

OUT LOUT

LOUT _ RMS

OUT

P II 50.3 A

V 3

æ ö Dæ ö= + =ç ÷ ç ÷

è øè ø

OUTL 2 H= m

LOUTDCR 750= mW

2

LOUT LOUT _ RMS LOUTP 2 I DCR 3.8 W= ´ ´ »

BUDGET BUDGET LOUTP P P 25.4 W= - »

www.ti.com Output Inductor Selection (LOUT)

7 Output Inductor Selection (LOUT)

Inductor LOUT was designed for 20% inductor ripple current (∆ILOUT):

(44)

(45)

Calculate output inductor RMS current (ILOUT_RMS):

(46)

A 2-µH inductor from Vitec Electronics Corporation, part number 75PR108, was chosen for this design.The inductor had the following specifications.

(47)

Output inductor DC resistance:

(48)

Estimate output inductor losses (PLOUT) and recalculate power budget. Note PLOUT is an estimate ofinductor losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It isadvisable to double check the magnetic loss with the magnetic manufacture.

(49)

(50)



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OUT OUT

OUT

HU

OUT

L P 0.9

Vt 7.5 s

V

´ ´

= = m

TRAN

COUT

OUT

OUT

V 0.9ESR 12m

P 0.9

V

´£ = W

´

OUT HU

OUT

OUT

TRAN

P 0.9 t

VC 5.6mF

V 0.1

´ ´

³ »´

LOUT

COUT _ RMS

II 5.8 A

3

D= »

n 5=

OUTC 1500 F n 7500 F= m ´ » m

COUT

31mESR 6.2m

n

W= = W

2

COUT COUT _ RMS COUTP I ESR 0.21W= ´ »

BUDGET BUDGET COUTP P P 25.2W= - »

Output Capacitance (COUT) www.ti.com

8 Output Capacitance (COUT)

The output capacitor is being selected based on holdup and transient (VTRAN) load requirements.

Time it takes LOUT to change 90% of its full load current:

(51)

During load transients most of the current will immediately go through the capacitors equivalent seriesresistance (ESRCOUT). The following equations are used to select ESRCOUT and COUT based on a 90% loadstep in current. The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the outputcapacitance (COUT) is selected for 10% of VTRAN.

(52)

(53)

Before selecting the output capacitance it is also required to calculate the output capacitor RMS current(ICOUT_RMS).

(54)

To meet our design requirements five 1500-µF, aluminum electrolytic capacitors were chosen for thedesign from United Chemi-Con, part number EKY-160ELL152MJ30S. These capacitors had an ESR of 31mΩ.

Number of output capacitors:

(55)

Total output capacitance:

(56)

Effective output capacitance ESR:

(57)

Calculate output capacitor loss (PCOUT):

(58)

Recalculate remaining Power Budget:

(59)



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gQE 152nC=

ds(on)QER 3.2m= W

INMAX

dsQE

VV 19.5 V

a1= »

ds _ specV 25 V=

OSS _ SPECC 1810pF=

dsQE

OSS _ QE _ AVG OSS _ SPEC

ds _ spec

VC C 1.6nF

V= »

QE _ RMS SRMSI I 36.0 A= =

www.ti.com Select FETs QE and QF

9 Select FETs QE and QF

Selecting FETs for a design is always trial and error. To meet the power requirements of this design weselected 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs’ had the followingcharacteristics.

(60)

(61)

Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), anddrain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltagein the design (VdsQE) that will be applied to the FET in the application.

Voltage across FET QE and QF when they are off:

(62)

Voltage where FET COSS is specified and tested in the FET data sheet:

(63)

Specified output capacitance from FET data sheet:

(64)

Average QE and QF COSS [2]:

(65)

QE and QF RMS current:

(66)



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nCQEMINMILLER

52_

»

nCQEMAXMILLER

100_ »

MILLER _ MAXQE 100nC»

MILLER _ MINQE 52nC»

PI 4 A»

r f

P

100nC 52nC 48nCt t 24ns

I 4A

22

-» = = »

( )2 2OUT s s s

QE QE _ RMS ds(on)QE dsQE r f OSS _ QE _ AVG dsQE gQE gQE

OUT

P f f fP I R V t t 2 C V 2 Q V

V 2 2 2= ´ + ´ + + ´ ´ + ´ ´

QEP 9.3 W»

BUDGET BUDGET QEP P 2 P 6.5 W= - ´ »

Select FETs QE and QF www.ti.com

To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First thegate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gatecharge at the end of the miller plateau (QEMILLER_MAX) for the given VDS.

Figure 3. Vg vs. Qg for QE and QF FETs

Maximum gate charge at the end of the miller plateau:

(67)

Minimum gate charge at the beginning of the miller plateau:

(68)

NOTE: The FETs in this design were driven with UCC27324 setup to drive 4-A (IP) of gate drivecurrent.

(69)

Estimated FET Vds rise and fall time:

(70)

Estimate QE and QF FET Losses (PQE):

(71)

(72)

Recalculate the power budget.

(73)



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R

S OSS _ QA _ AVG

1f

2 L (2 C )=

p ´ ´

DELAY

R

2t 314ns

f 4= »

´

CLAMP DELAY

1D t fs 94%

fs

æ ö= - ´ =ç ÷

è ø

CLAMP RDSON OUT RDSON

DROP

CLAMP

2 D V a1 (V V )V 276.2V

D

æ ö´ ´ + ´ += =ç ÷

è ø

www.ti.com Input Capacitance (CIN)

10 Input Capacitance (CIN)

If this converter was designed for a 390-V input, which is generally fed by the output of a PFC boostpre-regulator. The input capacitance is generally selected based on holdup and ripple requirements.

NOTE: The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).

Calculate tank frequency:

(74)

Estimated delay time:

(75)

Effective duty cycle clamp (DCLAMP):

(76)

VDROP is the minimum input voltage where the converter can still maintain output regulation. Theconverter’s input voltage would only drop down this low during a brownout or line-drop condition if thisconverter was following a PFC pre-regulator.

(77)



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( )OUT

IN 2 2

IN DROP

12 P

60HzC 364 F

V V

´ ´³ » m

-

2

2 OUT

CINRMS PRMS1

INMIN

PI I 1.8 A

V a1

æ ö= - =ç ÷

´è ø

INC 330 F= m

CINESR 0.150= W

2

CIN CINRMS CINP I ESR 0.5 W= ´ =

BUDGET BUDGET CINP P P 6.0 W= - »

Input Capacitance (CIN) www.ti.com

CIN was calculated based on one line cycle of holdup:

(78)

Calculate high frequency input capacitor RMS current (ICINRMS).

(79)

To meet the input capacitance and RMS current requirements for this design we chose a 330-µF capacitorfrom Panasonic part number EETHC2W331EA.

(80)

This capacitor had a high frequency (ESRCIN) of 150 mΩ this was measured with an impedance analyzerat both 120 and 200 kHz.

(81)

Estimate CIN power dissipation (PCIN):

(82)

Recalculate remaining power budget:

(83)

There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the controldevice and all resistors supporting the control device.



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P

S

Ia2 100

I= =

OUT LOUT INMAX MAX

P1

OUT MAG s

P I V D1I 3.3 A

V 2 a1 L f

æ öD ´= + + »ç ÷

´ h ´è ø

PV 2V=

P

S

PEAK

V 0.2VR 49.9

I1.1

a2

-= » W

´

SR 48.7= W

2

PRMS1

RS S

IP R 0.03 W

a2

æ ö= ´ »ç ÷

è ø

CLAMP

DA P

CLAMP

DV V 29.8 V

1 D= »

-

OUT

DA

INMIN

P 0.6 VP 0.01W

V a2

´= »

´ h´

RE SR 100 R 4.87k= ´ = W

www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)

11 Setting Up the Current Sense Network (CT, RS, RRE, DA)

The CT chosen for this design had a turn’s ratio (a2) of 100:1

(84)

Calculate nominal peak current (IP1) at VINMIN:

Peak primary current:

(85)

The voltage where peak current limit will trip.

(86)

Calculate current sense resistor (RS) and leave 200 mV for slope compensation:

(87)

Select a standard resistor for RS:

(88)

Estimate power loss for RS:

(89)

Calculate maximum reverse voltage (VDA) on DA:

(90)

Estimate DA power loss (PDA):

(91)

Calculate RS reset resistor RRE:

Resistor RRE is used to reset the current sense transformer CT.

(92)



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LFR 1k= W

LFC 330pF=

LFP

LF LF

1f 482kHz

2 f R C= =

p ´ ´

BP1C 1 F= m

REFV 5 V=

V1 2.5 V=

BR 2.37k= W

( )B REF

A

R V V1R 2.37k

V1

´ -= = W

CR 2.37k= W

( )c OUT

I

R V V1R 9k

V1

´ -= » W

( )c OUT

I

R V V1R 9.09k

V1

´ -= » W

Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com

Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this designwe chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work formost applications but maybe adjusted to suit individual layouts and EMI present in the design.

(93)

(94)

(95)

The UCC28950 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequencynoise. This pin needs at least 1 µF of high frequency bypass capacitance (CBP1). Please refer to figure 1for proper placement.

(96)

The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (RA, RB), for thisdesign example we are going to set the error amplifier reference voltage (V1) to 2.5 V. Select a standardresistor value for RB and then calculate resistor value RA.

UCC28950 reference voltage:

(97)

Set voltage amplifier reference voltage:

(98)

(99)

(100)

Voltage divider formed by resistor RC and RI are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).

Select a standard resistor for RC:

(101)

Calculate RI:

(102)

Then choose a standard resistor for RI:

(103)



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2

OUT

LOAD

OUT

VR 2.4

P 0.1= = W

´

OUT LOAD COUT OUT

CO 2

C S LOAD OUT

PP PP

V R 1 2 j f ESR C 1G (f ) a1 a2

V R 1 2 j f R C S(f ) S(f )1

2 f 2 f

æ öD + p ´ ´ ´» = ´ ´ ´ ´ç ÷

D + p ´ ´ ´ æ öè ø+ + ç ÷p´ p´è ø

s

PP

ff 50kHz

4» =

S(f ) 2 j f= p´ ´

( )

C F Z

C

OUT Z P F

Z P I

Z P

V 2 j f R C 1G (f )

V 2 j f C C R2 j f C C R 1

C C

D p ´ ´ ´ += =

D æ öp ´ ´ ´ ´p ´ ´ + +ç ÷+è ø

PP

C

ff 5kHz

10= =

I

F

PP

CO

RR 27.9k

fG

10

= » Wæ öç ÷è ø

FR 27.4k» W

Z

C

F

1C 5.8nF

f2 R

5

= »´ p´ ´


Compensating the feedback loop can be accomplished by properly selecting the feedback components(RF, CZ and CP). These components are placed as close to pin 3 and 4 as possible of the UCC28950.

Calculate load impedance at 10% load (RLOAD):

(104)

Approximation of control to output transfer function (GCO(f)) as a function of frequency:

(105)

Double pole frequency of GCO(f):

(106)

Angular velocity:

(107)

Compensate the voltage loop with type 2 feedback network. The following transfer function is thecompensation gain as a function of frequency (GC(f)). Please refer to Figure 1 for component placement.

(108)

Calculate voltage loop feedback resistor (RF) based on crossing the voltage (fC) loop over at a 10th of thedouble pole frequency (fPP).

(109)

(110)

Select a standard resistor for RF.

(111)

Calculate the feedback capacitor (CZ) to give added phase at crossover.

(112)



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ZC 5.6nF=

P

F C

1C 580pF

2 R f 2= »

´ p´ ´ ´

PC 560pF=

( )V C COT dB(f ) 20log G (f ) G (f )= ´

Tv(f) Frequency Response

-80

-60

-40

-20

0

20

40

60

80

100 1000 10000 100000

Frequency in Hz

Gain

ind

B

-180

-135

-90

-45

0

45

90

135

180

Ph

as

ein

De

gre

es

TvdB(f)

?Tv(f)

sst 15ms=

SS

SS

t 25 AC 123nF

V1 0.55

´ m= »

+


Select a standard capacitance value for the design.

(113)

Put a pole at two times fC.

(114)

Select a standard capacitance value for the design.

(115)

Loop gain as a function of frequency (TV(f)) in dB.

(116)

Plot theoretical loop gain and phase to graphically check for loop stability (Figure 4). The theoretical loopgain crossed over at roughly 3.7 kHz with a phase margin of greater than 90 degrees.

NOTE: It is wise to check your loop stability of your final design with transient testing and/or anetwork analyzer and adjust the compensation (GC(f)) feedback as necessary.

Figure 4. Loop Gain (TVdB(f)), Loop Phase (θTV(f))

To limit over shoot during power up the UCC28950 has a soft-start function (SS, Pin 5) which in thisapplication was set for a soft start time of 15 ms (tSS).

(117)

(118)



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SSC 150nF=

R S

R OSS _ QA _ AVG

12 f L

2 f (2 C )p´ =

p´ ´ ´

R

S OSS _ QA _ AVG

1f

2 L (2 C )=

p ´ ´

ABSET

R

2.25t 346ns

f 4= »

´

DA1R 8.25k= W

DA1 ADEL

DA2

ADEL

R VR 344

5V V

´= » W

-

DA2R 348= W


Select a standard capacitor for the design.

(119)

This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50%load. When the converter is operating below 50% load the converter will be operating in valley switching.In order to achieve zero voltage switching on switch node of QBd, the turn-on (tABSET) delays of FETs QAand QB needs to be initially set based on the interaction of LS and the theoretical switch nodecapacitance. The following equations are used to set tABSET initially.

Equate shim inductance to two times COSS capacitance:

(120)

Calculate tank frequency:

(121)

Set initial tABSET delay time and adjust as necessary.

NOTE: The 2.25 factor of the tABSET equation was derived from empirical test data and may varybased on individual design differences.

(122)

The resistor divider formed by RDA1 and RDA2 programs the tABSET, tCDSET delay range of the UCC28950.Select a standard resistor value for RDA1.

NOTE: tABSET can be programmed between 30 ns to 1000 ns.

(123)

The voltage at the ADEL input of the UCC28950 (VADEL) needs to be set with RDA2 based on the followingconditions.

If tABSET > 155 ns set VADEL = 0.2 V, tABSET can be programmed between 155 ns and 1000 ns:

If tABSET ≤ 155 ns set VADEL = 1.8 V, tABSET can be programmed between 29 ns and 155 ns:

Based on VADEL selection, calculate RDA2:

(124)

Select the closest standard resistor value for RDA2:

(125)



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DA2

ADEL

DA1 DA2

5 V RV 0.202V

R R

´= =

+

3

ABSET ADEL

DELAB

(t 5ns) (0.15 V V 1.46) 10 1R 30.4k

ns 5 1A

- + ´ ´= ´ ´ » W

DELABR 30.1k= W

QAg

QB g

QB d

tABSET

= t1

- t0

Set tABSET

at resonant tank Peak and Valley

t0 t1 t2 t3 t4

tABSET

= t4

- t3

Miller Plateau

t5

Miller Plateau

tMILLER = t 2 - t 1

tMILLER = t 5 - t 4


Recalculate VADEL based on resistor divider selection:

(126)

Resistor RDELAB programs tABSET:

(127)

Select a standard resistor value for the design:

(128)

NOTE: Once you have a prototype up and running it is recommended you fine tune tABSET at lightload to the peak and valley of the resonance between LS and the switch node capacitance. Inthis design the delay was set at 10% load. Please refer to Figure 5.

Figure 5. tABSET to Achieve Valley Switching at Light Loads



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ABSET CDSETt t=

3

ABSET ADEL

DELCD

(t 5ns) (0.15 V V 1.46) 10 1R 30.4k

ns 5 1A

- + ´ ´= ´ ´ » W

DELCDR 30.1k= W

QCg

QDg

QDd

tCDSET

= t1

- t0

Set tCDSET

at resonant tank Peak and Valley

t0

t1

t2

t3

t4

tCDSET

= t4

- t3

Miller Plateau

t5

Miller Plateau

t MILLER = t 2 - t 1

tMILLER

= t5

- t4


The initial starting point for the QC and QD turn on delays (tCDSET) should be initially set for the same delayas the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays(tCDSET) by properly selecting resistor RDELCD (Pin 7).

(129)

Resistor RDELCD programs tCDSET:

(130)

Select a standard resistor for the design:

(131)

NOTE: Once you have a prototype up and running it is recommended to fine tune tCDSET at lightload. In this design the CD node was set to valley switch at roughly 10% load. Please referto Figure 6. Obtaining ZVS at lighter loads with switch node QDd is easier due to thereflected output current present in the primary of the transformer at FET QD and QCturnoff/on. This is because there was more peak current available to energize LS before thistransition, compared to the QA and QB turnoff/on.

Figure 6. tCDSET to Achieve Valley Switching at Light Loads



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AFSET BESET ABSETt t t 0.5= = ´

CA1R 8.25k= W

CA1 ADELEF

CA2

ADELEF

R VR 4.25k

5 V V

´= » W

-

CA2R 4.22k= W

CA2

ADELEF

CA1 CA2

5 V RV 1.692V

R R

´= =

+

( ) ( ) 3

AFSET ADELEF

DELEF

t 0.5 4ns 2.65 V V 1.32 10 1R 14.1k

ns 5 1A

´ - - ´ ´= ´ ´ » W


There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff ofFET QE after FET QB turnoff (tBESET). A good place to set these delays is 50% of tABSET. This will ensurethat the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large itwill cause OUTE and OUTF not to overlap correctly and it will create excess body diode conduction onFETs QE and QF.

(132)

The resistor divider formed by RCA1 and RCA2 programs the tAFSET and tBESET delay range of the UCC28950.Select a standard resistor value for RCA1.

NOTE: tEFSET and tBESET can be programmed between 32 ns to 1100 ns.

(133)

The voltage at the ADELEF pin of the UCC28950 (VADELEF) needs to be set with RCA2 based on the followingconditions.

If tAFSET < 170 ns set VADEL = 0.2 V, tABSET can be programmed between 32 ns and 170 ns:

If tABSET > or = 170 ns set VADEL = 1.7 V, tABSET can be programmed between 170 ns and 1100 ns:

Based on VADELEF selection, calculate RCA2:

(134)

Select the closest standard resistor value for RCA2:

(135)

Recalculate VADELEF based on resistor divider selection:

(136)

The following equation was used to program tAFSET and tBESET by properly selecting resistor RDELEF.

(137)



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DELEFR 14k= W

MINt 100ns=

3

MIN

TMIN

(t 15ns) 10R 12.9k

6.6s

- ´= » W

TMINR 13k= W

( )6

3

T REF

S

Hz2.5 10

VR V 2.5 V 2.5 10 60k

f V

2

Wæ ö´ç ÷W

= - ´ - ´ ´ » Wç ÷ç ÷è ø

TR 61.9k= W

( )IN TYP

LMAG

MAG s

V 1 DI 234mA

L f

-D = =

´


A standard resistor was chosen for the design.

(138)

Resistor RTMIN programs the minimum duty cycle on time (tMIN) that the UCC28950 (Pin 9) can demandbefore entering burst mode. If the UCC28950 controller tries to demand a duty cycle on time of less thantMIN the power supply will go into burst mode operation. Please see the UCC28950 data sheet for detailsregarding burst mode. For this design we set the minimum on time to 100 ns.

(139)

The minimum on time is set by selecting RTMIN with the following equation.

(140)

A standard resistor value is then chosen for the design.

(141)

There is a pin that is provided for setting up the converter switching frequency (Pin 10). The frequency canbe selected by adjusting timing resistor RT.

(142)

Select a standard resistor for the design.

(143)

The UCC28950 also provides slope compensation for peak current mode control (Pin 12). This can be setby setting RSUM with the following equations. The following equations will calculate the required amount ofslope compensation (VSLOPE) that is needed for loop stability.

NOTE: The change in magnetizing current on the primary dILMAG contributes to slope compensation.

(144)



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SLOPE1 S

0.04 VV 0.2V f

s= ´ =

m

OUTMAG S S

SLOPE2

TYP

dILdIL R f

a1 2 1mVV

a2 (1 D ) s

æ ö- ´ ´ç ÷´è ø= =´ - m

3

SUM

SLOPE

2.5 V 10R 125.4k

V 0.5 s

´ W= » W

´ m

SUMR 127k= W

OUT LOUT

S

OUT

RS

P 0.15 IR

V 2V 0.29 V

a1 a2

æ ö´ D+ ´ç ÷

è ø= =´

GR 1k= W

( )G REF RS

E

RS

R V VR 16.3k

V

-= » W

ER 16.9k= W


To help improve noise immunity VSLOPE is set to have a total slope that will equal 10% of the maximumcurrent sense signal (0.2 V) over one inductor switching period.

(145)

(146)

If VSLOPE2 < VSLOPE1 set VSLOPE = VSLOPE1

If VSLOPE2 ≥ VSLOPE1 set VSLOPE = VSLOPE2

(147)

Select a standard resistor for RSUM.

(148)

To increase efficiency at lighter loads the UCC28950 is programmed (Pin 12, DCM) under light loadconditions to turn off the synchronous FETs on the secondary side of the converter (QE and QF). Thisthreshold is programmed with resistor divider formed by RE and RG. This DCM threshold needs to be setat a level before the inductor current goes discontinues. The following equation sets the synchronousrectifiers to turnoff at roughly 15% load current.

(149)

Select a standard resistor value for RG.

(150)

Calculate resistor value RE.

(151)

Select a standard resistor value for this design

(152)



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Figure 7. Daughter Board Schematic

NOTE: Black triangles designate not populated.



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++

+

+

++

+


Figure 8. Power Stage Schematic

NOTE: It is recommended to use an RCD clamp to protect the output synchronous FETs from overvoltage due to switch node ringing. This RCD clamp is formed by diodes D4, D6 and resistorR6, R8 and R9 and capacitor C1 in the power stage schematic, .



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600W UCC28950 Effiency

83%

84%

85%

86%

87%

88%

89%

90%

91%

92%

93%

94%

95%

96%

10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

370V Efficiency

390V Efficiency

410V Efficiency

QBd/Q4

d

Q4 g

QB/Q4 = on

QA/QB = off

QB/Q4 = off

QA/Q1 = on

Valley Switching

tABSET Slight Delay after t ABSET

before Miller Plateau

tD

0V

QD d/Q3 d

Q3 g

QD/Q3 = on

QC/Q2 = off

QD/Q3 = off

QC/Q2 = on

Valley Switching

tCDSET Slight Delay after tCDSET


tD

0V


Figure 9. 600-W Phase Shifted Full Bridge Efficiency

Full bridge gate drives and primary switch nodes (QBd and QDd) at VIN = 390 V, IOUT = 5 A.

Figure 10. Q4g Q4d, VIN = 390 V, IOUT = 5 A Figure 11. Q3g Q3d, VIN = 390 V, IOUT = 5 A

NOTE: The gate drives look slightly different than Figure 5 and Figure 6. This is because they weredriven with 1:2 gate drive transformers instead of 1:1. At 10% load the primary switch nodeswere valley switching



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QD d/Q3 d

Q3 g

QD/Q3 = on

QC/Q2 = off

QD/Q3 = off

QC/Q2 = on

ZVS

tCDSET Slight Delay after t

CDSET


tD

0V

0V

QB d/Q4 d

Q4 g

QB/Q4 = on

QA/QB = off

QB/Q4 = off

QA/Q1 = on

Valley Switching

tABSET Slight Delay after tABSET


tD

0V

QB d/Q4 d

Q4 g

QB/Q4 = on

QA/QB = off

QB/Q4 = off

QA/Q1 = on

ZVS Achieved

tABSET

0V

QD d/Q3 d

Q3 g

QD/Q3 = on

QC/Q2 = off

QD/Q3 = off

QC/Q2 = on

ZVS

tCDSET

0V


Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 10 A


NOTE: Switch node QBd/Q4d is valley switching and node QDd/Q3d has achieved ZVS. Please referto Figure 12 and Figure 13. It is not uncommon for switch node QDd/Q3d to obtain ZVSbefore QBd/Q4d. This is because during the QDd/Q3d switch node voltage transition, thereflected output current provides immediate energy for the LC tanking at the switch node.Where at the QBd/Q4d switch node transition the primary has been shorted out by the highside or low side FETs in the H bridge. This transition is dependent on the energy stored in LS

and LLK to provide energy for the LC tanking at switch node QBd/Q4d making it take longer toachieve ZVS.



NOTE: When the converter is running at 25 A both switch nodes are operating into zero voltageswitching (ZVS). It is also worth mentioning that there is no evidence of the gate millerplateau during gate driver switching. This makes sense because the voltage across the drainand source of FETs QA through QD has already transition before the gate drives havetransitioned.



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QB d/Q4 d

Q4 g

QB/Q4 = on

QA/QB = off

QB/Q4 = off

QA/Q1 = on

ZVS

tABSET

0V

QD d/Q3 d

Q3 g

QD/Q3 = on

QC/Q2 = off

QD/Q3 = off

QC/Q2 = on

ZVS

tCDSET

0V

www.ti.com References



NOTE: ZVS was maintained from 50% to 100% output power.

12 References1. Bill Andreycak, “Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM

Controller” Unitrode Application Note SLUA107, 9/5/19992. Lazlo Balogh, “Design and Application Guide for High Speed MOSFET Gate Drive” Unitrode Power

Supply Design Seminar 1400, Topic 2, 2001



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Documents

UCC28950 600-W,Phase-Shifted,Full-Bridge Application Report...(LMAG). The following equations calculate the minimum magnetizing inductance of the primary of the transformer (T1) to