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Two’s Complement Arithmetic. Introduction to Combinational Logic Circuits.
(Class 1.2 – 8/30/2012)
CSE 2441 – Introduction to Digital Logic
Fall 2012
Instructor – Bill Carroll, Professor of CSE
Today’s Topics
• Reminder – check course website regularly http://crystal.uta.edu/~carroll/
• Two’s complement arithmetic
• Digital logic circuit taxonomy
• Basic logic gates – AND, OR, NOT, NAND, NOR, XOR
• Truth tables, logic equations
• Half adders and full adders
• Basic Verilog statements and modules
Signed Binary Numbers (n=4) Decimal Sign-Magnitude Two’s Complement One’s Complement
+7 0111 0111 0111
+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
0 0000, 1000 0000 0000, 1111
-1 1001 1111 1110
-2 1010 1110 1101
-3 1011 1101 1100
-4 1100 1100 1011
-5 1101 1011 1010
-6 1110 1010 1001
-7 1111 1001 1000
-8 NA 1000 NA
Two’s Complement Arithmetic (1)
• Two’s complement number systems are used in computer systems since this reduces hardware requirements (only adders are needed).
• A - B = A + (-B) (add r’s complement of B to A) • Range of numbers in two’s complement number system, where n is the number of
bits. – 2n-1 -1 = (0, 11 ... 1)2cns and -2n-1 = (1, 00 ... 0)2cns
• If the result of an operation falls outside the range, an overflow condition is said to
occur and the result is not valid. • Consider three cases (where B 0 and C 0):
– A = B + C – A = B - C – A = - B - C
Two’s Complement Arithmetic (2)
• Case 1: A = B + C
– (A)2 = (B)2 + (C)2
– If A > 2n-1 -1 (overflow), it is detected by a sign bit = 1 in A.
– Example: (7)10 + (4)10 = ? using 4-bit two’s complement arithmetic.
• + (5)10 = +(101)2 = (0101)2cns
• + (2)10 = +(010)2 = (0010)2cns
• (0101)2cns + (0010)2cns = (0111)2cns = +(111)2 = +(7)10
• No overflow.
– Example: (5)10 + (6)10 = ?
• + (5)10 = +(101)2 = (0101)2cns
• + (6)10 = +(110)2 = (0110)2cns
• (0101)2cns + (0110)2cns = (1011)2cns (overflow)
Two’s Complement Arithmetic (3)
• Case 2: A = B - C – A = (B)2 + (-(C)2) = (B)2 + [C]2 = (B)2 + 2n - (C)2 = 2n + (B - C)2 – If B C, then A 2n and the carry is discarded. – So, (A)2 = (B)2 + [C]|carry discarded – If B < C, then A = 2n - (C - B)2 = [C - B]2 or A = -(C - B)2 (no
carry in this case). – No overflow for Case 2. – Example: (7)10 - (3)10 = ?
• Perform (7)10 + (-(3)10) • (7)10 = +(0111)2 = (0111)2cns • -(3)10 = -(0011)2 = (1101)2cns • (7)10 - (3)10 = (0111)2cns + (1101)2cns = (0100)2cns + carry • = +(0100)2 = +(4)10
Two’s Complement Arithmetic (4)
– Example: (3)10 - (7)10 = ?
• Perform (3)10 + (-(7)10)
• (3)10 = +(011)2 = (0011)2cns
• -(7)10 = -(111)2 = (1001)2cns
• (3)10 - (7)10 = (0011)2cns + (1001)2cns = (1100)2cns
= -(0100)2 = -(4)10
Two’s Complement Arithmetic (5)
• Case 3: A = -B - C – A = [B]2 + [C]2 = 2n - (B)2 + 2n - (C)2 = 2n + 2n - (B + C)2 = 2n + [B + C]2 – The carry bit (2n) is discarded. – An overflow can occur, in which case the sign bit is 0. – Example: -(5)10 - (2)10 = ?
• Perform (-(5)10) + (-(2)10) • -(5)10 = -(0101)2 = (1011)2cns , -(2)10 = -(0010)2 = (1110)2cns • -(5)10 - (2)10 = (1011)2cns + (1110)2cns = (1001)2cns + carry
= -(0111)2 = -(7)10
– Example: -(5)10 - (7)10 = ? • Perform (-(5)10) + (-(7)10) • -(5)10 = (1011)2cns , -(7)10 = -(0111)2 = (1001)2cns • -(5)10 - (7)10 = (1011)2cns + (1001)2cns = (0100)2cns + carry • Overflow, because the sign bit of the result is 0.
Two’s Complement Arithmetic (6)
Example: A = (25)10 and B = -(46)10 , n = 8
• A = +(25)10 = (0 0011001)2cns , -A = (1 1100111)2cns • B = -(46)10 = -(0 0101110)2 = (1 1010010)2cns , -B = (0 0101110)2cns
• A + B = (0 0011001)2cns + (1 1010010)2cns = (1 1101011)2cns = -(21)10 • A - B = A + (-B) = (0 0011001)2cns + (0 0101110)2cns = (0 1000111)2cns = +(71)10 • B - A = B + (-A) = (1 1010010)2cns + (1 1100111)2cns = (1 0111001)2cns + carry = -(0 1000111)2cns = -(71)10 • -A - B = (-A) + (-B) = (1 1100111)2cns + (0 0101110)2cns = (0, 0010101)2cns + carry = +(21)10
Two’s Complement Arithmetic (7)
• Summary • When numbers are represented using 2’s complement number system:
– Addition: Add two numbers. – Subtraction: Add two’s complement of the subtrahend to the minuend. – Carry bit is discarded, and overflow is detected as shown above.
Case Carry Sign Bit Condition Overflow ?
B + C 0
0
0
1
B + C 2n-1 - 1
B + C > 2n-1 - 1
No
Yes
B - C 1
0
0
1
B C
B > C
No
No
-B - C 1
1
1
0
-(B + C) -2n-1
-(B + C) < -2n-1No
Yes
Digital Logic Circuit Taxonomy
• Combinational Circuits – Primary characteristic -- memoryless
– Primary building blocks -- logic gates
• Sequential circuits – Primary characteristic -- memory
– Primary building blocks -- logic gates, flip-flops
– Types • Synchronous (clocked)
• Asynchronous (unclocked)
Combinational Logic Circuits and Truth Tables
a b c z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Circuit Diagram Block Diagram
Truth Table Logic Equation
z = ab + ac + bc
Verilog HDL Code
module LogicCircuit (a,b,c,z); input a,b,c; output z; wire j,k,l; and (j,a,b); and (k,b,c); and (l,a,c); or (z,j,k,l); endmodule
j
k
l
Basic Logic Gates – AND, OR, NOT
AND gate OR Gate NOT Gate
a b f a
b f a f
a b f
0 0 0
0 1 0
1 0 0
1 1 1
a b f
0 0 0
0 1 1
1 0 1
1 1 1
a f
0 1
1 0
f = a·b f = a + b
f = a’
and(f,a,b) or(f,a,b)
not(f,a)
Basic Logic Gates – NAND, NOR
a b f
0 0 1
0 1 1
1 0 1
1 1 0
a b f
0 0 1
0 1 0
1 0 0
1 1 0
a b f a
b f
NAND gate NOR gate
f = (a·b)’ f = (a + b)’
nand(f,a,b) nor(f,a,b)
Exclusive-OR (XOR)
a b f
0 0 0
0 1 1
1 0 1
1 1 0
f = a b
xor(f,a,b)
ab’ b’
a’ a’b
f = ab’ + a’b
Test Your Understanding
a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
XOR3 gate
Logic equation f = ?
Verilog code
Test Your Understanding – Self-Check
a b c f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
XOR3 gate
Logic equation f = ?
f = a b c
Verilog code
xor(f,a,b,c)
XOR3 Realizations
g = f c = (a b) c = a b c
= a’b’c + a’bc’ + ab’c’ + abc
Half Adder
a b cout s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Output logic equations
s = a b
cout = a·b
Full Adder Realization
Output logic equations
s = a b cin
= a’b’cin + a’bcin’
+ ab’cin’ + abc
cout = a’bcin + ab’cin
+ abcin’ + abcin
= ab + acin + bcin
= majority (a,b,cin)
Logic Circuit Diagram
FA = HA + HA + OR2
HA and FA Verilog Code
module halfadder (s, cout, a, b);
input a, b;
output s, cout;
and (cout, a, b);
xor (s, a, b);
endmodule
module fulladder (s, cout, a, b, cin);
input a, b, cin;
output s, cout;
wire d, e, f, g;
xor (d, a, b);
xor (s, d, cin);
and (e, a, b);
and (f, a, cin);
and (g, b, cin);
or (cout, e, f, g);
endmodule
Summary of Basic Logic Gates
Chapter 2 24
Dual In-line Packages (DIP) – 1
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GND
7400: Y = ABQuadruple two-input NAND gates
1A
Vcc 4Y 4B 4A 3Y 3B 3A
1Y 1B 2A2Y 2B
14 13 12 11 10 9 8
7654321
GND
7402: Y = A + BQuadruple two-input NOR gates
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GND1Y
Vcc 6A 6Y 5A 5Y 4A 4Y
1A 2A 3A2Y 3Y
14 13 12 11 10 9 8
7654321
GND
7404: Y = AHex inverters
7408: Y = ABQuadruple two-input AND gates
Power signals 4.75 ≤ Vcc ≤ 5.25 volts GND = 0 volts
Inputs signals 0 ≤ L ≤ 0.8 volts 2.0 ≤ H ≤ 5.25 volts
Chapter 2 25
Dual In-line Packages (DIP) – 2
1B
Vcc 1C 1Y 3C 3B 3A 3Y
1A 2A 2C2B 2Y
14 13 12 11 10 9 8
7654321
GND
7410: Y = ABCTriple three-input NAND gates
1B
Vcc 2D 2C NC 2B 2A 2Y
1A NC 1D1C 1Y
14 13 12 11 10 9 8
7654321
GND
7420: Y = ABCDDual four-input NAND gates
Chapter 2 26
Dual In-line Packages (DIP) – 3
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GNDB
Vcc NC H G NC NC Y
A C ED F
14 13 12 11 10 9 8
7654321
GND
7430: Y = ABCDEFGH8-input NAND gate
7432: Y = A + BQuadruple two-input OR gates
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GND
7486: Y = A Å BQuadruple two-input exclusive-OR gates
Chapter 2 27
Positive and Negative Logic
Electrical Signals and Logic Values
– A signal that is set to logic 1 is said to be asserted, active, or true. – An active-high signal is asserted when it is high (positive logic). – An active-low signal is asserted when it is low (negative logic). – For TTL devices, 0 ≤ L ≤ 0.8 volts, 2 ≤ H ≤ 5.25 Volts
Electric Signal Logic Value
Positive Logic Negative Logic
High Voltage (H) 1 0
Low Voltage (L) 0 1