Tutorial Xil in x 11

7/29/2019 Tutorial Xil in x 11

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Xilinx and Nexys2 Tutorial

Kartik MohanramDept. of Electrical and Computer Engineering

Rice University, Houston, TX


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ELEC 326 Digital Logic Design 2

Verilog synthesis+simulation with Xilinx

XilinxProject

NavigatorIcon

on yourDesktop


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Open a new project called decoder2to4

Choose a working directory

(C:\...\decoder2to4) and name thetop level module there (decoder2to4)


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Device options, etc.

The next step is to select the target device and

its specs from the board (Spartan3E, xc3s500e, fg320);

to specify Verilog as the input HDL language


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Create a new top level module

decoder2to4 in the project

Adding new Verilog source


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Initialize project directory


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Enter the source

Use bottom tabs to

select the source file, key in the Verilog description,and save it

Design constraints+actions:

synthesis+implementation,

bit-file generation, etc.


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2-to-4 decoder example

Use case statement

Note that output [3:0] y ischanged to output reg [3:0] y

No Xilinx option to specify

this directly

Hand-code as necessary



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User constraint file (UCF)

UCF file for I/O mapping

The UCF allows us to leveragethe switches, LEDs, etc. on

the board to interact with the

implemented design (see

documentation on 326 pagetoo)

Add new source

Mapping visible on board

Sometime mis-marked Cross-check with manual



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UCF generation



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Add I/O constraints

The mapping assigns switch 1 (available on pin G18) to

input W[0], etc. These mappings are visible on theboard and also part of the Nexys2 board

documentation.



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Compile!

Select the decoder2to4 module anddouble-click the Synthesize XST button.

Note that Xilinx displays all allowed optionsfor the selected file in the project. Forexample, selecting the io.ucf file does notprovide options like synthesis, etc. since itreally is not a Verilog module.

Synthesis will take some time.

If successful, you will see a greencheck-mark

Double-click Generate Programming Fileto generate the bit-file

You can expand the synthesis tab and lookat the synthesis report, warnings, critical

path delay, etc. Errors and warnings

Heed them and you will learn as you go

Ask labbies



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Adding SSD signal

Add extra output ssd

Pulls all seven-segmentdisplay limbs up for the

decoder, so that you dont

see a faint glow

Same limbs will find usein core of your SS module

UCF entries are handy



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UCF for complete design



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Generate programming file



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Programming the FPGA

Once the bit-stream is generated, we will configure the

FPGA using the boundary-scan port Boundary-scan and JTAG are features used for

post-production test of ICs using very simple shift-

register concepts and 4 I/O pins

The parallel-port connector lists these as TDI, TDO,TCLK, and TMS (test data in, )

Can be used to configure FPGAs using the Adept

software (icon below)


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Tutorial Xil in x 11