Xilinx and Nexys2 TutorialKartik MohanramDept. of Electrical and Computer EngineeringRice University, Houston, TX

Verilog synthesis+simulation with XilinxELEC 326 Digital Logic Design*XilinxProjectNavigatorIconon yourDesktop

Open a new project called decoder2to4ELEC 326 Digital Logic Design*Choose a working directory(C:\...\decoder2to4) and name thetop level module there (decoder2to4)

Device options, etc.ELEC 326 Digital Logic Design*The next step is to select the target device andits specs from the board (Spartan3E, xc3s500e, fg320);to specify Verilog as the input HDL language

Adding new Verilog sourceELEC 326 Digital Logic Design*Create a new top level moduledecoder2to4 in the project

Initialize project directoryELEC 326 Digital Logic Design*

Enter the sourceUse bottom tabs to select the source file, key in the Verilog description, and save itELEC 326 Digital Logic Design*Design constraints+actions:synthesis+implementation,bit-file generation, etc.

2-to-4 decoder exampleUse case statementNote that output [3:0] y is changed to output reg [3:0] yNo Xilinx option to specifythis directlyHand-code as necessaryELEC 326 Digital Logic Design*

User constraint file (UCF)UCF file for I/O mappingThe UCF allows us to leverage the switches, LEDs, etc. on the board to interact with the implemented design (see documentation on 326 page too)Add new sourceMapping visible on boardSometime mis-markedCross-check with manualELEC 326 Digital Logic Design*

UCF generationELEC 326 Digital Logic Design*

Add I/O constraintsThe mapping assigns switch 1 (available on pin G18) to input W[0], etc. These mappings are visible on the board and also part of the Nexys2 board documentation.ELEC 326 Digital Logic Design*

Compile!Select the decoder2to4 module and double-click the Synthesize XST button. Note that Xilinx displays all allowed options for the selected file in the project. For example, selecting the io.ucf file does not provide options like synthesis, etc. since it really is not a Verilog module.Synthesis will take some time.If successful, you will see a green check-markDouble-click Generate Programming File to generate the bit-fileYou can expand the synthesis tab and look at the synthesis report, warnings, critical path delay, etc.Errors and warningsHeed them and you will learn as you goAsk labbiesELEC 326 Digital Logic Design*

Adding SSD signalAdd extra output ssdPulls all seven-segment display limbs up for the decoder, so that you dont see a faint glowSame limbs will find use in core of your SS moduleUCF entries are handyELEC 326 Digital Logic Design*

UCF for complete designELEC 326 Digital Logic Design*

Generate programming fileELEC 326 Digital Logic Design*

Programming the FPGAOnce the bit-stream is generated, we will configure the FPGA using the boundary-scan portBoundary-scan and JTAG are features used for post-production test of ICs using very simple shift-register concepts and 4 I/O pinsThe parallel-port connector lists these as TDI, TDO, TCLK, and TMS (test data in, )Can be used to configure FPGAs using the Adept software (icon below)

Programming the FPGAELEC 326 Digital Logic Design*

Programming the FPGAELEC 326 Digital Logic Design*