Tutorial on Critical Path Analysis - George Mason Universityece.gmu.edu/sites/ece/files/student-resource/7977/... · 2015-12-01 · Critical Path Analysis: !Analysis of critical path

Tutorial on

Critical Path Analysis

using Synplify Premier DP

Ver 1.0

Tutorial on Critical Path Analysis using Synplify Premier DP

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CAD Tools Setup: This tutorial is tested on following CAD tools

• Simulation Tool : ActiveHDL (Versions : 8.3)

• Synthesis Tool : Synplify Premier DP (2010)

Note: Synplify Premier DP is a licensed software and there is no free student version of the tool

available to work from home. Therefore students are encouraged to work at school in order to

perform Critical Path Analysis of below mentioned designs.

Initial Setup:

1. Go to the link https://cryptography.gmu.edu/athena/ .

2. Click on the link GMU Source Codes and scroll down to source codes for SHA-3

Round 3 candidates for Folded and Unrolled architectures.

3. Download both the packages (BLAKE_fh4v4.zip and BLAKE_folded.zip) available for

Blake algorithm.

BLAKE_fh4v4 (Folded horizontally and vertically by a factor of 4) design does not require any

changes in the default settings of Generics. However, BLAKE_folded design can be configured

into different architectures based on the Generic settings. BLAKE_folded is configured to

Blake_x1 (Basic iterative architecture) as one of the sample architectures for this tutorial.


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Blake_x1 Generic settings in blake_top.vhd file in BLAKE_folded VHDL source code

package:

-- Possible generic(s) values:

-- VERSION = {SHA3_ROUND2, SHA3_ROUND3}

-- FF = {1, 2, 4} Folding Factor (Vertical) %% Default is 2

-- HS = {HASH_SIZE_256, HASH_SIZE_512}

-- ADDERTYPE = {SCCA_BASED, CSA_BASED}

--

-- ADDERTYPE describes the type of adders being used in the critical paths. They are :

-- SCCA_BASED => Standard Carry Chain Addition in FPGA. This is a simple '+' sign.

-- CSA_BASED => Carry Save Adder.

-- Extra generic(s) :

-- W = {2^x} where x can be any reasonable number. By default, x is 6

-- Note : Input and output test vectors must correspond to the size of w

library ieee;

use ieee.std_logic_1164.all;

use work.sha3_pkg.all;

use work.sha3_blake_package.all;

entity blake_top is

generic (

VERSION : integer := SHA3_ROUND3;

FF : integer := 1; (change folding factor FF to 1 to chose Blake_x1 arch)

HS : integer := HASH_SIZE_256;

ADDERTYPE : integer := SCCA_BASED;

W : integer := 64

);


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Critical Path Analysis: Analysis of critical path is one of the most critical components while designing and

optimizing FPGA hardware designs. It is counterproductive to completely design the hardware

architecture without taking into account the critical path analysis and then try to tweak the

architecture to enhance the throughput and frequency at the end. This exercise should be

followed at the start of the project.

Purpose of this tutorial is to guide you through the whole process of taking a design, finding its

critical path, then take the appropriate steps for optimization i.e. pipeling, folding and unrolling

the architecture. For the sake of better understanding, two architectures of Blake (Basic iterative

and Folded horizontally and vertically by 4) are chosen. At the end, throughput and critical paths

are compared in order to evaluate criteria’s like high throughput and resource efficient

implementations.

This tutorial assumes that students have already gone through the exercise of FPGA Design Flow

based on Aldec Active-HDL. Follow the tutorial, mentioned below, to create a project in Active-

HDL and invoke Synplify Premier DP for synthesis.

• Tutorial on FPGA Design Flow based on Aldec Active-HDL


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There is no need to create a project and adding VHDL source files. Tool will automatically

select default project.

Default Project Run synthesis Fast synthesis option


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Handy Shortcuts : There are some handy shortcuts that appear in the quick access tool bar

of file menu. These options are sufficient to complete the critical path analysis and are used

throughout the tutorial. These options are very simple and helpful, therefore it is encouraged to

play around with them to get familiarized with the tool. All these options can also be accessed

from the file menu options.

1. RTL view ( )

2. Technology view ( )

3. Filter ( )

4. Normal view ( )

5. Zoom in ( )

6. Zoom out ( )

7. Full view ( )

8. Push/ Pop hierarchy ( )

9. Back and Forward ( )

10. Show Critical Path ( )

11. Find ( ) :


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RTL view ( ) : Most designs are hierarchical so interactive hierarchical viewing helps to better analyze the design

Technology view ( ): Choose technology view and Show Critical Path ( ) to start Critical Path analysis (explained in the explanation of Show Critical Path)


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Filter ( ): This is a very useful command in order to filter logic that is not required to

view and to investigate specific part of the logic. Example below shows how blake_datapath is

filtered from rest of the circuit for further analysis.


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Blake_x1 architecture : Discussion of this tutorial is divided in two sub categories.

• Identifying the Critical Path • Calculating the Critical Path delay

Identifying the Critical Path: This step requires that we use Synplify Premier DP to Show

Critical Path ( ), analyzing it and then reconstruct or highlight our block level diagram based

on critical path analysis.


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Block level diagram reconstructed of blake_x1 datapath, reconstructed using Filter ( ), Normal

view ( ), Zoom in ( ), Zoom out ( ) and Full view ( ) options.

Core8


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Use of Technology view ( ) and Show Critical Path ( ) to find Critical Path:

Tracing the critical path:

This is the most critical part of the whole exercise. Use Filter ( ), Normal view ( ), Zoom in

( ), Zoom out ( ) and Full view ( ) options to trace the critical part back and forth.

• Start from the bottom left at the start of the critical path.

• Double click each component and it will automatically open the source code corresponding in the

related files. It is always a good idea to copy the VHDL code corresponding to each component

as you go along the critical path in a separate notepad file. This will help you reconstruct and

highlight the critical path in the top-level and other modules in the hierarchy (see the source code

and highlighted critical path for both the designs below).

• Keep on going till the end of the path.


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• Reconstruct and highlight the critical path

• Also zoom in and see names of all the instances that come inside critical path

Find ( ) : Find any instance in your critical path to see its details using Find command.

VHDL Code corresponding to critical path circuit: r_gen : regn generic map ( N => BS, init => bzeros ) port map (clk => clk, rst => '0', en => er, input => rin, output => r );

g0123 : entity work.gfunc_modified(struct) generic map ( IW => IW, h => HS, ADDER_TYPE => ADDERTYPE ) port map ( ain => v1(i),bin => v1(i+4),cin => v1(i+8),din => v1(i+12), const_0 => cp(2*i),const_1 => cp(2*i + 1), aout => v2(i), bout => v2(i+4), cout=> v2(i+8),dout => v2(i+12)); g6 : entity work.gfunc_modified(struct) generic map ( IW => IW, h => HS, ADDER_TYPE => ADDERTYPE ) port map ( ain => v2(2),bin => v2(7),cin => v2(8),din => v2(13), const_0 => cp(12),const_1 => cp(13), aout => v3(2), bout => v3(7), cout=> v3(8),dout => v3(13)); rin <= rinit when (sf = '1' or slr = '1' ) else rprime; r_gen : regn generic map ( N => BS, init => bzeros ) port map (clk => clk, rst => '0', en => er, input => rin, output => r );


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Calculating Critical path delay (Tclk): This steps requires much more attention in order to calculate the

delay cause by each instance and components inside each instance as well. The two features of the tool

used here are as follows:

• Viewing Timing information (Delay and Slack time)

• Annotating Timing information in the Schematic Views

Annotation showing delays (logic + net delay) and slack (worst path that goes through the instance)

(Delay, Slack) info


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Caculate delays related to all the instances and the overall delay to compute the throughput.


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Blake_fh4v4 architecture : All the steps followed for Blake_x1 are also valid for Blake_fh4v4

architecture. Details are omitted for this architecture but all the important steps are done here as well.

Use of Technology view ( ) and Show Critical Path ( ) to find Critical Path:

Note: Keep in mind that delay of one component may overlaps with the delay of second component. Highlighted part in the figure below (in Red) shows delay of an adder. It overlaps after sometime with the delay of second adder.


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VHDL Code corresponding to critical path circuit:

state_reg_gen : process ( clk ) begin if rising_edge( clk ) then if state_wr = '1' then state_ram(0,conv_integer(sram_addr_delayed(0))) <= state_in_p0; state_ram(1,conv_integer(sram_addr_delayed(1))) <= state_in_p4; state_ram(2,conv_integer(sram_addr_delayed(2))) <= state_in_p8; state_ram(3,conv_integer(sram_addr_delayed(3))) <= state_in_p12; end if; sram_addr_delayed <= sram_addr; end if; end process; aadd <= const + ain + bin; cadd <= dxor_rot + cin; bxor_rot <= rolx(bxor, 32-g_rot_arch32(1)) when sel = '0' else rolx(bxor, 32-g_rot_arch32(3)); state_in_p4 <= init_o_p4 when h_wr = '1' else gout1; state_reg_gen : process ( clk ) begin if rising_edge( clk ) then if state_wr = '1' then state_ram(0,conv_integer(sram_addr_delayed(0))) <= state_in_p0; state_ram(1,conv_integer(sram_addr_delayed(1))) <= state_in_p4; state_ram(2,conv_integer(sram_addr_delayed(2))) <= state_in_p8; state_ram(3,conv_integer(sram_addr_delayed(3))) <= state_in_p12; end if; sram_addr_delayed <= sram_addr; end if; end process;


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Highlighted Critical path information of Blake_fh4v4:


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G_half module:

Calculation of the Critical Path:


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Performance Summary: Worst slack in design: -0.886 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------ blake_top|clk 176.3 MHz 152.5 MHz 5.671 6.557 -0.886 inferred Autoconstr_clkgroup_0 ============================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------- blake_top|clk blake_top|clk | 5.671 -0.886 | No paths - | No paths - | No paths - ===================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: blake_top|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- datapath_gen.state_ram_1_I_9 blake_top|clk RAM16X4S O1 state_ram_1[1] 4.992 -0.886 datapath_gen.state_ram_0_I_9 blake_top|clk RAM16X4S O1 state_ram_0[1] 4.992 -0.868 datapath_gen.state_ram_1_I_9 blake_top|clk RAM16X4S O2 state_ram_1[2] 4.992 -0.864 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------- datapath_gen.state_ram_1_I_5 blake_top|clk RAM16X4S D3 state_in_p4[19] 8.758 -0.886 datapath_gen.state_ram_1_I_5 blake_top|clk RAM16X4S D2 state_in_p4[18] 8.758 -0.864 datapath_gen.state_ram_1_I_1 blake_top|clk RAM16X4S D0 state_in_p4[24] 8.758 -0.856 ===============================================================================================================


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Worst Path Information *********************** Path information for path number 1: Requested Period: 5.671 - Setup time: 0.594 + Clock delay at ending point: 3.682 = Required time: 8.758 - Propagation time: 5.963 - Clock delay at starting point: 3.682 = Slack (critical) : -0.886 Number of logic level(s): 51 Starting point: datapath_gen.state_ram_1_I_9 / O1 Ending point: datapath_gen.state_ram_1_I_5 / D3 The start point is clocked by blake_top|clk [rising] on pin WCLK The end point is clocked by blake_top|clk [rising] on pin WCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- datapath_gen.state_ram_1_I_9 RAM16X4S O1 Out 1.310 4.992 - state_ram_1[1] Net - - 0.512 - 7 datapath_gen.gfunc_gen.un2_aadd_0_o5_1_1 LUT3 I2 In - 5.504 - datapath_gen.gfunc_gen.un2_aadd_0_o5_1_1 LUT3 O Out 0.154 5.658 - un2_aadd_0_o5_1_1 Net - - 0.329 - 1 datapath_gen.gfunc_gen.un2_aadd_0_cry_2 MUXCY_L DI In - 5.987 - datapath_gen.gfunc_gen.un2_aadd_0_cry_2 MUXCY_L LO Out 0.231 6.218 - un2_aadd_0_cry_2 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_3 MUXCY_L CI In - 6.218 - datapath_gen.gfunc_gen.un2_aadd_0_cry_3 MUXCY_L LO Out 0.022 6.240 - un2_aadd_0_cry_3 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_4 MUXCY_L CI In - 6.240 - datapath_gen.gfunc_gen.un2_aadd_0_cry_4 MUXCY_L LO Out 0.022 6.263 - un2_aadd_0_cry_4 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_5 MUXCY_L CI In - 6.263 - datapath_gen.gfunc_gen.un2_aadd_0_cry_5 MUXCY_L LO Out 0.022 6.285 - un2_aadd_0_cry_5 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_6 MUXCY_L CI In - 6.285 - datapath_gen.gfunc_gen.un2_aadd_0_cry_6 MUXCY_L LO Out 0.022 6.307 - un2_aadd_0_cry_6 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_7 MUXCY_L CI In - 6.307 - datapath_gen.gfunc_gen.un2_aadd_0_cry_7 MUXCY_L LO Out 0.022 6.329 - un2_aadd_0_cry_7 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_8 MUXCY_L CI In - 6.329 - datapath_gen.gfunc_gen.un2_aadd_0_cry_8 MUXCY_L LO Out 0.022 6.351 - un2_aadd_0_cry_8 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_9 MUXCY_L CI In - 6.351 - datapath_gen.gfunc_gen.un2_aadd_0_cry_9 MUXCY_L LO Out 0.022 6.373 - un2_aadd_0_cry_9 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_10 MUXCY_L CI In - 6.373 - datapath_gen.gfunc_gen.un2_aadd_0_cry_10 MUXCY_L LO Out 0.022 6.396 - un2_aadd_0_cry_10 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_11 MUXCY_L CI In - 6.396 - datapath_gen.gfunc_gen.un2_aadd_0_cry_11 MUXCY_L LO Out 0.022 6.418 - un2_aadd_0_cry_11 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_12 MUXCY_L CI In - 6.418 - datapath_gen.gfunc_gen.un2_aadd_0_cry_12 MUXCY_L LO Out 0.022 6.440 - un2_aadd_0_cry_12 Net - - 0.000 - 2


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datapath_gen.gfunc_gen.un2_aadd_0_cry_13 MUXCY_L CI In - 6.440 - datapath_gen.gfunc_gen.un2_aadd_0_cry_13 MUXCY_L LO Out 0.022 6.462 - un2_aadd_0_cry_13 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_14 MUXCY_L CI In - 6.462 - datapath_gen.gfunc_gen.un2_aadd_0_cry_14 MUXCY_L LO Out 0.022 6.484 - un2_aadd_0_cry_14 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_15 MUXCY_L CI In - 6.484 - datapath_gen.gfunc_gen.un2_aadd_0_cry_15 MUXCY_L LO Out 0.022 6.507 - un2_aadd_0_cry_15 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_16 MUXCY_L CI In - 6.507 - datapath_gen.gfunc_gen.un2_aadd_0_cry_16 MUXCY_L LO Out 0.022 6.529 - un2_aadd_0_cry_16 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_17 MUXCY_L CI In - 6.529 - datapath_gen.gfunc_gen.un2_aadd_0_cry_17 MUXCY_L LO Out 0.022 6.551 - un2_aadd_0_cry_17 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_18 MUXCY_L CI In - 6.551 - datapath_gen.gfunc_gen.un2_aadd_0_cry_18 MUXCY_L LO Out 0.022 6.573 - un2_aadd_0_cry_18 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_19 MUXCY_L CI In - 6.573 - datapath_gen.gfunc_gen.un2_aadd_0_cry_19 MUXCY_L LO Out 0.022 6.596 - un2_aadd_0_cry_19 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_20 MUXCY_L CI In - 6.596 - datapath_gen.gfunc_gen.un2_aadd_0_cry_20 MUXCY_L LO Out 0.022 6.618 - un2_aadd_0_cry_20 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_21 MUXCY_L CI In - 6.618 - datapath_gen.gfunc_gen.un2_aadd_0_cry_21 MUXCY_L LO Out 0.022 6.640 - un2_aadd_0_cry_21 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_22 MUXCY_L CI In - 6.640 - datapath_gen.gfunc_gen.un2_aadd_0_cry_22 MUXCY_L LO Out 0.022 6.662 - un2_aadd_0_cry_22 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_23 MUXCY_L CI In - 6.662 - datapath_gen.gfunc_gen.un2_aadd_0_cry_23 MUXCY_L LO Out 0.022 6.684 - un2_aadd_0_cry_23 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_24 MUXCY_L CI In - 6.684 - datapath_gen.gfunc_gen.un2_aadd_0_cry_24 MUXCY_L LO Out 0.022 6.707 - un2_aadd_0_cry_24 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_25 MUXCY_L CI In - 6.707 - datapath_gen.gfunc_gen.un2_aadd_0_cry_25 MUXCY_L LO Out 0.022 6.729 - un2_aadd_0_cry_25 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_26 MUXCY_L CI In - 6.729 - datapath_gen.gfunc_gen.un2_aadd_0_cry_26 MUXCY_L LO Out 0.022 6.751 - un2_aadd_0_cry_26 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_27 MUXCY_L CI In - 6.751 - datapath_gen.gfunc_gen.un2_aadd_0_cry_27 MUXCY_L LO Out 0.022 6.773 - un2_aadd_0_cry_27 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_28 MUXCY_L CI In - 6.773 - datapath_gen.gfunc_gen.un2_aadd_0_cry_28 MUXCY_L LO Out 0.022 6.795 - un2_aadd_0_cry_28 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_29 MUXCY_L CI In - 6.795 - datapath_gen.gfunc_gen.un2_aadd_0_cry_29 MUXCY_L LO Out 0.022 6.817 - un2_aadd_0_cry_29 Net - - 0.000 - 2 datapath_gen.gfunc_gen.un2_aadd_0_cry_30 MUXCY_L CI In - 6.817 - datapath_gen.gfunc_gen.un2_aadd_0_cry_30 MUXCY_L LO Out 0.022 6.840 - un2_aadd_0_cry_30 Net - - 0.000 - 1 datapath_gen.gfunc_gen.un2_aadd_0_s_31 XORCY CI In - 6.840 - datapath_gen.gfunc_gen.un2_aadd_0_s_31 XORCY O Out 0.247 7.087 - gout0[31] Net - - 0.476 - 5 datapath_gen.gfunc_gen.cadd_axb_15_0 LUT6 I5 In - 7.563 - datapath_gen.gfunc_gen.cadd_axb_15_0 LUT6 O Out 0.086 7.649 - cadd_axb_15 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_15 MUXCY_L S In - 7.649 - datapath_gen.gfunc_gen.cadd_cry_15 MUXCY_L LO Out 0.257 7.906 -


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cadd_cry_15 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_16 MUXCY_L CI In - 7.906 - datapath_gen.gfunc_gen.cadd_cry_16 MUXCY_L LO Out 0.022 7.928 - cadd_cry_16 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_17 MUXCY_L CI In - 7.928 - datapath_gen.gfunc_gen.cadd_cry_17 MUXCY_L LO Out 0.022 7.950 - cadd_cry_17 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_18 MUXCY_L CI In - 7.950 - datapath_gen.gfunc_gen.cadd_cry_18 MUXCY_L LO Out 0.022 7.972 - cadd_cry_18 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_19 MUXCY_L CI In - 7.972 - datapath_gen.gfunc_gen.cadd_cry_19 MUXCY_L LO Out 0.022 7.995 - cadd_cry_19 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_20 MUXCY_L CI In - 7.995 - datapath_gen.gfunc_gen.cadd_cry_20 MUXCY_L LO Out 0.022 8.017 - cadd_cry_20 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_21 MUXCY_L CI In - 8.017 - datapath_gen.gfunc_gen.cadd_cry_21 MUXCY_L LO Out 0.022 8.039 - cadd_cry_21 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_22 MUXCY_L CI In - 8.039 - datapath_gen.gfunc_gen.cadd_cry_22 MUXCY_L LO Out 0.022 8.061 - cadd_cry_22 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_23 MUXCY_L CI In - 8.061 - datapath_gen.gfunc_gen.cadd_cry_23 MUXCY_L LO Out 0.022 8.083 - cadd_cry_23 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_24 MUXCY_L CI In - 8.083 - datapath_gen.gfunc_gen.cadd_cry_24 MUXCY_L LO Out 0.022 8.106 - cadd_cry_24 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_25 MUXCY_L CI In - 8.106 - datapath_gen.gfunc_gen.cadd_cry_25 MUXCY_L LO Out 0.022 8.128 - cadd_cry_25 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_26 MUXCY_L CI In - 8.128 - datapath_gen.gfunc_gen.cadd_cry_26 MUXCY_L LO Out 0.022 8.150 - cadd_cry_26 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_27 MUXCY_L CI In - 8.150 - datapath_gen.gfunc_gen.cadd_cry_27 MUXCY_L LO Out 0.022 8.172 - cadd_cry_27 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_28 MUXCY_L CI In - 8.172 - datapath_gen.gfunc_gen.cadd_cry_28 MUXCY_L LO Out 0.022 8.194 - cadd_cry_28 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_29 MUXCY_L CI In - 8.194 - datapath_gen.gfunc_gen.cadd_cry_29 MUXCY_L LO Out 0.022 8.217 - cadd_cry_29 Net - - 0.000 - 2 datapath_gen.gfunc_gen.cadd_cry_30 MUXCY_L CI In - 8.217 - datapath_gen.gfunc_gen.cadd_cry_30 MUXCY_L LO Out 0.022 8.239 - cadd_cry_30 Net - - 0.000 - 1 datapath_gen.gfunc_gen.cadd_s_31 XORCY CI In - 8.239 - datapath_gen.gfunc_gen.cadd_s_31 XORCY O Out 0.247 8.486 - gout2[31] Net - - 0.421 - 3 datapath_gen.gfunc_gen.bout_0[19] LUT5 I4 In - 8.907 - datapath_gen.gfunc_gen.bout_0[19] LUT5 O Out 0.117 9.024 - gout1[19] Net - - 0.206 - 1 datapath_gen.state_in_p4_0[19] LUT3 I2 In - 9.229 - datapath_gen.state_in_p4_0[19] LUT3 O Out 0.086 9.316 - state_in_p4[19] Net - - 0.329 - 1 datapath_gen.state_ram_1_I_5 RAM16X4S D3 In - 9.645 - ============================================================================================ Total path delay (propagation time + setup) of 6.557 is 4.284(65.3%) logic and 2.274(34.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

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Tutorial on Critical Path Analysis - George Mason Universityece.gmu.edu/sites/ece/files/student-resource/7977/... · 2015-12-01 · Critical Path Analysis: !Analysis of critical path