Chapter 2Circuit Switch Design Principles

IEG4020Telecommunication Switching and Network Systems

Fig. 2.1. An N x N switch used to interconnect N inputsand N outputs

12

N

12

N

......

Inputs Outputs

2

Space-Domain Circuit Switching

Fig. 2.2. Bar and cross states of 2 x 2 switching elements

Bar State Cross State

3

Strictly Nonblocking

Fig. 2.3. (a) Crossbar switch

1

2

3

4

1 2 3 4

Inputs

Outputs

Connections:Input 1 to Output 3Input 2 to Output 4

4

Strictly Nonblocking

Fig. 2.3. (b) banyan switch

Blocking: Input 2 cannot be connected to output 2 if input 1 is already connected to output 1

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12

34

5

Blocking

RNB RNB

WSNBWSNB

SNBSNB

RNB — Rearrangeably Nonblocking WSNB — Wide-sense NonblockingSNB — Strictly Nonblocking

6

Nonblocking Properties

Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking switch

1

2

3

4

1

2

3

4

7

Rearrangeably Nonblocking

Fig. 2.4. (b) a connection request from input 4 to output 1 is blocked

Fig. 2.4. (c) Same connection request can be satisfied by rearrangingthe existing connection from input 2 to output 2

1234

1234

Connection cannot be set up between input 4 and output 1

Connection can now be set up between input 4 and output 1

1234

1234

8

Rearrangements

Two states corresponding to the same mapping :

1234

1234

1234

1234

Input 1 2 3 4Output 1 2 3 4

9

Complexity of nonblocking switches :How to build large switch from smaller switches?

Problems with two-stage networks :

1

2

m

1

2

m

......

(a)

N = mn# lines = m2n

= mN

Bandwidth expansion factor = m

(b)

1

2

m

1

2

m

......

nn

10

Fig. 2.5. (a) An example of one-to-one mapping from input to output

1．2．3．4．

． 1． 2． 3． 4

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Fig. 2.5. (b) Number of crosspoints needed for nonblocking switch

12

N

12

N

.

.

....

N! mappingsM crosspoints

2

2

# states # mappings

2 ! log ! log for large

M NM N

N NN

12

Fig. 2.6. A three-stage clos switch architecture

13

Clos Switching Network

n1 × r2

n1 × r2

n1 × r2

r1 × r3

r1 × r3

r1 × r3

r2 × n3

r2 × n3

r2 × n3

...

...

...

...

...

...

(1)

(2)

(r1)

(1)

(2)

(r2)

(1)

(2)

(r3)

......

n1r1 = n3r3 = N for N × N switch

ri — # switch modules in column in1 — # inputs in column 1 modulen3 — # outputs in column 3 module

Necessary condition for nonblocking:

2 1 3,r n n

Fig. 2.7. An example of blocking in a three-stage switch

Key:Find a commonly accessible middle node from both input and output nodes

A

F

G B

123456789

123456789

H

A request for connection from input 9 to output 4 is blockedSA = middle-stage nodes used by A = { F, G }SB = middle-stage nodes used by B = { H }

14

Fig. 2.8. The connection matrix of the three-stage network

A B

F

G

H

F,G,H

21

A

r1

1 2 B r2

Stage 1 switch

Stage 3 switch

15

Conditions of a Legitimate connection Matrix :

1

3

2 1

2 3

1. , number of symbols in row A

2. , number of symbols in row B

3. necessary condition for nonblocking property

4. Symbols

A A

B B

S n S

S n S

r nr n

2

in each row (column) must be distinct

,A BS S r

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Fundamental Conditions

1 3

1 3

1

3

Proof: Trivial case 1If 1Worst case: all other inputs of A and outputs of B are busy

1

1

A

B

: N n n n n N :

S n

nS

1 3

2 1 3

2 if 1 there is at least one available middle-stage no

A B A B A B

A B

S S S S S S

S S

n nr n n ,

de17

Condition for Strictly NonblockingClos network is strictly nonblocking iff

2 1 3min 1r n n ,N

Rearrangeability allows condition to be reduced to

Rearrangement —— Substituting symbols in connection matrix such that

1.) Matrix remains legitimate

2.) An unused symbol in row A and column B can be found

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Condition for Rearrangeably Nonblocking

2 1 3max ,r n n

A 1

B 3

A 2

A 2

Proof: i) "Only if " part trivial ii) "if " part

S 1 S 1

a.) S an unused symbol

b.) S

B

B

nn

S r

S r

A A

2 3

B 2 1

S S

( 1) 1

S ( 1) 1

a symbol C in row A, not in column B a

B B B

A

S S S

r n

S r n

symbol D not in row A, but in column B

SB

‧D

SA

． C

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Condition for Rearrangeably Nonblocking

Fig. 2.9. (a) A chain of C and D originating from B

Fig. 2.9. (b) Physical connections corresponding to the chain

..

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C

D

D

D

C

CA’

A

B’ B

A’’

A’”

B”

Connection between A and B is blocked

B

A

C SD S

2A BS S rChain terminates at A” because

AC S

A’

A”

A

A”’

..

..

..

..

B’

B

B”

..

..

..

C

D

..

..

..

A already connected to all middle-stage nodes except D

B already connected to all middle-stage nodes except C

Only links used by connections in the chain are shown

..

Fig. 2.10. Illustration showing loops in chains are notpermitted in legitimate connection matrix

C D

C D

CD

A loop in the chain

D occurs twice in this column, making the matrix illegitimate (i.e. physically impossible in associated switch)

There should be two end points in a chain

21

Fig. 2.11. (a) Rearrangement of the chain in Fig. 2.9.

Fig. 2.11. (b) Corresponding rearrangement of connections

C

C

C

C

D

DA’

A”AA”’

B’ B B”

D can now be put in entry (A, B)

A’

A”

A

A”’

..

..

..

..

..

B’

B

B”

..

..

..

..

C

D

..

..

..

22

Fig. 2.12. (a) Two chains, one originates from B, one from A

Fig. 2.12. (b) Illustration that the two chains cannot be connected

D

D

C

C D

D C

D

C

......A

B

D

D

C

C DC

...

A

BThis column search ends in C, which is not possible

Start searching from B. Column search always looks for D

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How many rearrangements?o A new row/column is covered each time a point is

includedo (r1 + r3 – 2) other rows and columns

o At most (r1 + r3 – 1) rearrangements (loose)

o Basic: consider two chains, one originates from row A, one from column B Choose the shorter chain for rearrangement

o A composite move: a move in chain 1 with a move in chain 2 At most r1 – 2 moves before all rows exhausted

At most r3 – 2 moves before all columns exhausted

1 3Can do better: # rearrangements min( ) 1r , r

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Fig. 2.13. Recursive decomposition of a rearrangeably nonblocking network

2 x 2

2 x 2

2 x 2

2 x 2

2 x 2

2 x 2

..... ...

..

..

..

12

34

N-1N

12

34

N-1N

The x network is rearrangeably nonblocking if

the networks are rearrangeably nonblocking2 2

N NN N

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2 2N N

2 2N N

Benes Switching Network

Number of 2x2 elements in Benes Network :

-1

-2

-

2

Let 2 and # stages in x Benes Network, then

( ) ( ) 22

(2 ) (2 ) 2

(2 ) 4.

.

(2 ) 2 (2) 2( -1) 1 2( -1) 2 -1 2log

n

n n

n

n j

N f(k) k kN

f N f

ff

f

fjf n

nn 1N

26

Benes Network - Complexity

Fig. 2.14. An 8x8 Benes Network

12

34

56

78

12

34

56

78

Baseline Network Reverse

Baseline Network

27

Benes Network - Structure

Baseline Network

Reverse Baseline Network

28

Baseline and Reverse Baseline Networks

Fig. 2.15. Illustration of a looping connection setup algorithm

12

34

56

78

12

34

56

78

Set up paths for input-output pairs :(1, 4), (2, 5), (3, 6), (4, 3)(5, 7), (6, 8), (7, 1), (8, 2)Central Algorithm: # steps = N logN

1 2 3 4 5 6 7 8inputoutput 4 5 6 3 7 8 1 2

29

Looping Algorithm

1.) Unique path property of underlying baseline and reverse baseline networks

2.) Binary tree to middle-stage nodes An input can reach 2j-1 nodes at stage j, j <= log2N

3.) Reachability of nodes in baseline/reverse baseline networks: A node in stage i can be reached by 2i inputs and can reach 2n-j+1 outputs

4.) Middles nodes blocked by an existing path

30

Properties of Benes Network

Fig. 2.16. Cantor network

.

.

.

..

..

..

..

..

..

.

.

.

1

2

N

1

2

N

m = 1

m = log N

..

31

Cantor Network

Cantor Network is SNB :1.) Let m be # of Benes Network required2.) Worst case: all other N-1 inputs/outputs busy

→ there are (N-1) paths to middle nodes3.) One path meets the binary tree at stage 1

Two paths at stage 2

2log

1

Let the # paths meeting the binary trees at stage be

2 1

Check: 1

i

ii

N

ii

i A

A -

A N

32

Cantor Network – Strictly Nonblocking

An example of 8 x8 Benes network

Stage 1 Stage 2 …

4.) A node in stage i blocks

2

1

log 1

21

2 middle nodes

# middle nodes(log 1)

eliminated 4

n ii

N

i ii

B

NA B N

2

2

# middle nodes eliminated# middle nodes >

by inputs and outputs

2 (log -1)2 4

log -1

Nm NN

m N

33

Cantor Network – Strictly Nonblocking

5.)

-2(e.g. 1, half the nodes or 2 nodes are blocked)ni

Fig. 2.17. Binary tree extended from an input to all middle-stage nodes

12

34

56

78

12

34

56

78

Connection paths from inputs 1 and 2 intersect with binary tree from the first time in stage 2

If input 4 is connected to this link: a subtree is formed by the three subsequent nodes

Therefore the two lower middle-stage nodes are eliminated from connection by input 3

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2

Total number of middle1 2 ... 1 0

nodes blocked from inputs 4 8 4 2

(log 1)4

N N N N

NN

Number of paths Number of middle-stage nodes blocked

1 4

2 8

N

N

4 16N

... ...

35

# middle nodes blocked from inputs

Fig. 2.18. Performing time-slot interchange using space-division switch

DEMUX

DEMUX

Space division switch

36

Time-Domain Switching

Fig. 2.19. Direct time slot interchange using random access memory (switching in the time domain)

TSI

Write Read

abc

RAMSwitching in time domain

Write Address Sequence = a, b, c

Read Address Sequence = b, a, c

37

Time-Domain Switching

Example: memory access time 1 rate 1.5Mbps 24 Each data source is 64 kbps One byte per time-slot

24 x 64,000 bps Arrival rate =

8 bits/time-slot =192,000 time-slots/s

TN

ec A read and a write required per time-slot

1 memory access time 2.6

2 x 192,000s

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Example for Time-Domain Switching

Fig. 2.20. A time-space-time switch

TSI

TSI

TSI

r x r

TSI

TSI

TSI

......

n m m n

n, m : number of time slots per frame at various points

39

Time-Space-Time Switching

Fig. 2.25 A time-space time switch

C(1,3) B(1,2) A(1,1)

F(2,3) E(2,2) D(2,1)

L(3,3) H(3,2) G(3,1)

3 x 3

TSI

TSI

TSI

TSI

TSI

TSI

1

3

3

3 2

1 1

22

Frame

Targeted Outputs

( i, j ) — data on input i at time-slot j

40

Time-Space-Time Switching

Fig. 2.21. Equivalent of time-space-time switching and three-stage space switching

MUX

MUX

MUX

TSI

TSI

TSI

TSI

TSI

TSI

MUX

MUX

MUX

(1)

(2)

(3)

(1)

(2)

(3)

A(1,1)

D(2,1)

C(1,3)B(1,2)

F(2,3)E(2,2)

L(3,3)H(3,2)G(3,1)

A(1,1)

D(2,1)

C(1,3)

B(1,2)F(2,3)

E(2,2)

L(3,3)H(3,2)

G(3,1)

CBA

FED

LHG

BAC

EDF

HGL

EDC

HAL

BGF

CED

LHA

GBF

41

Time-Space-Time Switching

Fig. 2.21. Input-output mapping changes from slot to slot inspace-division switch in time-space-time switching

C(1,3)B(1,2) A(1,1)

F(2,3)E(2,2) D(2,1)

L(3,3)H(3,2) G(3,1)

3 x 3

C(1,3)E(2,2) D(2,1)

L(3,3)H(3,2) A(1,1)

F(2,3)B(1,2) G(3,1)

( i, j ) — data on input i at time slot j

Time Slot 1 Time Slot 2 Time Slot 3

42

Fig. 2.22. Equivalent of time-space-time switching and three-stage space switching

These lines correspond to time slot 1

(1) (1) (1)

(2) (2) (2)

(3) (3) (3)

Module (i) correspondsto input TSI (i) intime-space-time switch

Module (i) correspondsto time slot i ofspace-division switch intime-space-time switch

Module (i) correspondsto output TSI (i) intime-space-time switch

A(1,1)

D(2,1)C(1,3)B(1,2)

F(2,3)E(2,2)

L(3,3)H(3,2)G(3,1)

A(1,1)

D(2,1)

C(1,3)

B(1,2)F(2,3)

E(2,2)

L(3,3)H(3,2)

G(3,1)

43~END~