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Novel 4F2 Buried-Source-Line STT MRAM CellWith Vertical GAA Transistor as Select Device

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Shivam Verma, Student Member, IEEE, Shalu Kaundal, Student Member, IEEE,and Brajesh Kumar Kaushik, Senior Member, IEEE

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Abstract—Spin transfer torque (STT) magnetic random access5memories (MRAMs) have recently emerged as one of the strongest6contenders for universal memory technology. They have entire7range of features, i.e., high speed, nonvolatility, high density, and8low power, which make them cynosure to every memory designer’s9notion. Researchers are working ardently to use STT MRAMs un-10der continuously increasing scaling challenges. To accommodate a11larger amount of embedded memory, the cell size must be reduced.12Therefore, the designs target to attain an optimistic figure of 4F213(F being the feature size) array density, which is the maximum14achievable two-dimensional (2-D) density. With this objective in15mind, a novel 4F2 buried-source-line (SL) STT MRAM cell struc-16ture with a vertical gate all around (GAA) cylindrical buried source17NMOS transistor is proposed. The magnetic tunnel junction (MTJ)18multilayer structure is stacked above the select device with both oc-19cupying the same 2-D area. The diameters of perpendicular MTJ20and vertical silicon nanowire are equal (i.e., F). Device simula-21tions have been carried out on TCAD for buried source vertical22GAA device structure. Furthermore, these TCAD results are used23to calibrate the BSIM CG model for cylindrical GAA transistors.24The proposed STT MRAM cell is then analyzed using calibrated25Verilog-A models for perpendicular anisotropy MTJ and vertical26GAA NMOS transistor (BSIM CG). The performance analysis in27terms of read stability, write margins, and power dissipation for28the proposed cell is also presented.29

Index Terms—Magnetic tunnel junction (MTJ), perpendicular30magnetic anisotropy (PMA), spin transfer torque (STT), vertical31gate all around (GAA).32

I. INTRODUCTION33

ANALOGOUS to a typical memory system, spin transfer34

torque (STT) magnetic random access memory (MRAM)35

consists of memory cells connected to form an array. Conven-36

tionally, each cell is composed of a storage element as magnetic37

tunnel junction (MTJ) and a planar NMOS transistor as select38

device. An MTJ consists of two ferromagnetic (FM) layers sep-39

arated by a nonmagnetic insulator layer. The resistance of MTJ40

depends on the magnetization orientations of the two FM lay-41

ers. Each cell stores data as the resistance state of an MTJ. The42

resistance state of MTJ is high (binary 1), if the two FM layers43

have antiparallel (AP) alignment of magnetization. Conversely,44

Manuscript received January 29, 2014; accepted July 31, 2014. Date of pub-lication; date of current version. The review of this paper was arranged byAssociate Editor A. Martinez.

The authors are with the Microelectronics and VLSI Group, Departmentof Electronics and Communication Engineering, Indian Institute of Technol-ogy Roorkee, Roorkee 247667, India (e-mail: shivamvermaid@gmail.com;shalupec@iitr.ac.in; bkk23fec@iitr.ac.in).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2014.2346790

it is low (binary 0) if the magnetization orientations of the two 45

FM layers have a parallel (P) alignment. 46

Embedded memory can be accessed faster as compared to the 47

external memory; hence, there is a continuously increasing quest 48

for an on-chip embedded memory. Moreover, in almost every 49

memory technology, the select devices have been the bottleneck 50

toward increasing the integration density [1]. Keeping this in 51

mind, several novel architectures for select devices have been 52

proposed by researchers working in the area [2]–[5]. They have 53

been primarily focusing on vertical select devices to reduce the 54

cell area. Kawahara et al. [6] analyzed memory cell scalability 55

for STT MRAMs for various transistor gate widths and informed 56

the possibility of cell area reduction up to 4F2 with a vertical 57

select device. However, till date no thorough analysis has been 58

presented for vertical select device driving STT MRAM cells. 59

In the conventional in-plane MTJ technology, the switching 60

current is quite high (200–1200 μA) [7], [8]. Such high current 61

drive could not be achieved with minimum-sized transistors, 62

and hence, scaling toward 4F2 array density per cell is not fea- 63

sible for STT MRAMs with in-plane MTJs. However, with the 64

evolution of perpendicular magnetic anisotropy (PMA) MTJs 65

(with switching current as low as 20–100 μA or even less), one 66

can see decent prospects for higher integration density in STT 67

MRAMs. 68

The planar MOSFETs have a saturation drive current per 69

unit width of 900 μA/μm for high-performance logic [9]. On 70

the other hand, gate all around (GAA) MOSFETs have been 71

reported to have a much higher saturation drive current of 2.6– 72

2.9 mA/μm per unit diameter [10]. Hence, GAA transistor with 73

the same diameter should provide a larger drive current. A ver- 74

tical GAA transistor can act as an ideal select device that can 75

provide sufficient drive current for efficient switching of an 76

MTJ. In addition, it will provide a cell size of minimum 2-D 77

area. Considering these facts, this paper proposes a novel STT 78

MRAM cell with vertical GAA transistor as select device with 79

a buried source line (SL) and word line (WWL). The objective Q180

is to improve or retain the other performance specifications (ac- 81

cess time read and write margins) with the proposed 4F2 STT 82

MRAM cell. A detailed analysis is done taking into account 83

the design considerations and the constraints for an efficient 84

STT MRAM cell. The proposed cell is also compared with the 85

minimum-sized cell that can be realized with a planar select 86

device. 87

The paper is divided into seven sections, including the in- 88

troductory section. The architecture and functionality of the 89

proposed STT MRAM cell are presented in Section II. Section 90

III analyzes the recent advances in the field of PMA MTJs for 91

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Fig. 1. (a) Typical STT MRAM cell. (b) Front view of the proposed STTMRAM cell.

creating Verilog-A models based on experimental results. Sec-92

tion IV focuses on the design considerations (read, write mar-93

gins and switching probability) of an STT MRAM cell from the94

perspective of select devices. Section V describes the TCAD95

analysis of the proposed buried source GAA device followed96

by the load line analysis. Section VI analyzes and compares97

the HSPICE simulation results of the proposed STT MRAM98

cell with conventional STT MRAM cell. Finally, in Section99

VII, conclusions are drawn based on the analysis done in the100

previous sections.101

II. PROPOSED STT MRAM ARCHITECTURE102

STT MRAMs have three-dimensional (3-D) integration of103

MTJs with conventional CMOS technology. The memory cell104

of STT MRAMs has one MTJ and one NMOS select device,105

abbreviated as a 1T-1MTJ cell. The structure and properties of106

a typical 1T-1MTJ STT MRAM cell can be understood through107

Fig. 1(a). The bottom layer (pinned or fixed layer) of an MTJ108

has fixed magnetization due to its comparatively high magnetic109

coercivity. The top layer of the MTJ is known as free/recording110

layer whose magnetization can be switched by the spin torque111

acting on it. This spin torque is generated by the electric cur-112

rent, which is spin polarized by the pinned bottom layer. The113

directions of current for writing 1 and 0 are shown in Fig. 1(a).114

A current from BL to SL would make the magnetization ori-115

entation as P (to write a 0). Conversely, a current from SL to116

BL would make the magnetization states of two layers as AP (to117

write a 1). Besides this, for both the directions, the write currents118

need to be above a minimum threshold value for proper switch-119

ing of the MTJ. The front view of the proposed architecture120

is shown in Fig. 1(b) that consists of a PMA MTJ multilayer121

structure stacked above the vertical GAA cylindrical NMOS122

transistor. The bit line (BL) and buried SL are perpendicular to123

the plane of paper, while the WWL is in the plane of the paper.124

The proposed GAA structure allows the maximum possible 2-D125

array density for STT MRAMs.126

III. ANALYSIS OF PRACTICALLY FABRICATED PMA MTJS 127

PMA MTJs offer low critical currents and higher thermal sta- 128

bility and scalability for STT switching. Lee et al. [11] demon- Q2129

strated a PMA in Fe-rich CoFeB free layers due to the reduction 130

of demagnetizing field. The demagnetizing field decreases with 131

increase in perpendicular anisotropy and eventually leads to a 132

layer with perpendicular easy axis. The effective demagnetizing 133

(4πMeff ) field is expressed as 134

4πMeff = 4πMS − Hkp (1)

where Hkp is the perpendicular uniaxial anisotropy, Ms is the 135

magnetization of the layer and 4πMs is the demagnetizing field. 136

When Hkp exceeds 4πMs , the magnetic moment of CoFeB 137

has an easy axis perpendicular to the plane of MTJ. The low 138

switching current density is attributed to Hkp , which cancels 139

the effect of the out of plane demagnetizing field 4πMs . 140

Ikeda et al. [7], [12] demonstrated that the performance of 141

CoFeB/MgO/CoFeB based PMA MTJ with 40 nm diameter 142

shows excellent properties that includes a high stability factor 143

(E/KB T = 39) and low switching current (IC0 = 49μA). The 144

only limitation is large write voltage due to high resistance area 145

(RA) product, which leaves a scope of improvement. Moreover, 146

Gajek et al. experimentally analyzed spin torque switching of 147

PMA MTJ with a diameter of 20 nm. However, the results are 148

not as promising because of a low TMR (57%) [13]. Hence, Q3149

experimental results (shown in Table I) for 40 nm PMA MTJ 150

are used to develop a Verilog-A model that precisely replicates 151

the behavior and properties [14]. 152

IV. DESIGN CONSIDERATIONS 153

The select device in a typical memory system allows a mem- 154

ory cell to be accessible for read and write. This section describes 155

the design considerations of STT MRAMs from the perspective 156

of select devices. Fig. 2(a) and (b) represents the two states of 157

the STT MRAM cell before the write operation is performed. 158

Fig. 2(a) shows the equivalent circuit with polarity of BL and 159

SL trying to write a 0 into the cell (P write). Likewise, Fig. 2(b) 160

shows the equivalent circuit with the polarities of BL and SL 161

trying to write a 1 into the cell (AP write). Hence, an STT 162

MRAM cell can be viewed as an NMOS transistor with RP or 163

RAP connected to it as load. 164

The switching of MTJ depends on the direction of current and 165

also a minimum threshold current (IC0) required for switching 166

to occur. Hence, the primary consideration is that whether the 167

select device can provide sufficient drive current for MTJ switch- 168

ing in either direction. The driving current must be sufficiently 169

high to surmount the switching threshold with high switching 170

probability for proper operation of the STT MRAM cell. 171

A write error occurs when the strength of the write current is 172

not enough, and there is a probability that the desired data may 173

not be written into the cell [15]. Furthermore, a read disturb 174

is the unintentional write due to the read current flowing in a 175

direction; this lowers the switching energy barrier [15], [16]. 176

The write error rate (WER) and read disturb rate (RDR) for 177

STT-MRAM cell are determined from the switching probability. 178

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TABLE IPRACTICALLY FABRICATED MTJ PARAMETERS FOR CURRENT PULSEWIDTH OF 1 ns

Barrier/recording layer structure (nm) Diameter(nm)

TMR(%)

RA(Ω ·μm2)

Δ = E/kB T RP (kΩ) RA P (kΩ) IL H 0 (μA) IH L 0 (μA) VW (V) Reference

MgO(�0.85)/CoFeB(�1.7)/Ta 40 113 16 39 12.73 27.1 �72 �28 0.608 [7]

VW = JC 0 (RA) is the mean write voltage, where JC 0 is the switching current density and RA is the resistance area product. RA P = 27.1 kΩ and TMR = 113% are thezero-bias values for the PMA MTJ from [7].

Fig. 2. (a) Equivalent circuit of STT MRAM cell before MTJ switching withAP resistance as load. (b) Equivalent circuit of STT MRAM cell before MTJswitching with P resistance as load. (c) Top view of the vertical GAA NMOSdevice. (d) Front view of the vertical GAA NMOS device.

WER and RDR are expressed as179

RDR = PSW, WER = 1 − PSW (2)

where PSW is the probability of occurrence of switching below180

critical switching current (IC0) that is expressed as [15]181

PSW = 1 − exp{− tPW

τ0exp

[− E

kB T

(1 − I

IC0

)]}(3)

where tPW is the current pulsewidth, τ0 is the attempt time, IC0182

is the critical current required for switching, and E/kB T is the183

Boltzmann’s factor.184

The drain current (ID ) should be very small, when the cell185

has not been selected (WWL = 0) for reading or writing. The186

current through the cell with WWL = 0 should be small enough187

so that the switching probability is negligible, preferably below188

10−9 [15]. This means that the select device should offer very189

small off the current even though BL or SL is equal to VDD .190

Write margin is defined as the difference between the writing191

current and critical switching current of an MTJ [16]. The write192

current must be sufficiently high to obtain a cell with large193

write margins and small switching time. Different write margins194

are defined for P (WMP ) or AP (WMAP ) write into the cell. The195

write current for P writing IWP0 should have a direction from196

free layer (BL) to the pinned layer (SL) of an MTJ. Conversely,197

the write current for AP writing IWAP0 should have a direction198

from pinned layer (SL) to free layer (BL). WMP and WMAP199

are expressed as 200

WMP = (IWP0 − IHL0), WMAP = (IWAP0 − ILH0)(4)

where IHL0 and ILH0 are AP to P and P to AP critical switching 201

currents, respectively. 202

Read margin is defined in terms of sensing current (read cur- 203

rent) as the normalized difference between the critical switching 204

current and read current (sensing current) [16]. Analogous to 205

write margins, different read margins would be defined for P 206

(RMP ) and AP (RMAP ) reading mechanisms. The read current 207

during P reading has a direction from free layer (BL) to the 208

pinned layer (SL) of an MTJ. Likewise, the read current during 209

AP reading has a direction from pinned layer (SL) to free layer 210

(BL) of an MTJ. The RMAP and RMP are expressed as 211

RMP =IHL0 − IP0

IHL0, RMAP =

ILH0 − IAP0

ILH0(5)

where IP0 and IAP0 are the read currents during P and AP 212

reading, respectively. 213

Write access time (tP and tAP ) is defined as the time required 214

for switching the state of MTJ at the particular write current 215

and write current pulsewidth. The switching time also depends 216

on the switching threshold at that write current pulse duration 217

(tPW ) [14]. 218

V. VERTICAL GAA TRANSISTOR AS SELECT DEVICE 219

Conventionally, the overall area of the STT MRAM cell has 220

been dominated by the select device [1]. The proposed structure 221

allows us to accommodate the MTJ and select device within the 222

same area through 3-D stacking. In this section, the proposed 223

select device structure is thoroughly analyzed. The analysis has 224

been carried out for feature size F = 40 nm, which is same as 225

the diameter of the MTJ to keep the overall cell area 4F 2 . The 226

proposed structure with a buried source of diameter 2F is shown 227

in Fig. 2(c) and (d). The source is extended upward to a height 228

of 40 nm (F) so that the gate and source are not shorted together. 229

The diameter of the extension region is also F (40 nm). Drain 230

is at the top having a diameter and length of F (40 nm). Device 231

simulations are carried out for the proposed GAA structure on 232

Silvaco Atlas [17] (TCAD device simulator) for gate/channel 233

lengths (Lch ) of 40 (F), 80 (2F), and 120 nm (3F). The buried 234

oxide layer has not been shown for simplicity. 235

Source, drain, and source extension regions are heavily doped 236

with a uniform n-type doping concentration of 1 × 1020cm−3. 237

The channel is uniformly doped with p-type impurity concentra- 238

tion of 1 × 1016cm−3. The work function and gate oxide thick- 239

ness of the cylindrical gate are 4.61 eV and 2 nm, respectively. 240

The heavily doped extension region ensures a high current drive. 241

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TABLE IITCAD RESULTS OF GAA DEVICE FOR DIFFERENT GATE LENGTHS

L ch V t l in (V) DIBL (mV/V) Io n (μA) Io n /Io f f SS (mV/decade)

40 0.279 115 214.6 3.8×103 103.080 0.300 22.1 194 3.3×106 63.4120 0.307 13.6 175.5 1.5×107 60.3

TABLE IIITCAD RESULTS OF PLANAR NMOS DEVICE

W (nm) L ch (nm) V t l in (V) DIBL (mV/V) Io n (μA) Io n /Io f f SS (mV/decade)

40 80 0.250 354 85.8 18.29 768.340 120 0.275 280 72.8 142.8 294.280 120 0.275 310 145.6 142.7 294.2

A. TCAD Analysis of the Proposed Structure242

The ID−VDS and ID−VGS characteristics are analyzed us-243

ing 3-D TCAD device simulation of the proposed structure.244

Threshold voltage, drain-induced barrier lowering (DIBL), sub-245

threshold slope (SS), and Ion/Ioff are calculated for Lch of 40,246

80, and 120 nm. The method used for threshold voltage extrac-247

tion is “the linear extrapolation method in the linear region,”248

which is also commonly known as “maximum transconduc-249

tance method” [18], [19]. The magnitude of on current (Ion )250

and off current (Ioff ) are calculated at VGS = VDS = 1.6 V and251

VGS = 0, VDS = 1.6 V, respectively. DIBL is defined as the nor-252

malized difference in threshold voltages when VDS is changed253

from VDS lin and VDS sat254

DIBL =Vt lin − Vt sat

VDS sat − VDS lin(6)

where Vt lin and Vt sat are the threshold voltage in the linear255

(very low VDS ) and saturation regions, respectively. The values256

of VDS sat and VDS lin are 1.6 and 0.05 V, respectively. Vt sat257

is the value of VGS on ID−VGS curve at VDS = VDS sat re-258

quired to get the same value of current, which is obtained when259

VGS = Vt lin and VDS = VDS lin . The subthreshold slope (SS)260

is the change in VGS required to alter the subthreshold drain261

current by one decade (ten times). The corresponding results262

are shown in Table II. Although the device with 40 nm gate263

length has the largest current drive, but it severely suffers from264

short channel effects. The DIBL, off-current, and subthreshold265

slope parameters are comparatively large for the device with266

40 nm gate length. It is because of lower electrostatic gate con-267

trol at smaller gate length. Evidently, the device with 120 nm268

gate length demonstrates the best performance. In order to com-269

pare with the conventional STT MRAM cell, TCAD simula-270

tions are carried out for planar NMOS transistor also. The gate271

work function and oxide thickness of the planar NMOS are272

4.61 eV and 1.5 nm, respectively. However, the source, drain,273

and channel doping is same as that for GAA NMOS. The perfor-274

mance parameters calculated for planar transistor for different275

device dimensions are placed in Table III. The performance of276

the planar transistor is poor, especially for small gate length,277

Fig. 3. Comparison of the ID−VGS characteristics of GAA (40 nm nanowirediameter and Lch = 120 nm) and planar (W = 80 nm and Lch = 120 nm)NMOS.

Fig. 4. Comparison of |ID | − |VDS | characteristics with top as drain andbottom as drain operation for the GAA NMOS of Lch = 120 nm.

due to large short channel effects that are measured at a high 278

VDD of 1.6 V. Although, the short channel effects of the planar 279

NMOS can be reduced by decreasing the source and drain dop- 280

ing concentration, but that will reduce Ion also. A comparison 281

of ID−VGS characteristics is shown in Fig. 3, which confirms 282

that GAA NMOS has much lower off current than the planar 283

NMOS devices. 284

For SL = VDD and BL = 0, the vertical GAA transistor 285

would be operating with drain as bottom and top as source. 286

Therefore, the ID−VDS characteristics of the proposed structure 287

should also be analyzed with bottom [buried source in Fig. 2(d)] 288

as drain. However, Fig. 4 clearly shows a minute difference 289

between |ID | − |VDS | characteristics under the two modes of 290

operation. This difference can be safely neglected in the subse- 291

quent analysis and the device can be considered to be having 292

symmetric I–V characteristics. 293

B. DC Load Line Analysis 294

In this section, dc load line analysis is carried out to ascertain 295

that the vertical GAA transistor provides sufficient drive cur- 296

rent for proper operation of the proposed STT-MRAM cell [20]. 297

The ID−VDS characteristics obtained from TCAD simulation 298

for the proposed structure [see Fig. 2(d)] are used for the load 299

line analysis. Moreover, ID−VDS characteristics obtained from 300

TCAD simulations of planar NMOS with 120 nm gate/channel 301

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length are also included in the load line analysis. The mini-302

mum width (W = F = 40 nm) planar NMOS has a low Ion as303

compared to GAA (Tables II and III). Hence, the comparison304

would be more appropriate with a planar NMOS of width 80 nm305

(W = 2F = 80 nm), that has Ion comparable to the GAA de-306

vice. The value of VDS , as deduced from Fig. 2(a) and (b) is307

expressed as308

VDS = VDD − ID RMTJ (7)

where RMTJ is the resistance of MTJ. The RMTJ and TMRQ4

309

parameters vary considerably with bias voltage across the MTJ,310

when in AP state [14], [15]. The AP resistance (RAP ) and TMR311

of an MTJ are expressed as312

RAP(Vbias) = RP {1 + TMR(Vbias)}

TMR(Vbias) =TMR(0)

1 + (V 2bias/V 2

h )(8)

where Vbias is voltage across MTJ and Vh(= 0.5V) is the fitting313

parameter [14]. Hence, both RAP and TMR reduce with an in-314

crease in Vbias as compared to their zero-bias values according315

to (8) for Vbias > 0. RAP is considered as 20 kΩ (value of RAP316

at Vbias = 0.5) based on the safe assumption that Vbias ≥ 0.5 V317

at VGS > Vt and VDD ≥ 1 V. This assumption is perfectly safe,318

because the on resistance (for VGS greater than Vt) of NMOS319

is comparatively lower than the resistance of the MTJ. Thus,320

two load lines are drawn corresponding to the loads of RP =321

12.73 kΩ and RAP = 20 kΩ as shown in Fig. 5. The point of in-322

tersection between the load line and ID − VDS curves represents323

the operating point of the NMOS. The corresponding value of324

ID should be high enough for providing a drive current larger325

than the critical switching current of MTJ in either direction. The326

dotted lines show the critical MTJ switching currents ILH0 =327

72 μA and IHL0 = 28 μA in Fig. 5. As expected, the primary328

cause of concern is the comparatively high critical switching329

current required for P to AP switching (ILH0) [15]. The current330

ILH0 is higher, since the electrons reflected from the pinned331

layer switch the state of MTJ. The points of intersection (oper-332

ating points) of ID −VDS curve with the P and AP load lines333

are worth noting. The drain current ID at the operating point334

corresponding to load RP (RAP ) should be higher than the335

critical switching current ILH0 (IHL0). At VGS = 1.2, ID (for336

GAA) barely overcomes ILH0 (P load line), while at VGS equal337

to 1.4 and 1.6 V, ID (for GAA) exceeds ILH0 by 19 and 36 μA,338

respectively. Hence, the load line analysis shows that vertical339

GAA transistor can provide a sufficient drive current for switch-340

ing MTJ in either direction when VDD ≥ 1.4 V. Besides, it is341

evident from Fig. 5 that, to achieve a drive current close to342

GAA, the planar transistor of width 80 nm (2F) is required and343

the minimum width transistor (W = F = 40 nm) does not pro-344

vide sufficient current driving capability. The cell area for such345

a cell is exorbitantly higher, i.e., 10F 2 , the layout of which is346

shown in Fig. 6(a).347

C. BSIM CG Model Calibration348

BSIM CG is a part of the combined multigate (MG) model349

BSIM CMG coded in Verilog-A, which captures the behavior of350

all MG and GAA transistors [21], [22]. Appendix I depicts the 351

steps along with parameters to calibrate BSIM CG according to 352

TCAD results for the proposed GAA structure (40 nm diameter 353

and 120 nm gate length). The results of HSPICE simulation of 354

calibrated model are shown and compared with TCAD results 355

in Fig. 6(b) and (c). The ID − VDS and ID − VGS characteris- 356

tics show that the model closely replicates the TCAD results. 357

Henceforth, it can be used for further analysis of the proposed 358

STT MRAM cell. 359

VI. ANALYSIS OF PROPOSED STT MRAM CELL 360

The proposed STT MRAM cell and conventional cell with 361

planar transistor are analyzed using transient and dc simula- 362

tions on HSPICE using calibrated Verilog-A models. The lay- 363

out of the 10F2 (F = 40 nm) conventional cell is shown in 364

Fig. 6(c). For the circuit analysis of this 10F 2 planar cell, 365

BSIMSOI [23] Verilog-A model for planar SOI NMOS is cali- 366

brated from TCAD results using the same methodology given in 367

Appendix I for BSIM CG. The behavior of the two cells during 368

read is analyzed by performing dc analysis for P read scheme. 369

The bit stored in the STT MRAM cell (MTJ state) is read out 370

by applying WWL = VDD and a read voltage (VR ) between 371

BL and SL. The P read scheme employs BL = VR and SL = 0 372

during read operation. An optimum read voltage at BL is found 373

by simultaneous consideration of TMR degradation effect with 374

MTJ bias voltage and read current difference between P and AP 375

states of MTJ [24]. Since this read current has to be compared 376

with a reference current to read the data, the difference in cell 377

current between 0 and 1 stored cells should be high enough 378

to be discernible. In addition, TMR should be high during the 379

read operation, which decreases with an increase in read cur- 380

rent (or with an increase in MTJ bias voltage) expressed in (8). 381

The optimum read voltage is found to be 0.4 V [see Fig. 7(a)] 382

with a read current difference of 10 μA and TMR = 0.75 for 383

the GAA cell. Fig. 7 (a) also shows that, the read performance 384

of the two cells is similar. The read margins (RMP ) plotted in 385

Fig. 7 (b) further confirm the analogous read behavior, which 386

is expected because both the NMOS devices are in deep linear 387

region with very little difference currents during read operation. 388

The dynamic behavior of the proposed cells [see Fig. 8 and Ta- 389

ble IV] is verified by a series of write, hold, and read operation 390

cycle in terms of time at VDD of 1.6 V. The pulsewidth (tPW ) 391

of every cycle is 1 ns with rise and fall times of 0.1 ns. The 392

initial state of MTJ is considered as AP. The P read operation 393

is performed keeping WWL = 1.6 V with SL = 0 and BL = 394

0.4 V [24]. All entries in Table IV are measured at the midpoint 395

of each cycle or after the write operation is complete, in case of 396

write cycle. 397

The dynamic and leakage power of the two cells is obtained 398

from a transient analysis by keeping WWL equal to 1.6 and 0 V, 399

respectively. In addition, SL and BL are applied with a square 400

wave pulse of period 2 ns (50% duty cycle) with amplitude 401

of 1.6 V (VDD ) in both cases. During the analysis, SL is kept 402

as logical complement of BL such that when SL = 0, BL = 403

1.6 V, and vice versa. Again, the initial state of MTJ is consid- 404

ered as AP. Furthermore, write margins are also calculated for 405

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Fig. 5. Load-line analysis of vertical GAA (40 nm nanowire diameter and Lch = 120 nm) and planar NMOS (gate length of 120 nm) at different VGS (= VDD )corresponding to P and AP resistance as load. (a) For VGS = 1.6 V, (b) for VGS = 1.4 V, and (c) for VGS = 1.2. Red and black lines represent P and AP loadlines, respectively, in each of (a), (b), and (c). ILH0 and IHL0 are 72 and 28 μA, respectively.

Fig. 6. (a) Cell layout of conventional 10F 2 STT MRAM cell with planar select device. (b) Comparison of ID − VGS characteristics of calibrated BSIM CGwith TCAD results at VDS = 1.6 V. (c) Comparison of ID − VDS characteristics of calibrated BSIM-CG with TCAD results.

Fig. 7. (a) Variation of TMR and read current difference with read voltage (WWL = VDD = 1.6 V and SL = 0 V). (b) Variation of read margin (RMP )and write margins WMP with WWL = VDD . The analysis is done keeping BL = 0.4 V and SL = 0 V with the initial state of MTJ considered as AP.(c) Comparison of dynamic power dissipation (with WWL = 1.6 V) of the two cells in terms of VDD .

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TABLE IVTIMING ANALYSIS OF THE PROPOSED 4F2 GAA CELL AND 10F2 PLANAR CELL

Parameter Hold (initial state AP) Write 0 Hold Read 0 (P read) Hold Write 1 Hold Read 1 (P read) Hold

Bias voltages SL 0 0 0 0 0 1.6V 0 0 0BL 0 1.6 V 0 0.4 V 0 0 0 0.4 V 0

WWL 0 1.6 V 0 1.6 V 0 1.6V 0 1.6 V 0Planar Ic e l l (μA) 0 55.1 0 25.2 0 −92 0 15.7 0

RM T J (kΩ) 27.1 12.73 12.73 12.73 27.1 14.46 27.1 22.4 27.1TMR 1.13 – – – – 0.14 1.13 0.76 1.13

MTJ State AP (1) P (0) P (0) P(0) P(0) AP (1) AP (1) AP (1) AP (1)GAA Ic e l l (μA) 0 61.3 0 26.5 0 −95.8 0 16.3 0

RM T J (kΩ) 27.1 12.73 12.73 12.73 12.73 14.41 27.1 22.20 27.1TMR 1.13 – – – – 0.13 1.13 0.74 1.13

MTJ state AP (1) P (0) P (0) P(0) P(0) AP (1) AP (1) AP (1) AP (1)

Fig. 8. Timing diagram showing successful operation of the proposed 4F 2

STT MRAM cell at VDD = 1.6 V.

the proposed 4F 2 and conventional 10F 2 cell. The correspond-406

ing results are tabulated in Table V. Undoubtedly, the proposed407

cell demonstrates a better performance in terms of power dis-408

sipation and write margins. The leakage power dissipation for409

the proposed cell is four to five orders of magnitude lower than410

conventional cell (when the cell is not selected for writing). The411

dynamic power dissipation at WWL = 1.6 V (VDD ) is higher;412

although, here the point of consideration is that the dynamic413

power always has a tradeoff with the P and AP write margins414

(write currents). There is a larger tradeoff window between the415

write margin and dynamic power dissipation in the case of pro-416

posed cell with GAA device, as it can operate with VDD as low417

as 1.3 V (at tPW = 1 ns) by sacrificing the write margins. It is418

clearly observed in Fig. 7(b) that the planar cell cannot operate419

correctly at VDD = 1.3 V for tPW = 1 ns. Moreover, a com-420

parison of the dynamic power dissipation between the cells in421

terms of VDD in Fig. 7(c) shows that the proposed cell can be422

optimized for low-power operation also.423

VII. CONCLUSION424

The proposed STT MRAM cell offers better performance425

over the conventional STT MRAM cell from all perspectives.426

The biggest improvements are in terms of area and leakage427

power dissipation. The proposed cell occupies a much smaller428

area of 4F 2 with a 60% reduction in area from its conventional 429

counterpart, and still offers a much better performance. Hence, 430

to achieve high density STT MRAMs, the 4F 2 cell with vertical 431

GAA transistor is potentially better solution than 6–10 F2 cell 432

with planar transistor. The leakage power dissipation of the pro- 433

posed cell is comparatively much smaller, when the cell is not 434

selected for writing (WWL = 0V ). In addition, the proposed 435

cell shows excellent write margins and can be optimized for 436

low power operation. Despite the high write currents, the read 437

behavior is not compromised, as the proposed cell offers good 438

read stability and high read margins. Moreover, the read disturb 439

rate is lower than 10−7 up to read voltage VR = 0.4 V with 440

a read current difference of 10 μA between 0 (P) and 1 (AP) 441

stored cells. These advantages have been possible by the virtue 442

of vertical GAA NMOS. The proposed select device offers ex- 443

cellent gate control (Ioff = 12 pA) and high current drive along 444

with the attainment of maximum 2-D array density. These im- 445

provements should proliferate even more with subsequent down 446

scaling of the STT MRAM cell. 447

APPENDIX IBSIM CG MODEL CALIBRATION 448

The important parameters and model calibration methodol- 449

ogy for configuring BSIM CG for cylindrical GAA operation 450

are classified and discussed as follows: 451

A. Geometry and Material Parameters: The geometry 452

and material parameters of BSIM CMG are set for a vertical 453

GAA device operation, according to the parameters used for 454

TCAD simulation (see Table VI). 455

B. Threshold Voltage Calibration: The threshold voltage 456

of BSIM CG is expressed as 457

Vth = Vth0 + ΔVth,SCE + ΔVth,DIBL + DVTSHIFT (A1)

where Vth0 is the threshold voltage of the model based on sur- 458

face potential calculations. ΔVth,SCE is the threshold voltage 459

degradation due to short channel effects, ΔVth,DIBL is used 460

to model the effect of drain voltage on threshold voltage, and 461

DVTSHIFT is to handle any additional shift in Vth [21]. 462

The model equation for ΔVth,SCE in BSIM CG [21] is 463

ΔVth,SCE = − 0.5DVT0cosh {DVT1 (Leff /λ)} − 1

(Vbi − ψst)

(A2)

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TABLE VCOMPARISON BETWEEN PROPOSED CELL AND 10F2 PLANAR NMOS

Select Device WMP (μA) WMA P (μA) tp (ns) tA P (ns) Power (pW) WWL = 0 V Power (μW) WWL = 1.6 V

GAA 23.3 34.0 0.43 0.25 16.2 112.4Planar 17.6 29.0 0.52 0.32 1140 107.0

TABLE VIGEOMETRY AND MATERIAL PARAMETERS

BSIM Model Parameter Value Description[21]

GEOMOD 3 Cylindrical GAABULKMOD 0 SOI substrateASYMMMOD 1 Asymmetric deviceCOREMOD 0 Surface potential modelL 120 nm Gate lengthD 40 nm Gate diameterEOT 2 nm Gate oxide thicknessNGATE 0 Metal gateNSD 1 × 1020 cm–3 S/D doping concentrationPHIG 4.61 eV Gate work functionNBODY 1 × 1016 cm–3 Channel doping

where Vbi = (kB T/q) ln{NSD ∗ (nbody/n2

i )}

,464

ψst = 0.4 + (kB T/q) ln(nbody/ni), and λ =465 √(εsi · R · EOT/2εox) {1 + (R · εox/2εsi · EOT)}.466

Leff is the effective channel length. The model equation for467

ΔVth,DIBL in BSIM CG is expressed as [22]468

ΔVth,DIBL = − 0.5ETA0cosh (DSUB (Leff /λ)) − 1

VDS

+ DVTP0 ∗ VDSDVTP1 (A3)

TCAD simulation is carried to calculate ΔVth,SCE and469

ΔVth,DIBL and then (A1)–(A3) are used to set threshold voltage470

parameters accordingly (see Table VII).471

C. Mobility and Drain Current Parameters: Average low472

field mobility is calculated using TCAD simulations for the473

on state (VGS > Vth and VDS = 0.05) of the device. The low474

field mobility is found to be 650 cm2/(V·s). Further, U0MULT475

(multiplier to mobility) and IDS0MULT (multiplier to source–476

drain channel current) are set, which are dedicated to variability477

modeling and can be set by the user appropriately [21]. Mobility478

and drain current parameters are shown in Table VIII.479

D. Parasitic Capacitance, Subthreshold, and Leakage480

Current Parameters: AC analysis is done at a frequency of481

1 MHz with a low VDS (load line analysis in Section V shows482

that the NMOS will be invariably in the linear region of oper-483

ation). Hence, at |VDS | = 0.2 V, the average values of capac-484

itances are calculated. The average gate to source capacitance485

CGS and gate-to-drain capacitances CGD are found to be 0.087486

and 0.1 fF/μm, respectively. The parameters concerned with487

parasitic capacitance and subthreshold conduction are placed in488

Table IX.489

TABLE VIITHRESHOLD VOLTAGE PARAMETERS

BSIM Model Parameter VALUE Description [21]

DVT0 2.2 SCE coefficientDVT1 0.177 SCE exponent coefficientETA0 1 DIBL coefficientDSUB 0.80 DIBL exponent coefficientDVTP0 0 Coefficient for drain-induced V t h shiftDVTP1 0 Exponent coefficient for drain-induced V t h shiftDVTSHIFT 0 Additional V t h shift handle

TABLE VIIIMOBILITY AND DRAIN CURRENT PARAMETERS

BSIM Model Parameter Value Description [21]

U0 650 cm2/V·s Low field mobilityIDS0MULT 5 Multiplier to source–drain channel currentU0MULT 0.62 Multiplier to mobility

TABLE IXPARASITIC CAPACITANCE, SUBTHRESHOLD, AND LEAKAGE CURRENT

PARAMETERS

BSIM Model Parameter Value Description [21]

CGEOMOD 1 Parasitic capacitance model selectorCGEO1SW 1 Capacitance unit selectorCOVS 0.1 fF Constant ate to source overlap capacitanceCOVD 0.087 fF Constant gate to drain overlap capacitanceDVT1SS 1.0234 Subthreshold swing exponent coefficientGIDLMOD 1 GIDL/GISL model selectorAGISL 1.05 × 10–15 Preexponential coefficient for GISLAGIDL 1.05 × 10–15 Preexponential coefficient for GIDL

REFERENCES 490

[1] ERD. (2011). International technology road map for semiconductors [On- 491line]. Available: http://www.itrs.net 492

[2] T. Schloesser et al., “6F2 buried wordline DRAM cell for 40 nm and 493beyond,” in Proc. IEEE IEDM’08, San Francisco, CA, USA, pp. 1–4, 494Dec. 2008. Q5495

[3] H. Chung et al., “Novel 4F2 DRAM cell with vertical pillar transis- 496tor(VPT),” in Proc. IEEE ESSDRC, Helsinki, Finland, pp. 211–214, Sep. 4972011. 498

[4] Z. Fang et al., “Fully CMOS-compatible 1T1R integration of vertical 499nanopillar GAA transistor and oxide-based RRAM cell for high-density 500nonvolatile memory application,” IEEE Trans. Electron Devices, vol. 60, 501no. 3, pp. 1108–1113, Mar. 2013. 502

[5] D.-L. Kwong et al., “Vertical silicon nanowire platform for low power 503electronics and clean energy applications,” J. Nanotechnol., vol. 2012, 504pp. 1–21, 2012. 505

[6] T. Kawahara, K. Ito, R. Takemura, and H. Ohno, “Spin-transfer torque 506RAM technology: Review and prospect,” Microelectron. Reliab., vol. 52, 507no. 4, pp. 613–627, Apr. 2012. 508

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[7] S. Ikeda et al., “Recent progress of perpendicular anisotropy magnetic509tunnel junction for non-volatile VLSI,” Spin (World Sci.), vol. 2, no. 3,510pp. 1240003-1–1240003-12, Dec. 2012.511

[8] S. Ikeda et al., “Magnetic tunnel junctions for spintronic memories and512beyond,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 991–1002,5132007.514

[9] PIDS. (2001). International technology roadmap for semiconductors [On-515line]. Available: http://www.itrs.net516

[10] Y. Song et al., “Performance breakthrough in gate-all-around nanowire n-517and p-type MOSFETs fabricated on bulk silicon substrate,” IEEE Trans.518Electron Devices, vol. 59, no. 7, pp. 1885–1890, Jul. 2012.519

[11] K. Lee, J. J. Sapan, S. H. Kang, and E. E. Fullerton, “Perpendicular520magnetization of CoFeB on single-crystal MgO,” J. Appl. Phys., vol. 109,521no. 12, pp. 123910-1–123910-3, Jun. 2011.522

[12] S. Ikeda et al., “A perpendicular-anisotropy CoFeB-MgO magnetic tunnel523junction,” Nat. Mater., vol. 9, no. 9, pp. 721–724, Sep. 2010.524

[13] M. Gajek et al., “Spin torque switching of 20 nm magnetic tunnel junc-525tions with perpendicular anisotropy,” Appl. Phys. Lett., vol. 100, no. 13,526pp. 132408–1-132408-3, Mar. 2012.527

[14] Y. Zhang et al., “Compact modeling of perpendicular-anisotropy528CoFeB/MgO magnetic tunnel junctions,” IEEE Trans. Electron Devices,529vol. 59, no. 3, pp. 819–826, Mar. 2012.530

[15] D. D. Tang and Y. J. Lee, Magnetic memory fundamentals and technology,5311st ed. Cambridge U.K.: Cambridge Univ. Press, 2010, ch. 3–6.532

[16] J. Li et al., “Design paradigm for robust spin-torque transfer magnetic533RAM (STT MRAM) from circuit/architecture perspective,” IEEE Trans.534VLSI, vol. 18, no. 12, pp. 1710–1723, Dec. 2010.535

[17] Silvaco Inc. (2012, Mar.). ATLAS user’s manual [Online]. Available:536www.silvaco.com537

[18] L. Dobrescu et al., “Threshold voltage extraction methods for MOS tran-538sistors,” in Proc. CAS 2000 Int. Semicond. Conf., 23rd ed., 2000, vol. 1,539no. 2, pp. 371–374.

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[19] A. Bazigos et al., “An adjusted constant-current method to determine541saturated and linear mode threshold voltage of MOSFETs,” IEEE Trans.542Electron Devices, vol. 58, no. 11, pp. 3751–3758, Nov. 2011.543

[20] X. Fong, S. H. Choday, and K. Roy, “Bit-cell level optimization for544non-volatile memories using magnetic tunnel junctions and spin-transfer545torque switching,” IEEE Trans. Nanotechnol., vol. 11, no. 1, pp. 172–181,546Jan. 2012.547

[21] V. Sriramkumar et al., BSIM-CMG 107.0.0 Multi-gate MOSFET Compact548Model: Technical Manual, Dept. Elect. Eng. Comp. Sci., Univ. California,549Berkeley, USA, 2013.550

[22] D. Lu, C. H Lin, A. Niknejad, and C. Hu, “Multi-gate MOSFET com-551pact model BSIM-MG,” in Compact Modeling, G. Gidenblat, Ed. The552Netherlands: Springer, pp. 395–429, 2010.

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[23] N. Paydavosi, A. Niknejad, C. Hu, BSIMSOIv4.5.0 MOSFET MODEL554Users’ Manual, Dept. Elect. Eng. Comp. Sci., Univ. California, Berkeley,555USA, 2013.556

[24] T. Kawahara et al., “2 Mb SPRAM (spin-transfer torque RAM) with557bit-by-bit bi-directional current write,” IEEE Trans. Solid State Circuits,

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vol. 43, no. 1, pp. 109–120, 2008.559

Shivam Verma (S’13) received the M.Tech. degree 560in microelectronics from IIT BHU, Varanasi, India, 561in 2012. He is currently working toward the Ph.D. 562degree from the Indian Institute of Technology Roor- 563kee, Roorkee, India. 564

His current research interests include STT 565MRAMs and all spin logic. 566

567

Shalu Kaundal (S’14) received the M.Tech. degree 568in microelectronics and VLSI from the Indian Insti- 569tute of Technology Roorkee, Roorkee, India. 570

Her current research interests include designing 571and modeling of STT MRAMs. 572

573

Brajesh Kumar Kaushik (SM’13) received the B.E. 574degree in electronics and communication engineer- 575ing from D.C.R. University of Science and Technol- 576ogy (formerly C. R. State College of Engineering), 577Murthal, India, in 1994, and the M.Tech. degree in 578engineering systems from Dayalbagh Educational In- 579stitute, Agra, India, in 1997, and the Ph.D. degree 580under AICTE-QIP scheme from the Indian Institute 581of Technology Roorkee, Roorkee, India, in 2007. 582

He was with Vinytics Peripherals Pvt. Ltd., Delhi, 583India, as a Research and Development Engineer in 584

microprocessor, microcontroller, and DSP processor-based systems. He joined 585the Department of Electronics and Communication Engineering, G. B. Pant 586Engineering College, Pauri Garhwal, India, as a Lecturer in July 1998, where 587he was an Assistant Professor from May 2005 to May 2006 and an Associate 588Professor from May 2006 to December 2009. He is currently an Associate 589Professor in the Department of Electronics and Communication Engineering, 590Indian Institute of Technology Roorkee, Roorkee, India. His current research 591interests include in the area of high-speed interconnects, low-power VLSI de- 592sign, carbon-nanotube-based designs, organic thin film transistor design and 593modeling, and spintronics-based devices and circuits. 594

595

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QUERIES596

Q1. Author: Please check the acronym of “word line.” Is this OK as is or should be WL.597

Q2. Author: Please check the edited sentence “PMA MTJs offer . . . switching.” for intended meaning.598

Q3. Author: Please provide the full form of the acronyms BSIM CG and TMR.599

Q4. Author: The variable “j” has been set as “R MTJ.” Please check.600

Q5. Author: Please provide all the names of authors in Refs. [2]–[5], [7], [8], [10], [12]–[14], [16], [21], and [24].601

Q6. Author: Please verify Ref. [18] as set.602

Q7. Author: Please provide the city of the publisher in Ref. [22].603

Q8. Author: Please provide the month information in Ref. [24].604

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Novel 4F2 Buried-Source-Line STT MRAM CellWith Vertical GAA Transistor as Select Device

1

2

Shivam Verma, Student Member, IEEE, Shalu Kaundal, Student Member, IEEE,and Brajesh Kumar Kaushik, Senior Member, IEEE

3

4

Abstract—Spin transfer torque (STT) magnetic random access5memories (MRAMs) have recently emerged as one of the strongest6contenders for universal memory technology. They have entire7range of features, i.e., high speed, nonvolatility, high density, and8low power, which make them cynosure to every memory designer’s9notion. Researchers are working ardently to use STT MRAMs un-10der continuously increasing scaling challenges. To accommodate a11larger amount of embedded memory, the cell size must be reduced.12Therefore, the designs target to attain an optimistic figure of 4F213(F being the feature size) array density, which is the maximum14achievable two-dimensional (2-D) density. With this objective in15mind, a novel 4F2 buried-source-line (SL) STT MRAM cell struc-16ture with a vertical gate all around (GAA) cylindrical buried source17NMOS transistor is proposed. The magnetic tunnel junction (MTJ)18multilayer structure is stacked above the select device with both oc-19cupying the same 2-D area. The diameters of perpendicular MTJ20and vertical silicon nanowire are equal (i.e., F). Device simula-21tions have been carried out on TCAD for buried source vertical22GAA device structure. Furthermore, these TCAD results are used23to calibrate the BSIM CG model for cylindrical GAA transistors.24The proposed STT MRAM cell is then analyzed using calibrated25Verilog-A models for perpendicular anisotropy MTJ and vertical26GAA NMOS transistor (BSIM CG). The performance analysis in27terms of read stability, write margins, and power dissipation for28the proposed cell is also presented.29

Index Terms—Magnetic tunnel junction (MTJ), perpendicular30magnetic anisotropy (PMA), spin transfer torque (STT), vertical31gate all around (GAA).32

I. INTRODUCTION33

ANALOGOUS to a typical memory system, spin transfer34

torque (STT) magnetic random access memory (MRAM)35

consists of memory cells connected to form an array. Conven-36

tionally, each cell is composed of a storage element as magnetic37

tunnel junction (MTJ) and a planar NMOS transistor as select38

device. An MTJ consists of two ferromagnetic (FM) layers sep-39

arated by a nonmagnetic insulator layer. The resistance of MTJ40

depends on the magnetization orientations of the two FM lay-41

ers. Each cell stores data as the resistance state of an MTJ. The42

resistance state of MTJ is high (binary 1), if the two FM layers43

have antiparallel (AP) alignment of magnetization. Conversely,44

Manuscript received January 29, 2014; accepted July 31, 2014. Date of pub-lication; date of current version. The review of this paper was arranged byAssociate Editor A. Martinez.

The authors are with the Microelectronics and VLSI Group, Departmentof Electronics and Communication Engineering, Indian Institute of Technol-ogy Roorkee, Roorkee 247667, India (e-mail: shivamvermaid@gmail.com;shalupec@iitr.ac.in; bkk23fec@iitr.ac.in).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2014.2346790

it is low (binary 0) if the magnetization orientations of the two 45

FM layers have a parallel (P) alignment. 46

Embedded memory can be accessed faster as compared to the 47

external memory; hence, there is a continuously increasing quest 48

for an on-chip embedded memory. Moreover, in almost every 49

memory technology, the select devices have been the bottleneck 50

toward increasing the integration density [1]. Keeping this in 51

mind, several novel architectures for select devices have been 52

proposed by researchers working in the area [2]–[5]. They have 53

been primarily focusing on vertical select devices to reduce the 54

cell area. Kawahara et al. [6] analyzed memory cell scalability 55

for STT MRAMs for various transistor gate widths and informed 56

the possibility of cell area reduction up to 4F2 with a vertical 57

select device. However, till date no thorough analysis has been 58

presented for vertical select device driving STT MRAM cells. 59

In the conventional in-plane MTJ technology, the switching 60

current is quite high (200–1200 μA) [7], [8]. Such high current 61

drive could not be achieved with minimum-sized transistors, 62

and hence, scaling toward 4F2 array density per cell is not fea- 63

sible for STT MRAMs with in-plane MTJs. However, with the 64

evolution of perpendicular magnetic anisotropy (PMA) MTJs 65

(with switching current as low as 20–100 μA or even less), one 66

can see decent prospects for higher integration density in STT 67

MRAMs. 68

The planar MOSFETs have a saturation drive current per 69

unit width of 900 μA/μm for high-performance logic [9]. On 70

the other hand, gate all around (GAA) MOSFETs have been 71

reported to have a much higher saturation drive current of 2.6– 72

2.9 mA/μm per unit diameter [10]. Hence, GAA transistor with 73

the same diameter should provide a larger drive current. A ver- 74

tical GAA transistor can act as an ideal select device that can 75

provide sufficient drive current for efficient switching of an 76

MTJ. In addition, it will provide a cell size of minimum 2-D 77

area. Considering these facts, this paper proposes a novel STT 78

MRAM cell with vertical GAA transistor as select device with 79

a buried source line (SL) and word line (WWL). The objective Q180

is to improve or retain the other performance specifications (ac- 81

cess time read and write margins) with the proposed 4F2 STT 82

MRAM cell. A detailed analysis is done taking into account 83

the design considerations and the constraints for an efficient 84

STT MRAM cell. The proposed cell is also compared with the 85

minimum-sized cell that can be realized with a planar select 86

device. 87

The paper is divided into seven sections, including the in- 88

troductory section. The architecture and functionality of the 89

proposed STT MRAM cell are presented in Section II. Section 90

III analyzes the recent advances in the field of PMA MTJs for 91

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Fig. 1. (a) Typical STT MRAM cell. (b) Front view of the proposed STTMRAM cell.

creating Verilog-A models based on experimental results. Sec-92

tion IV focuses on the design considerations (read, write mar-93

gins and switching probability) of an STT MRAM cell from the94

perspective of select devices. Section V describes the TCAD95

analysis of the proposed buried source GAA device followed96

by the load line analysis. Section VI analyzes and compares97

the HSPICE simulation results of the proposed STT MRAM98

cell with conventional STT MRAM cell. Finally, in Section99

VII, conclusions are drawn based on the analysis done in the100

previous sections.101

II. PROPOSED STT MRAM ARCHITECTURE102

STT MRAMs have three-dimensional (3-D) integration of103

MTJs with conventional CMOS technology. The memory cell104

of STT MRAMs has one MTJ and one NMOS select device,105

abbreviated as a 1T-1MTJ cell. The structure and properties of106

a typical 1T-1MTJ STT MRAM cell can be understood through107

Fig. 1(a). The bottom layer (pinned or fixed layer) of an MTJ108

has fixed magnetization due to its comparatively high magnetic109

coercivity. The top layer of the MTJ is known as free/recording110

layer whose magnetization can be switched by the spin torque111

acting on it. This spin torque is generated by the electric cur-112

rent, which is spin polarized by the pinned bottom layer. The113

directions of current for writing 1 and 0 are shown in Fig. 1(a).114

A current from BL to SL would make the magnetization ori-115

entation as P (to write a 0). Conversely, a current from SL to116

BL would make the magnetization states of two layers as AP (to117

write a 1). Besides this, for both the directions, the write currents118

need to be above a minimum threshold value for proper switch-119

ing of the MTJ. The front view of the proposed architecture120

is shown in Fig. 1(b) that consists of a PMA MTJ multilayer121

structure stacked above the vertical GAA cylindrical NMOS122

transistor. The bit line (BL) and buried SL are perpendicular to123

the plane of paper, while the WWL is in the plane of the paper.124

The proposed GAA structure allows the maximum possible 2-D125

array density for STT MRAMs.126

III. ANALYSIS OF PRACTICALLY FABRICATED PMA MTJS 127

PMA MTJs offer low critical currents and higher thermal sta- 128

bility and scalability for STT switching. Lee et al. [11] demon- Q2129

strated a PMA in Fe-rich CoFeB free layers due to the reduction 130

of demagnetizing field. The demagnetizing field decreases with 131

increase in perpendicular anisotropy and eventually leads to a 132

layer with perpendicular easy axis. The effective demagnetizing 133

(4πMeff ) field is expressed as 134

4πMeff = 4πMS − Hkp (1)

where Hkp is the perpendicular uniaxial anisotropy, Ms is the 135

magnetization of the layer and 4πMs is the demagnetizing field. 136

When Hkp exceeds 4πMs , the magnetic moment of CoFeB 137

has an easy axis perpendicular to the plane of MTJ. The low 138

switching current density is attributed to Hkp , which cancels 139

the effect of the out of plane demagnetizing field 4πMs . 140

Ikeda et al. [7], [12] demonstrated that the performance of 141

CoFeB/MgO/CoFeB based PMA MTJ with 40 nm diameter 142

shows excellent properties that includes a high stability factor 143

(E/KB T = 39) and low switching current (IC0 = 49μA). The 144

only limitation is large write voltage due to high resistance area 145

(RA) product, which leaves a scope of improvement. Moreover, 146

Gajek et al. experimentally analyzed spin torque switching of 147

PMA MTJ with a diameter of 20 nm. However, the results are 148

not as promising because of a low TMR (57%) [13]. Hence, Q3149

experimental results (shown in Table I) for 40 nm PMA MTJ 150

are used to develop a Verilog-A model that precisely replicates 151

the behavior and properties [14]. 152

IV. DESIGN CONSIDERATIONS 153

The select device in a typical memory system allows a mem- 154

ory cell to be accessible for read and write. This section describes 155

the design considerations of STT MRAMs from the perspective 156

of select devices. Fig. 2(a) and (b) represents the two states of 157

the STT MRAM cell before the write operation is performed. 158

Fig. 2(a) shows the equivalent circuit with polarity of BL and 159

SL trying to write a 0 into the cell (P write). Likewise, Fig. 2(b) 160

shows the equivalent circuit with the polarities of BL and SL 161

trying to write a 1 into the cell (AP write). Hence, an STT 162

MRAM cell can be viewed as an NMOS transistor with RP or 163

RAP connected to it as load. 164

The switching of MTJ depends on the direction of current and 165

also a minimum threshold current (IC0) required for switching 166

to occur. Hence, the primary consideration is that whether the 167

select device can provide sufficient drive current for MTJ switch- 168

ing in either direction. The driving current must be sufficiently 169

high to surmount the switching threshold with high switching 170

probability for proper operation of the STT MRAM cell. 171

A write error occurs when the strength of the write current is 172

not enough, and there is a probability that the desired data may 173

not be written into the cell [15]. Furthermore, a read disturb 174

is the unintentional write due to the read current flowing in a 175

direction; this lowers the switching energy barrier [15], [16]. 176

The write error rate (WER) and read disturb rate (RDR) for 177

STT-MRAM cell are determined from the switching probability. 178

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TABLE IPRACTICALLY FABRICATED MTJ PARAMETERS FOR CURRENT PULSEWIDTH OF 1 ns

Barrier/recording layer structure (nm) Diameter(nm)

TMR(%)

RA(Ω ·μm2)

Δ = E/kB T RP (kΩ) RA P (kΩ) IL H 0 (μA) IH L 0 (μA) VW (V) Reference

MgO(�0.85)/CoFeB(�1.7)/Ta 40 113 16 39 12.73 27.1 �72 �28 0.608 [7]

VW = JC 0 (RA) is the mean write voltage, where JC 0 is the switching current density and RA is the resistance area product. RA P = 27.1 kΩ and TMR = 113% are thezero-bias values for the PMA MTJ from [7].

Fig. 2. (a) Equivalent circuit of STT MRAM cell before MTJ switching withAP resistance as load. (b) Equivalent circuit of STT MRAM cell before MTJswitching with P resistance as load. (c) Top view of the vertical GAA NMOSdevice. (d) Front view of the vertical GAA NMOS device.

WER and RDR are expressed as179

RDR = PSW, WER = 1 − PSW (2)

where PSW is the probability of occurrence of switching below180

critical switching current (IC0) that is expressed as [15]181

PSW = 1 − exp{− tPW

τ0exp

[− E

kB T

(1 − I

IC0

)]}(3)

where tPW is the current pulsewidth, τ0 is the attempt time, IC0182

is the critical current required for switching, and E/kB T is the183

Boltzmann’s factor.184

The drain current (ID ) should be very small, when the cell185

has not been selected (WWL = 0) for reading or writing. The186

current through the cell with WWL = 0 should be small enough187

so that the switching probability is negligible, preferably below188

10−9 [15]. This means that the select device should offer very189

small off the current even though BL or SL is equal to VDD .190

Write margin is defined as the difference between the writing191

current and critical switching current of an MTJ [16]. The write192

current must be sufficiently high to obtain a cell with large193

write margins and small switching time. Different write margins194

are defined for P (WMP ) or AP (WMAP ) write into the cell. The195

write current for P writing IWP0 should have a direction from196

free layer (BL) to the pinned layer (SL) of an MTJ. Conversely,197

the write current for AP writing IWAP0 should have a direction198

from pinned layer (SL) to free layer (BL). WMP and WMAP199

are expressed as 200

WMP = (IWP0 − IHL0), WMAP = (IWAP0 − ILH0)(4)

where IHL0 and ILH0 are AP to P and P to AP critical switching 201

currents, respectively. 202

Read margin is defined in terms of sensing current (read cur- 203

rent) as the normalized difference between the critical switching 204

current and read current (sensing current) [16]. Analogous to 205

write margins, different read margins would be defined for P 206

(RMP ) and AP (RMAP ) reading mechanisms. The read current 207

during P reading has a direction from free layer (BL) to the 208

pinned layer (SL) of an MTJ. Likewise, the read current during 209

AP reading has a direction from pinned layer (SL) to free layer 210

(BL) of an MTJ. The RMAP and RMP are expressed as 211

RMP =IHL0 − IP0

IHL0, RMAP =

ILH0 − IAP0

ILH0(5)

where IP0 and IAP0 are the read currents during P and AP 212

reading, respectively. 213

Write access time (tP and tAP ) is defined as the time required 214

for switching the state of MTJ at the particular write current 215

and write current pulsewidth. The switching time also depends 216

on the switching threshold at that write current pulse duration 217

(tPW ) [14]. 218

V. VERTICAL GAA TRANSISTOR AS SELECT DEVICE 219

Conventionally, the overall area of the STT MRAM cell has 220

been dominated by the select device [1]. The proposed structure 221

allows us to accommodate the MTJ and select device within the 222

same area through 3-D stacking. In this section, the proposed 223

select device structure is thoroughly analyzed. The analysis has 224

been carried out for feature size F = 40 nm, which is same as 225

the diameter of the MTJ to keep the overall cell area 4F 2 . The 226

proposed structure with a buried source of diameter 2F is shown 227

in Fig. 2(c) and (d). The source is extended upward to a height 228

of 40 nm (F) so that the gate and source are not shorted together. 229

The diameter of the extension region is also F (40 nm). Drain 230

is at the top having a diameter and length of F (40 nm). Device 231

simulations are carried out for the proposed GAA structure on 232

Silvaco Atlas [17] (TCAD device simulator) for gate/channel 233

lengths (Lch ) of 40 (F), 80 (2F), and 120 nm (3F). The buried 234

oxide layer has not been shown for simplicity. 235

Source, drain, and source extension regions are heavily doped 236

with a uniform n-type doping concentration of 1 × 1020cm−3. 237

The channel is uniformly doped with p-type impurity concentra- 238

tion of 1 × 1016cm−3. The work function and gate oxide thick- 239

ness of the cylindrical gate are 4.61 eV and 2 nm, respectively. 240

The heavily doped extension region ensures a high current drive. 241

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TABLE IITCAD RESULTS OF GAA DEVICE FOR DIFFERENT GATE LENGTHS

L ch V t l in (V) DIBL (mV/V) Io n (μA) Io n /Io f f SS (mV/decade)

40 0.279 115 214.6 3.8×103 103.080 0.300 22.1 194 3.3×106 63.4120 0.307 13.6 175.5 1.5×107 60.3

TABLE IIITCAD RESULTS OF PLANAR NMOS DEVICE

W (nm) L ch (nm) V t l in (V) DIBL (mV/V) Io n (μA) Io n /Io f f SS (mV/decade)

40 80 0.250 354 85.8 18.29 768.340 120 0.275 280 72.8 142.8 294.280 120 0.275 310 145.6 142.7 294.2

A. TCAD Analysis of the Proposed Structure242

The ID−VDS and ID−VGS characteristics are analyzed us-243

ing 3-D TCAD device simulation of the proposed structure.244

Threshold voltage, drain-induced barrier lowering (DIBL), sub-245

threshold slope (SS), and Ion/Ioff are calculated for Lch of 40,246

80, and 120 nm. The method used for threshold voltage extrac-247

tion is “the linear extrapolation method in the linear region,”248

which is also commonly known as “maximum transconduc-249

tance method” [18], [19]. The magnitude of on current (Ion )250

and off current (Ioff ) are calculated at VGS = VDS = 1.6 V and251

VGS = 0, VDS = 1.6 V, respectively. DIBL is defined as the nor-252

malized difference in threshold voltages when VDS is changed253

from VDS lin and VDS sat254

DIBL =Vt lin − Vt sat

VDS sat − VDS lin(6)

where Vt lin and Vt sat are the threshold voltage in the linear255

(very low VDS ) and saturation regions, respectively. The values256

of VDS sat and VDS lin are 1.6 and 0.05 V, respectively. Vt sat257

is the value of VGS on ID−VGS curve at VDS = VDS sat re-258

quired to get the same value of current, which is obtained when259

VGS = Vt lin and VDS = VDS lin . The subthreshold slope (SS)260

is the change in VGS required to alter the subthreshold drain261

current by one decade (ten times). The corresponding results262

are shown in Table II. Although the device with 40 nm gate263

length has the largest current drive, but it severely suffers from264

short channel effects. The DIBL, off-current, and subthreshold265

slope parameters are comparatively large for the device with266

40 nm gate length. It is because of lower electrostatic gate con-267

trol at smaller gate length. Evidently, the device with 120 nm268

gate length demonstrates the best performance. In order to com-269

pare with the conventional STT MRAM cell, TCAD simula-270

tions are carried out for planar NMOS transistor also. The gate271

work function and oxide thickness of the planar NMOS are272

4.61 eV and 1.5 nm, respectively. However, the source, drain,273

and channel doping is same as that for GAA NMOS. The perfor-274

mance parameters calculated for planar transistor for different275

device dimensions are placed in Table III. The performance of276

the planar transistor is poor, especially for small gate length,277

Fig. 3. Comparison of the ID−VGS characteristics of GAA (40 nm nanowirediameter and Lch = 120 nm) and planar (W = 80 nm and Lch = 120 nm)NMOS.

Fig. 4. Comparison of |ID | − |VDS | characteristics with top as drain andbottom as drain operation for the GAA NMOS of Lch = 120 nm.

due to large short channel effects that are measured at a high 278

VDD of 1.6 V. Although, the short channel effects of the planar 279

NMOS can be reduced by decreasing the source and drain dop- 280

ing concentration, but that will reduce Ion also. A comparison 281

of ID−VGS characteristics is shown in Fig. 3, which confirms 282

that GAA NMOS has much lower off current than the planar 283

NMOS devices. 284

For SL = VDD and BL = 0, the vertical GAA transistor 285

would be operating with drain as bottom and top as source. 286

Therefore, the ID−VDS characteristics of the proposed structure 287

should also be analyzed with bottom [buried source in Fig. 2(d)] 288

as drain. However, Fig. 4 clearly shows a minute difference 289

between |ID | − |VDS | characteristics under the two modes of 290

operation. This difference can be safely neglected in the subse- 291

quent analysis and the device can be considered to be having 292

symmetric I–V characteristics. 293

B. DC Load Line Analysis 294

In this section, dc load line analysis is carried out to ascertain 295

that the vertical GAA transistor provides sufficient drive cur- 296

rent for proper operation of the proposed STT-MRAM cell [20]. 297

The ID−VDS characteristics obtained from TCAD simulation 298

for the proposed structure [see Fig. 2(d)] are used for the load 299

line analysis. Moreover, ID−VDS characteristics obtained from 300

TCAD simulations of planar NMOS with 120 nm gate/channel 301

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length are also included in the load line analysis. The mini-302

mum width (W = F = 40 nm) planar NMOS has a low Ion as303

compared to GAA (Tables II and III). Hence, the comparison304

would be more appropriate with a planar NMOS of width 80 nm305

(W = 2F = 80 nm), that has Ion comparable to the GAA de-306

vice. The value of VDS , as deduced from Fig. 2(a) and (b) is307

expressed as308

VDS = VDD − ID RMTJ (7)

where RMTJ is the resistance of MTJ. The RMTJ and TMRQ4

309

parameters vary considerably with bias voltage across the MTJ,310

when in AP state [14], [15]. The AP resistance (RAP ) and TMR311

of an MTJ are expressed as312

RAP(Vbias) = RP {1 + TMR(Vbias)}

TMR(Vbias) =TMR(0)

1 + (V 2bias/V 2

h )(8)

where Vbias is voltage across MTJ and Vh(= 0.5V) is the fitting313

parameter [14]. Hence, both RAP and TMR reduce with an in-314

crease in Vbias as compared to their zero-bias values according315

to (8) for Vbias > 0. RAP is considered as 20 kΩ (value of RAP316

at Vbias = 0.5) based on the safe assumption that Vbias ≥ 0.5 V317

at VGS > Vt and VDD ≥ 1 V. This assumption is perfectly safe,318

because the on resistance (for VGS greater than Vt) of NMOS319

is comparatively lower than the resistance of the MTJ. Thus,320

two load lines are drawn corresponding to the loads of RP =321

12.73 kΩ and RAP = 20 kΩ as shown in Fig. 5. The point of in-322

tersection between the load line and ID − VDS curves represents323

the operating point of the NMOS. The corresponding value of324

ID should be high enough for providing a drive current larger325

than the critical switching current of MTJ in either direction. The326

dotted lines show the critical MTJ switching currents ILH0 =327

72 μA and IHL0 = 28 μA in Fig. 5. As expected, the primary328

cause of concern is the comparatively high critical switching329

current required for P to AP switching (ILH0) [15]. The current330

ILH0 is higher, since the electrons reflected from the pinned331

layer switch the state of MTJ. The points of intersection (oper-332

ating points) of ID −VDS curve with the P and AP load lines333

are worth noting. The drain current ID at the operating point334

corresponding to load RP (RAP ) should be higher than the335

critical switching current ILH0 (IHL0). At VGS = 1.2, ID (for336

GAA) barely overcomes ILH0 (P load line), while at VGS equal337

to 1.4 and 1.6 V, ID (for GAA) exceeds ILH0 by 19 and 36 μA,338

respectively. Hence, the load line analysis shows that vertical339

GAA transistor can provide a sufficient drive current for switch-340

ing MTJ in either direction when VDD ≥ 1.4 V. Besides, it is341

evident from Fig. 5 that, to achieve a drive current close to342

GAA, the planar transistor of width 80 nm (2F) is required and343

the minimum width transistor (W = F = 40 nm) does not pro-344

vide sufficient current driving capability. The cell area for such345

a cell is exorbitantly higher, i.e., 10F 2 , the layout of which is346

shown in Fig. 6(a).347

C. BSIM CG Model Calibration348

BSIM CG is a part of the combined multigate (MG) model349

BSIM CMG coded in Verilog-A, which captures the behavior of350

all MG and GAA transistors [21], [22]. Appendix I depicts the 351

steps along with parameters to calibrate BSIM CG according to 352

TCAD results for the proposed GAA structure (40 nm diameter 353

and 120 nm gate length). The results of HSPICE simulation of 354

calibrated model are shown and compared with TCAD results 355

in Fig. 6(b) and (c). The ID − VDS and ID − VGS characteris- 356

tics show that the model closely replicates the TCAD results. 357

Henceforth, it can be used for further analysis of the proposed 358

STT MRAM cell. 359

VI. ANALYSIS OF PROPOSED STT MRAM CELL 360

The proposed STT MRAM cell and conventional cell with 361

planar transistor are analyzed using transient and dc simula- 362

tions on HSPICE using calibrated Verilog-A models. The lay- 363

out of the 10F2 (F = 40 nm) conventional cell is shown in 364

Fig. 6(c). For the circuit analysis of this 10F 2 planar cell, 365

BSIMSOI [23] Verilog-A model for planar SOI NMOS is cali- 366

brated from TCAD results using the same methodology given in 367

Appendix I for BSIM CG. The behavior of the two cells during 368

read is analyzed by performing dc analysis for P read scheme. 369

The bit stored in the STT MRAM cell (MTJ state) is read out 370

by applying WWL = VDD and a read voltage (VR ) between 371

BL and SL. The P read scheme employs BL = VR and SL = 0 372

during read operation. An optimum read voltage at BL is found 373

by simultaneous consideration of TMR degradation effect with 374

MTJ bias voltage and read current difference between P and AP 375

states of MTJ [24]. Since this read current has to be compared 376

with a reference current to read the data, the difference in cell 377

current between 0 and 1 stored cells should be high enough 378

to be discernible. In addition, TMR should be high during the 379

read operation, which decreases with an increase in read cur- 380

rent (or with an increase in MTJ bias voltage) expressed in (8). 381

The optimum read voltage is found to be 0.4 V [see Fig. 7(a)] 382

with a read current difference of 10 μA and TMR = 0.75 for 383

the GAA cell. Fig. 7 (a) also shows that, the read performance 384

of the two cells is similar. The read margins (RMP ) plotted in 385

Fig. 7 (b) further confirm the analogous read behavior, which 386

is expected because both the NMOS devices are in deep linear 387

region with very little difference currents during read operation. 388

The dynamic behavior of the proposed cells [see Fig. 8 and Ta- 389

ble IV] is verified by a series of write, hold, and read operation 390

cycle in terms of time at VDD of 1.6 V. The pulsewidth (tPW ) 391

of every cycle is 1 ns with rise and fall times of 0.1 ns. The 392

initial state of MTJ is considered as AP. The P read operation 393

is performed keeping WWL = 1.6 V with SL = 0 and BL = 394

0.4 V [24]. All entries in Table IV are measured at the midpoint 395

of each cycle or after the write operation is complete, in case of 396

write cycle. 397

The dynamic and leakage power of the two cells is obtained 398

from a transient analysis by keeping WWL equal to 1.6 and 0 V, 399

respectively. In addition, SL and BL are applied with a square 400

wave pulse of period 2 ns (50% duty cycle) with amplitude 401

of 1.6 V (VDD ) in both cases. During the analysis, SL is kept 402

as logical complement of BL such that when SL = 0, BL = 403

1.6 V, and vice versa. Again, the initial state of MTJ is consid- 404

ered as AP. Furthermore, write margins are also calculated for 405

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Fig. 5. Load-line analysis of vertical GAA (40 nm nanowire diameter and Lch = 120 nm) and planar NMOS (gate length of 120 nm) at different VGS (= VDD )corresponding to P and AP resistance as load. (a) For VGS = 1.6 V, (b) for VGS = 1.4 V, and (c) for VGS = 1.2. Red and black lines represent P and AP loadlines, respectively, in each of (a), (b), and (c). ILH0 and IHL0 are 72 and 28 μA, respectively.

Fig. 6. (a) Cell layout of conventional 10F 2 STT MRAM cell with planar select device. (b) Comparison of ID − VGS characteristics of calibrated BSIM CGwith TCAD results at VDS = 1.6 V. (c) Comparison of ID − VDS characteristics of calibrated BSIM-CG with TCAD results.

Fig. 7. (a) Variation of TMR and read current difference with read voltage (WWL = VDD = 1.6 V and SL = 0 V). (b) Variation of read margin (RMP )and write margins WMP with WWL = VDD . The analysis is done keeping BL = 0.4 V and SL = 0 V with the initial state of MTJ considered as AP.(c) Comparison of dynamic power dissipation (with WWL = 1.6 V) of the two cells in terms of VDD .

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TABLE IVTIMING ANALYSIS OF THE PROPOSED 4F2 GAA CELL AND 10F2 PLANAR CELL

Parameter Hold (initial state AP) Write 0 Hold Read 0 (P read) Hold Write 1 Hold Read 1 (P read) Hold

Bias voltages SL 0 0 0 0 0 1.6V 0 0 0BL 0 1.6 V 0 0.4 V 0 0 0 0.4 V 0

WWL 0 1.6 V 0 1.6 V 0 1.6V 0 1.6 V 0Planar Ic e l l (μA) 0 55.1 0 25.2 0 −92 0 15.7 0

RM T J (kΩ) 27.1 12.73 12.73 12.73 27.1 14.46 27.1 22.4 27.1TMR 1.13 – – – – 0.14 1.13 0.76 1.13

MTJ State AP (1) P (0) P (0) P(0) P(0) AP (1) AP (1) AP (1) AP (1)GAA Ic e l l (μA) 0 61.3 0 26.5 0 −95.8 0 16.3 0

RM T J (kΩ) 27.1 12.73 12.73 12.73 12.73 14.41 27.1 22.20 27.1TMR 1.13 – – – – 0.13 1.13 0.74 1.13

MTJ state AP (1) P (0) P (0) P(0) P(0) AP (1) AP (1) AP (1) AP (1)

Fig. 8. Timing diagram showing successful operation of the proposed 4F 2

STT MRAM cell at VDD = 1.6 V.

the proposed 4F 2 and conventional 10F 2 cell. The correspond-406

ing results are tabulated in Table V. Undoubtedly, the proposed407

cell demonstrates a better performance in terms of power dis-408

sipation and write margins. The leakage power dissipation for409

the proposed cell is four to five orders of magnitude lower than410

conventional cell (when the cell is not selected for writing). The411

dynamic power dissipation at WWL = 1.6 V (VDD ) is higher;412

although, here the point of consideration is that the dynamic413

power always has a tradeoff with the P and AP write margins414

(write currents). There is a larger tradeoff window between the415

write margin and dynamic power dissipation in the case of pro-416

posed cell with GAA device, as it can operate with VDD as low417

as 1.3 V (at tPW = 1 ns) by sacrificing the write margins. It is418

clearly observed in Fig. 7(b) that the planar cell cannot operate419

correctly at VDD = 1.3 V for tPW = 1 ns. Moreover, a com-420

parison of the dynamic power dissipation between the cells in421

terms of VDD in Fig. 7(c) shows that the proposed cell can be422

optimized for low-power operation also.423

VII. CONCLUSION424

The proposed STT MRAM cell offers better performance425

over the conventional STT MRAM cell from all perspectives.426

The biggest improvements are in terms of area and leakage427

power dissipation. The proposed cell occupies a much smaller428

area of 4F 2 with a 60% reduction in area from its conventional 429

counterpart, and still offers a much better performance. Hence, 430

to achieve high density STT MRAMs, the 4F 2 cell with vertical 431

GAA transistor is potentially better solution than 6–10 F2 cell 432

with planar transistor. The leakage power dissipation of the pro- 433

posed cell is comparatively much smaller, when the cell is not 434

selected for writing (WWL = 0V ). In addition, the proposed 435

cell shows excellent write margins and can be optimized for 436

low power operation. Despite the high write currents, the read 437

behavior is not compromised, as the proposed cell offers good 438

read stability and high read margins. Moreover, the read disturb 439

rate is lower than 10−7 up to read voltage VR = 0.4 V with 440

a read current difference of 10 μA between 0 (P) and 1 (AP) 441

stored cells. These advantages have been possible by the virtue 442

of vertical GAA NMOS. The proposed select device offers ex- 443

cellent gate control (Ioff = 12 pA) and high current drive along 444

with the attainment of maximum 2-D array density. These im- 445

provements should proliferate even more with subsequent down 446

scaling of the STT MRAM cell. 447

APPENDIX IBSIM CG MODEL CALIBRATION 448

The important parameters and model calibration methodol- 449

ogy for configuring BSIM CG for cylindrical GAA operation 450

are classified and discussed as follows: 451

A. Geometry and Material Parameters: The geometry 452

and material parameters of BSIM CMG are set for a vertical 453

GAA device operation, according to the parameters used for 454

TCAD simulation (see Table VI). 455

B. Threshold Voltage Calibration: The threshold voltage 456

of BSIM CG is expressed as 457

Vth = Vth0 + ΔVth,SCE + ΔVth,DIBL + DVTSHIFT (A1)

where Vth0 is the threshold voltage of the model based on sur- 458

face potential calculations. ΔVth,SCE is the threshold voltage 459

degradation due to short channel effects, ΔVth,DIBL is used 460

to model the effect of drain voltage on threshold voltage, and 461

DVTSHIFT is to handle any additional shift in Vth [21]. 462

The model equation for ΔVth,SCE in BSIM CG [21] is 463

ΔVth,SCE = − 0.5DVT0cosh {DVT1 (Leff /λ)} − 1

(Vbi − ψst)

(A2)

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TABLE VCOMPARISON BETWEEN PROPOSED CELL AND 10F2 PLANAR NMOS

Select Device WMP (μA) WMA P (μA) tp (ns) tA P (ns) Power (pW) WWL = 0 V Power (μW) WWL = 1.6 V

GAA 23.3 34.0 0.43 0.25 16.2 112.4Planar 17.6 29.0 0.52 0.32 1140 107.0

TABLE VIGEOMETRY AND MATERIAL PARAMETERS

BSIM Model Parameter Value Description[21]

GEOMOD 3 Cylindrical GAABULKMOD 0 SOI substrateASYMMMOD 1 Asymmetric deviceCOREMOD 0 Surface potential modelL 120 nm Gate lengthD 40 nm Gate diameterEOT 2 nm Gate oxide thicknessNGATE 0 Metal gateNSD 1 × 1020 cm–3 S/D doping concentrationPHIG 4.61 eV Gate work functionNBODY 1 × 1016 cm–3 Channel doping

where Vbi = (kB T/q) ln{NSD ∗ (nbody/n2

i )}

,464

ψst = 0.4 + (kB T/q) ln(nbody/ni), and λ =465 √(εsi · R · EOT/2εox) {1 + (R · εox/2εsi · EOT)}.466

Leff is the effective channel length. The model equation for467

ΔVth,DIBL in BSIM CG is expressed as [22]468

ΔVth,DIBL = − 0.5ETA0cosh (DSUB (Leff /λ)) − 1

VDS

+ DVTP0 ∗ VDSDVTP1 (A3)

TCAD simulation is carried to calculate ΔVth,SCE and469

ΔVth,DIBL and then (A1)–(A3) are used to set threshold voltage470

parameters accordingly (see Table VII).471

C. Mobility and Drain Current Parameters: Average low472

field mobility is calculated using TCAD simulations for the473

on state (VGS > Vth and VDS = 0.05) of the device. The low474

field mobility is found to be 650 cm2/(V·s). Further, U0MULT475

(multiplier to mobility) and IDS0MULT (multiplier to source–476

drain channel current) are set, which are dedicated to variability477

modeling and can be set by the user appropriately [21]. Mobility478

and drain current parameters are shown in Table VIII.479

D. Parasitic Capacitance, Subthreshold, and Leakage480

Current Parameters: AC analysis is done at a frequency of481

1 MHz with a low VDS (load line analysis in Section V shows482

that the NMOS will be invariably in the linear region of oper-483

ation). Hence, at |VDS | = 0.2 V, the average values of capac-484

itances are calculated. The average gate to source capacitance485

CGS and gate-to-drain capacitances CGD are found to be 0.087486

and 0.1 fF/μm, respectively. The parameters concerned with487

parasitic capacitance and subthreshold conduction are placed in488

Table IX.489

TABLE VIITHRESHOLD VOLTAGE PARAMETERS

BSIM Model Parameter VALUE Description [21]

DVT0 2.2 SCE coefficientDVT1 0.177 SCE exponent coefficientETA0 1 DIBL coefficientDSUB 0.80 DIBL exponent coefficientDVTP0 0 Coefficient for drain-induced V t h shiftDVTP1 0 Exponent coefficient for drain-induced V t h shiftDVTSHIFT 0 Additional V t h shift handle

TABLE VIIIMOBILITY AND DRAIN CURRENT PARAMETERS

BSIM Model Parameter Value Description [21]

U0 650 cm2/V·s Low field mobilityIDS0MULT 5 Multiplier to source–drain channel currentU0MULT 0.62 Multiplier to mobility

TABLE IXPARASITIC CAPACITANCE, SUBTHRESHOLD, AND LEAKAGE CURRENT

PARAMETERS

BSIM Model Parameter Value Description [21]

CGEOMOD 1 Parasitic capacitance model selectorCGEO1SW 1 Capacitance unit selectorCOVS 0.1 fF Constant ate to source overlap capacitanceCOVD 0.087 fF Constant gate to drain overlap capacitanceDVT1SS 1.0234 Subthreshold swing exponent coefficientGIDLMOD 1 GIDL/GISL model selectorAGISL 1.05 × 10–15 Preexponential coefficient for GISLAGIDL 1.05 × 10–15 Preexponential coefficient for GIDL

REFERENCES 490

[1] ERD. (2011). International technology road map for semiconductors [On- 491line]. Available: http://www.itrs.net 492

[2] T. Schloesser et al., “6F2 buried wordline DRAM cell for 40 nm and 493beyond,” in Proc. IEEE IEDM’08, San Francisco, CA, USA, pp. 1–4, 494Dec. 2008. Q5495

[3] H. Chung et al., “Novel 4F2 DRAM cell with vertical pillar transis- 496tor(VPT),” in Proc. IEEE ESSDRC, Helsinki, Finland, pp. 211–214, Sep. 4972011. 498

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Shivam Verma (S’13) received the M.Tech. degree 560in microelectronics from IIT BHU, Varanasi, India, 561in 2012. He is currently working toward the Ph.D. 562degree from the Indian Institute of Technology Roor- 563kee, Roorkee, India. 564

His current research interests include STT 565MRAMs and all spin logic. 566

567

Shalu Kaundal (S’14) received the M.Tech. degree 568in microelectronics and VLSI from the Indian Insti- 569tute of Technology Roorkee, Roorkee, India. 570

Her current research interests include designing 571and modeling of STT MRAMs. 572

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Brajesh Kumar Kaushik (SM’13) received the B.E. 574degree in electronics and communication engineer- 575ing from D.C.R. University of Science and Technol- 576ogy (formerly C. R. State College of Engineering), 577Murthal, India, in 1994, and the M.Tech. degree in 578engineering systems from Dayalbagh Educational In- 579stitute, Agra, India, in 1997, and the Ph.D. degree 580under AICTE-QIP scheme from the Indian Institute 581of Technology Roorkee, Roorkee, India, in 2007. 582

He was with Vinytics Peripherals Pvt. Ltd., Delhi, 583India, as a Research and Development Engineer in 584

microprocessor, microcontroller, and DSP processor-based systems. He joined 585the Department of Electronics and Communication Engineering, G. B. Pant 586Engineering College, Pauri Garhwal, India, as a Lecturer in July 1998, where 587he was an Assistant Professor from May 2005 to May 2006 and an Associate 588Professor from May 2006 to December 2009. He is currently an Associate 589Professor in the Department of Electronics and Communication Engineering, 590Indian Institute of Technology Roorkee, Roorkee, India. His current research 591interests include in the area of high-speed interconnects, low-power VLSI de- 592sign, carbon-nanotube-based designs, organic thin film transistor design and 593modeling, and spintronics-based devices and circuits. 594

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QUERIES596

Q1. Author: Please check the acronym of “word line.” Is this OK as is or should be WL.597

Q2. Author: Please check the edited sentence “PMA MTJs offer . . . switching.” for intended meaning.598

Q3. Author: Please provide the full form of the acronyms BSIM CG and TMR.599

Q4. Author: The variable “j” has been set as “R MTJ.” Please check.600

Q5. Author: Please provide all the names of authors in Refs. [2]–[5], [7], [8], [10], [12]–[14], [16], [21], and [24].601

Q6. Author: Please verify Ref. [18] as set.602

Q7. Author: Please provide the city of the publisher in Ref. [22].603

Q8. Author: Please provide the month information in Ref. [24].604