1

TMS570LS Architecture Overview: Memory Map, Clocking, Exceptions

2

Architecture Overview

Flex

Ray

Flex

Ray

Flex

Ray

DC

AN

sD

CA

Ns

Mib

SPI/

Mib

SPIP

Mib

SPI

Mib

SPI

/ / Mib

SPIP

Mib

SPIP

Mib

AD

Cs

Mib

AD

Cs

Mib

AD

Cs

NH

ET

NH

ET

NH

ET

GIOGIO

GIO

EC

PE

CP

EC

P

Peripheral BusPeripheral Bus

RTIRTI SYSSYS VIMVIM

Bus MatrixBus Matrix

CRCCRC A2VA2V

RAMRAM

Peripheral Library

LIN

/SC

ILI

N/S

CI

LIN

/SC

I

POM

POM

EMIFEMIF

PROGRAM

FLASH

HTUHTU

FTUFTU

DMADMADMMDMMDAPDAP

RTPRTP

RTP

Cortex-R4(F)Cortex-R4(F)

32-bit ARMCortex-R4(F)32-bit ARM

Cortex-R4(F)

Bus Matrix masters

Peripherals

Arbitration logic

Memory related logic

3

Memory Map

0x00000000

0x00 1FF FFF

0x080000000x080 27FFF

CRC0xFE0000000xFEFFFFFF0xFF0000000xFFF7FFFF

SYSTEM Modules0xFFF800000xFFFFFFFF

0x0 04000000x00 4FFFFF

0x0 84000000x084 27FFF

EMIF (256MB)0x60000000

0x6FF FFFFF

CS1CS0

CS2CS3

0x600000000x603FFFFF

POM (4MB)

TMS570LS20216

0x20000000

0x20 1FF FFF

0x2 04000000x20 4FFFFF

Flash (2MB)

Flash - ECC

RAM (160kB)

RAM - ECC

Flash (2MB) (mirrored image)

Flash – ECC (mirrored image)

Peripherals

4

Clock Sources and Domains

/1..64 X92..184 /1..8 /1..32

Low Power Oscillator

/1..2 X1..15 /1..8

OSCIN

/1..16

/1..16

0

1

4

5

6

GCLK (to CPU)

HCLK (to System Bus)

VCLK (to Peripheral Bus)

VCLK2 (to NHET/HTU)

01456

VCLK

VCLKA1 (to DCANx)

01456

VCLK

VCLKA2 (to FlexRay/FTU)

01456

VCLK

/1,2,4, or 8

RTI1CLK (to RTI)

Clock Source #

5

Frequency Modulated PLL (FMzPLL)

REFCLKDIV PLLDIV

PLLMUL

ODPLL PLLCTL2

PLLCTL1

PLLCLK, fPLLOSCIN, fOSCIN

Where

NR – Reference Clock Divider ratio (REFCLKDIV)NF – PLL feedback divider ratio (PLLMUL), 92 .. 184ODPLL – PLL output divider ratio (ODPLL), 1 .. 8R – PLL Divider Ratio (PLLDIV), 1 .. 32

Configure FMzPLL using PLLCTL1(0x70) and PLLCTL2 (0x74) registers of System frame1 (0xFFFF_FF00)

The output frequency of the FMzPLL is given by:

6

FMzPLL Calculator

• Can be used to determine PLLCTL1 and 2 register values based on the entered PLL and FM option settings• Can be used to determine the PLL and FM settings based on the entered PLLCTL1 and 2 register values

7

Secondary Non-Modulating PLL (FPLL)

Where

NR – Reference Clock Divider ratio (REFCLKDIV), /1 .. 2NF – PLL feedback divider ratio (PLLMUL), X1 .. 15R – PLL Divider Ratio (PLLDIV), /1 .. 8

Configure FPLL using FPLLCTL(0x00) register of System frame2 (0xFFFF_E100)

The output frequency of the FPLL is given by:

/NR

/ 1 .. 2

OSCIN

PLL

x NF

x 1 .. 15

/R

/ 1 .. 8

PLLCLK

8

FPLL Calculator

• Can be used to determine FPLLCTL register values based on the entered PLL settings• Can be used to determine the PLL settings based on the entered FPLLCTL register value

9

Low Power Modes

• Doze Mode– Highest power consumption among low power modes– Fastest from wake up event to full-speed operation– Main oscillator remains active and clocks RTI module– Wake up from RTI or external sources (CAN, LIN, SCI, GIO, reset)

• Snooze Mode– Power consumption near minimum– Allows fast wake up using internal reference oscillator– Only internal reference oscillator remains active and clocks RTI module– Wake up from RTI or external sources (CAN, LIN, SCI, GIO, reset)

• Sleep Mode– Lowest power consumption among low power modes– Slowest from wake up event to full-speed operation– All clock sources and clock domains are disabled– Wake up only from external sources (CAN, LIN, SCI, GIO, reset)

10

Low Power Modes Summary

High freq. oscillator

Internal low freq. clock

RTI clock

GCLK HCLK VCLKP VCLK2 VCLKA1 VCLKA2 PLL Flash banks

Flash pumps

on on on off off off off off off off off off

High freq. oscillator

Internal low freq. clock

RTI clock

GCLK HCLK VCLKP VCLK2 VCLKA1 VCLKA2 PLL Flash banks

Flash pumps

off on on off off off off off off off off off

LPO Internal low freq. clock

RTI clock

GCLK HCLK VCLKP VCLK2 VCLKA1 VCLKA2 PLL Flash banks

Flash pumps

off off off off off off off off off off off off

Doze Mode:

Snooze Mode:

Sleep Mode:

11

Reset Sources

• Power-on Reset– Asserted by external voltage supervisor, or by internal voltage monitor

• Oscillator fail– Asserted by internal clock monitor when enabled by software

• CPU Reset– Asserted by CPU self-test controller after LBIST operation completes

• Software Reset– Asserted by software writing to the exception control register

• External Reset– Asserted by external circuitry driving the warm reset (nRST) signal LOW

• Debug Reset– Asserted by ICEPICK JTAG module

12

TMS570LS: Flash Tools

13

nowECC

<return_value> nowECC [options] -i <input_file> [-o <output_file>]<return_value> nowECC [options] -i <input_file> [-o <output_file>]

• Generates ECC data for program flash

• Command-line executable

• Return value = 0 indicates no error during operation– Separate error codes to differentiate each type of error

• Input_file is only required parameter– Can be Extended Tektronix, Intel Hex, Motorola-S, COFF or ELF format

• Output_file specifies the name of the output file to be generated– If no name is specified, ECC is appended to input file specified

14

Options for Flash Programming

• On-board programming using nowFlash/Code Composer Studio v4.x– Requires JTAG connection– Emulators Supported:

• Blackhawk BHUSB560M• Spectrum Digital XDS510PP, XDS510PP+, XDS510USB,

XDS560RUSB• Signum JTAGjet• Texas Instruments SPI525, XDS100v2, XDS560

• On-board programming via customer boot-loader code– Must use Texas Instruments released API routines– Multiple communication interfaces can be used– Necessary to validate program and erase routines

• Off-board programming– Single-device or Concurrent programming– Supports high degree of automation

15

nowFlash

• PC-based software tool: GUI + command line executable• Communicates with microcontroller via JTAG• Can be used to program, erase, read, or verify flash memory• Also supports execution of custom code out of RAM (from command line only)

16

Flash Application Programming Interface

• Distributed only as an object library file

• Supports flash operations out of on-chip RAM

• Supports operations at max specified device clock frequency

• Library routines for– Blank check– Compaction– Erase– Program zeros– Program data– Calculate checksum– Verify

• Routines also manage ECC

17

TMS570LS: Real-Time Interrupt Module (RTI)

18

RTI: Block Diagram

19

RTI: Main Features

• Two independent counter blocks for generating different time bases

• Each block consists of– One 32-bit prescale counter– One 2-bit free-running counter– Two capture registers for capturing the prescale and free-running counters

• External event can be used for incrementing free-running counter 0– Can be used for synchronizing with FlexRay bus communication cycle

• Four compare interrupts– Each can use either of the two available free-running counters– Automatic update of compare values to minimize CPU intervention– Option to generate DMA request as well as the compare interrupt

• Two counter-overflow interrupts– Generated when a free-running counter overflows and goes to zero

• Four compare interrupts

20

TMS570LS: Vectored Interrupt Manager (VIM)

21

VIM: Block Diagram

PRI

ORITY

DECODER

INT0

INT63

FIQ

IRQPhantom Interrupt

Address ISR0

Address ISR1

Address ISR61

Address ISR62

VIM RAM

VBUS

WRAPPER

VBUS

REGISTERS

VBUSP

IRQVECTADDR [31:0]

IRQACK } Vector InterruptInterfacefrom CPU

P

CHANNEL

MAPPING

22

VIM: Main Features

• VIM Hardware– Dedicated Vector Interrupt interface to ARM CPU– Hardware relocation of the IRQ vector address– Hardware assistance for prioritizing and controlling interrupt sources

• VIM Functions– 64 interrupt requests – Map interrupt request to interrupt channel via programming.– Provides programmable priority through interrupt request mapping– Prioritizes the interrupt channels to the CPU– Provides the CPU with the address of the interrupt service routine (ISR)

• VIM Modes– Legacy ARM7 Mode (FIQ/IRQ)– Vectored interrupt (FIQ/IRQ)– Hardware vectored interrupt (IRQ only)

23

VIM: Interrupt Servicing ModesLegacy ARM7 Interrupts

• FIQ/IRQ request

• Fetch from 0x18/0x1C

• Branch to ISR handler

• Load Interrupt offset

• Decision which ISR to execute (FIQIVEC / IRQIVEC)

• Branch to ISR

Vectored Interrupts

• FIQ/IRQ request

• Fetch from 0x18/0x1C

• Branch to ISR (LDR PC, [PC, #-0x1B0]),address for highest active interrupt request derived from IRQVECREG/FIQVECREG

Hardware Vectored Interrupts

• IRQ request (only)

• CPU reads IRQ vectoraddress instead of 0x18

• VIM provides address of highest pending request directly to CPU vector interface

• CPU branches directly to ISR

• Note - processor state afterIRQ entry: T flag = VECTOR[0],LSB of vector address determines if first instructionof interrupt handler is ARM or Thumb instruction

24

VIM: Channel Mapping - Default State

priority

high

low

• Note - NMI (Non-Maskable Interrupt): Channel 0 and Channel 1 are called NMI Channels and are non-maskable.• Interrupt requests can be mapped to desired channel using CHANMAPx registers.

25

VIM: Input Channel Management

wake-up logic is asynchronous, but reset is synchronous

26

VIM: Wake-up Generation

Wake-up interrupt generation

detail of the interrupt request input

(to global clock module)

27

VIM: Vector RAM

• not initialized after reset• used for vectored interrupts• 64 x32bit organization• 32/16/8bit access• VIM read has always priority

over peripheral bus interface• RAM protected by parity

RAMVIM RAM address space

28

TMS570LS: Direct Memory Access (DMA)

29

DMA: Main Features

• 32 channels with individual enable

• 64 DMA requests– Software and hardware

DMA requests (event synchronization)

• Support 8, 16, 32 or 64 bit transaction

• Multiple addressing modes for source/destination

– fixed, incrementing, indexed

• Auto Initiation

• Channel chaining capability

• 1 FIFO (First In First Out)

• One AHB master port (64 bit wide) to interface with the bus matrix

• One slave port to interface with VBUS for register interface

• Memory Protection for the address range DMA can access

30

DMA: Transfer Definitions

Element

RES

WES

11: Double-word, 64bit 10: Word, 32bit 01: Half-word, 16bit 00: Byte, 8bit

RES, Read Element Size WES, Write Element Size

Element 1Element 2…..

Element N

…..

FrameFrame 1

Frame 2

…..

Frame M

…..

Block

N = Element Transfer Count (ETCOUNT) M = Frame Transfer Count (FTCOUNT)

N·M = Size of Block

31

DMA: Addressing Modes

• Constant– Source/Destination address do not change– e.g. SCI transmit and/or receive register (constant address)

• Post Increment– Source/Destination address is post incremented by the element size

(Byte, Half-word, Word, Double-word)– e.g. RAM to RAM transfer

• Indexed– Source/Destination address is post incremented as defined in the

element index offset register and the frame index offset register– Indexed addressing always works with Byte size

32

DMA: How to Start a Transfer?

• Software requests– By setting bit x in SWCHENAS [31:0] register transfer (channel x) will

be triggered.

• Hardware requests– An active DMA request signal will trigger a DMA transaction.– Up to 64 DMAREQ lines can be handled.– Since DMA controller is clocked by HCLK, the duration of all DMA

requests signals must be at least HCLK long.

• Triggered by other control packet– When a control packet finishes the programmed number of transfers

it can trigger another channel to initiate its transfers.

33

DMA: Frame or Block Trigger (TType)

34

DMA: Request Mapping/Control Packets

35

TMSx70 Software

6 5 5 4 4 3 3 2 2 1 1 0

Element transfer counter

3

DMA transfer

Setup of control packet x:• Source Address = start of source buffer• Destination Address = start of destination buffer

• Element Transfer Count = 6 • Frame Transfer Count = 1

• Read Element Size = Word (32 bit), also 8, 16 or 64 bit is possible • Write Element Size = Word (32 bit), also 8, 16 or 64 bit is possible• Addressing Mode Read = post-increment read address• Addressing Mode Write = post-increment write address

Setup control registers:• DMA_EN: Enable DMA controller after setup of control packet x

• SWCHENAS: Writing a one to the associated channel x to trigger a SW request

1

1

2

DMA: RAM to RAM transfer example

2 2 2 2 2

CPU Interrupt (optional)

Control packet x

RAM Buffer (32 bit)(destination)

RAM Buffer (32 bit)(source)

Frame Index Pointer

Element Index Pointer

Channel Configuration

Transfer Count

Destination Address

Source Address

2

Interrupt Service Routine of control packet x:• Process transferred data with CPU

3

36

DMA: Channel Interrupts

• Each channel can be configured to generate interrupts on several transfer conditions:

– FTC (Frame Transfer Complete) interrupt

– LFS (Last Frame Transfer Started) interrupt

– HBC (First Half of Block Complete) interrupt

– BTC (Block Transfer Complete) interrupt

– BER (Bus Error) interrupt

37

DMA: Memory Protection

0xFFFFFFFF

0xFFF78000

0x08003FFF

0x08000000

0x00000000

Region 3

Region 3

Region 1

Region 0

System + Peripherals

RAM

No access restriction

Access restriction apply

0xFFFFFFFF

0xFFF78000

0x08003FFF

0x08000000

0x00000000

Region 3

Region 2

Region 1

Region 0

System + Peripherals

RAM

No access restriction

Access restriction apply

38

TMS570LS: General-Purpose I/O (GPIO)

39

GPIO: Block Diagram

External pin

GIODSETx

GIODOUTx

GIODINx

GIOPDRx

GIODCLRx

High-level-interrupt

handling

Low-level-interrupt

handlingGIOLVLSET

High priority

Low priorityInterrupt enable

Interrupt disable

GIOENASETGIOFLGGIOPOL

Rising edge

Falling edge

To VIM

To VIM

VBU

S

GIOPULDIS

GIOPSL

GIODIRx

GIOENACLR GIOLVLCLR

GIOINTDET

OPEN DRAIN LOGIC GATES

40

GPIO: Main Features

• Configurable as Input or Output via Direction Register

• Read/Write Registers

• Set Registers

• Clear Registers

• Separate Input Register

• Pull-up/Pull-down Configurability

• Open Drain Capability

• Interrupt Capability– Configurable Priority– Configurable Polarity: rising edge, falling edge, or both edges

41

TMS570LS: New High-End Timer (NHET)

42

• User-programmable Timing Co-Processor

• Provides high level and complex timing functions with low CPU overhead

• 128 word instruction RAM with Parity protection

• Dedicated DMA functionality (HTU) to transfer data from NHET to Data Ram w/o CPU

• Conditional program execution based on pin conditions and compares

• 32 input/output (I/O) channels (pins) for complex or classical timing functions such as capture, compare, PWM, GPIO

• Suppression filters eliminate undesired input frequencies

• Multiple 25-bit virtual counters for timers, event counters, and angle counters

• High Resolution I/Os and coarse resolutions implemented by sub loops for multiple resolution capability

High End Timer (HET)

32 I/O Channels

Hostinterface

Address/Data Bus

TimerRAM

ExecutionUnit

Input/Output

Unit

Compare

32 bit ALU

Register A, B, T

Instruction Register

Address Register

Interrupt Control

Operation Control

Program RAM Control RAM Data RAM

CPU wait control

Shadow registers Prescaler

Global & prescale control register

I/O ControlRegister

Synchronizers

32 High Resolution Channels

43

NHET: Application ExamplesPulse Width Modulation

• Single / multi channel PWMs

• PWM with synchronous / asynchronous duty cycle update

• PWM with synchronous period update

• Phase shift PWM's using RADM64 instruction

Frequency and Pulse Measurements

• Pulse width and period measurement (using PCNT)

• Period measurement using PCNT in HR mode, HRshare feature and 64 bit read access with “auto read/clear” bit set

Other Features

• Frequency Modulated Output

• Pulse width count (using PWCNT)

• Time stamp (using WCAP)

• Event counter (using ECNT)

• Pulse accumulator example (using ECNT )

• Multi-resolution scheme

44

NHET: Timer RAM

• Timer RAM uses 4 RAM banks

• Each bank supports Dual Port Access (one RAM address may be written while another address is read)

• Third access possibility to RAM by CPU, TU or DMA

• RAM words are 96-bits wide (3*32bit, program, control, data)

• Write access by word (32bit) only

• Read access is allowed by 8-bit, 16-bit and 32-bit

45

HETDSETHET[x]

HETDIR

HETDCLR

HETDOUT

HR control logic

HR flags, HR register

HR up / down counter (5 bits)

Timer data inHR prescale driverHigh resolution clock

HR compare data

Timer data out

Timer data in

HETDIN

Loop Resolution Clock

NHET: I/O Structure

HETPDR

HETPULDIS

HETPSL

HET Pull Control Logic

46

NHET: Instruction Set OverviewMnemonic Instruction Name Cycles

ACMP Angle Compare 1ACNT Angle Count 2

ADCNST Add Constant 2ADM32 Add Move 32 1 or 2APCNT Angle Period Count 1 or 2

BR Branch 1CNT Count 1 or 2

DADM64 Data Add Move 64 2DJNZ Decrement and Jump if Non-Zero 1ECMP Equality Compare 1ECNT Event Count 1MCMP Magnitude Compare 1MOV32 Move 32 1 or 2MOV64 Move 64 1PCNT Period/Pulse Count 1

PWCNT Pulse Width Count 1RADM64 Register Add Move 64 1

SCMP Sequence Compare 1SCNT Step Count 3SHFT Shift 1WCAP Software Capture Word 1

WCAPE Software Capture Word and Event Count 1

47

NHET: Command Line Assembler

• Invoking the NHET assembler (hetp.exe): hetp [options] input file

• Options:– -c32 produces an output file containing assembler directives for the TMS570

CodeGen Tools– -hc32 produces a C file and a header file. (used together with the -nx option)– -nx specifies the x-th HET module on the device (used together with -hc32

option)– -l (lowercase L) produces a listing file with the same name as the input file

with a .lst extension.– -x produces a cross-reference table and appends it to the end of listing file.

• Example: hetp -hc32 -n0 pwm.het• Input: pwm.het contains the assembly source of the HET program• Output: pwm.c provides a C array, which contains the HET

program opcodepwm.h provides a C structure, which allows a simple

access to the NHET fields from other C code

48

NHET: Time Base

• VCLK2 is used as base clock for the High End Timer

• A 6-bit prescaler dividing the system clock by a user-defined high-resolution (HR) prescale divide rate (hr) stored in the 6-bit HR prescale factor code (with a linear increment of codes).

• A 3-bit prescaler dividing the HR clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution prescale factor code (with a power of 2 increment of codes).

High Resolution (HR) prescaler (6 bits)

Loop Resolution (LR) prescaler (3 bits)

VCLK2 Loop Resolution clock

High Resolution clock

49

TMS570LS: High-End Timer Transfer Unit (HTU)

50

HTU: Block Diagram

51

HTU: Main Features

• CPU and DMA independent

• Master Port to access directly system memory

• HTU master accesses protected by dedicated Memory protection Unit

• One Slave port to interface with VBUS for register interface

• Maximum of 8 double control packets supporting dual buffer configuration

• Control packet information is stored in RAM protected by parity

• Event synchronization (HET transfer requests)

• Support 32 or 64 bits transaction

• Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64bit)

• Each type of interrupt can be routed to either two different host CPUs

• One shot, circular and auto switch buffer transfer modes

• Request lost detection

52

LAB2: Using NHET as GIO

53

Overview

• In this project we will:– Create our first HALCoGen Project– Generate and Import code into Code Composer Studio– Write code to turn on the LED on HET pin 1– Build and Deploy our code to the microcontroller

54

Setting up a New HALCoGen Project

• Launch HALCoGen– Start > Programs > Texas Instruments > HALCoGen

• File > New > Project• Family:

– TMDX570• Device:

– TMDX570LS20USB• Name: Exercise• Location: “C:\myWorkspace”

55

The Interface

56

Configuring the Peripherals

• Select the peripherals that are required for this project.– In this lab we need only enable the GIO driver, uncheck all other drivers

• No further changes should be made, the source code can now be generated.– To do this go to File > Generate Code– Following, the folders on the right will populate with our new files

57

HALCoGen Help• Information about the files

and functions that HALCoGen creates can be found in the HALCoGen ‘Help’ menu

• Help can be launched from the main title bar under Help -> Help Topics

58

Setting up Code Composer Studio 4 (CCS4)

• Launch CCS4– Start > Programs > Texas Instruments > Code Composer Studio v4 >

Code Composer Studio v4• When it launches, CCS will ask you to select a workspace, we will chose

“C:\myWorkspace”• Once it loads, go to File > New > CCS Project

59

Setting up our Project

• Our project name needs to match the name of our HALCoGen Project, Exercise

• Then Click “next”• On the next page, make

sure that your projecttype is set to ARM andDebug and Release areboth checked

• Then Click “next”

60

Setting up our Project (cont.)

• We are not using any referenced projects so click “next” again

61

Setting up the Project (cont.)

• Lastly, set the Device Variant to “Cortex R” and TMS570LS20216SPGE

• Click “Finish”

62

Getting Started

• On the left hand side in the “C/C++ Projects” exploer, open “sys_main.c”• When ever you generate code in HALCoGen, the program overwrites user

code, except specific sections marked by “USER CODE BEGIN (x)” and “USER CODE END”– For code placement we will be referring to the number within the User

Code block

/* USER CODE BEGIN (0) *//* USER CODE END */

63

Writing the Code

• Inside User Code 1, copy the code below.

• Then in User Code 3, copy the code below.

/* USER CODE BEGIN (1) */#include "het.h"/* USER CODE END */

/* USER CODE BEGIN (3) *//* Set HET port pins to output */gioSetDirection(hetPORT, 0xFFFFFFFF);

/* Set HET port pin 1 high */gioSetBit(hetPORT, 1, 1);

/* Infinite loop */while(1);

/* USER CODE END */

64

Notifications

• Lastly we must insert a function that would be called if interrupts were enabled. Without these, the code will fail to build

/* USER CODE BEGIN (4) *//* GIO Notification function not used, but required by compiler */void gioNotification(int bit){

return;}/* USER CODE END */

65

Compiling the Project

• The code is now complete and we are ready to build our project.– Go to Project > Build Active Project

• Now that we have our .out file, we need to program the microcontrollers Flash memory.

66

Creating a Target Configuration

• Before we begin, we must make a new target configuration, this tells CCS4 what device this project is designed for.– Target > New Target Configuration

• A new window will appear, we will make our file name “TMS570.ccsxml”• Click Finish

67

Creating a Target Configuration…

• A new tab will appear with a list of emulators and devices.– Connection: Texas Instruments XDS100v2 USB Emulator– In the text box labeled “Type Filter Text”, type “TMS570”.

• This will narrow the search down to just TMS570 devices, select TMS570LS20216SPGE

– Click “Save” on the right

68

Flash Programming Configuration• It is possible to make the flash programming process much faster

by only the necessary erasing and programming the necessary regions of flash memory.– To do so go to Tools > On-Chip Flash

• If ‘On-Chip Flash’ option is not available, select Target > Launch TI Debugger. Then go to Tools > On-Chip Flash

– In the window that appears on the right, under Erase Options, check “Necessary Sectors Only (for Program Load)”

69

Programming the Flash

• We are now ready to program the flash.– Go to Target > Debug Active Project– A new window should appear as it programs the flash memory.

• This may take a few moments.

70

Testing our Program

• Click the green arrow on the debug tab to run our program

– Alternatively the program can be run without the debugger connected by

• Clicking the red square on the debug tab to terminate the debugger’s connection

• Hit the reset button on the board and the NHET[1] LED should illuminate.

• Congratulations! You have completed the lab.

71

TMS570LS: Multi-Buffered Serial Peripheral Interface (MibSPI)

72

SPI / MibSPI Features

• The SPI / MibSPI has the following attributes:– 16-bit shift register

Receive buffer register– 8-bit baud clock generator

Serial Clock (SPICLK) I/O pin– Up to 4 Slave in, Master out (SPISIMO) I/O pins for faster data transfers – Up to 4 Slave out, Master in (SPISOMI) I/O pins for faster data transfers– SPI Enable (SPIENA) I/O pin (4 or 5-pin mode only)– Slave Chip Select (SPISCS[7:0]) I/O pin (4 or 5-pin mode only)

• The SPI / MibSPI allows software to program the following options:– SPISOMI / SPISIMO pin direction configuration– SPICLK pin source (external/internal)– MibSPI pins as functional or digital I/O pins

73

• For each Buffer, following features can be selected from 4 different combinations of Formats using the control fields in the buffer:

– SPICLK frequency ([VBUSPCLK]/2 through /256)

– Character length (2 to 16 bits)

– Phase (delay/no delay), Polarity (high or low)

– Enable/Disable Parity for transmit & receive

– Enable/Disable timers for ChipSelect Hold & Setup timers

– Direction of shifting, MSBit first or LSBit first

– Configurable Parallel modes to use multiple SIMO/SOMI pins

SPI / MibSPI Features

74

SPI / MibSPI Features

• In Multibuffer Mode (uses the Multibuffer RAM (up to 128 Buffers)), in addition to the above, many other features are configurable:

– Number of buffers for each peripheral (or data source/destination) or group (up to 8 transfer groupings)

– Number of DMA controlled buffers & number of DMA request channels (up to 8 for each of transmit & receive)

– Triggers for each groups, trigger types, trigger sources for individual groups (up to 14 external trigger sources & 1 internal trigger source)

– Number of DMA transfers for each buffer (up to 65536 for up to 8 buffers)

– Un-interrupted DMA buffer transfer (NOBREAK buffer)

75

SPI / MibSPI Additional Features

• Multibuffer RAM Fault Detection (MibSPI only): – Parity circuit to detect memory faults

• SPI / MibSPI Multiple Chip Select (Master only):– The SPI / MibSPI supports multi chip select (multiCS) modes

• SPI / MibSPI Internal Loop-Back Test Mode (Master only):– To test the SPI / MibSPI transmit path and receive path including the buffers and the parity

generator• SPI / MibSPI Transmission continuous self-test (Master/Slave):

– During data transfer SPI / MibSPI compares its own internal transmit data with its transmit data on the bus

• SPI / MibSPI Variable Chip Select Setup and Hold Timing (Master only): – To support slow slave devices a counter can be configured to delay the data transmission after

the chip select is activated• MibSPI Lock transmission (Multibuffer mode Master only):

– To enable consecutive transfer without being interrupted by another higher priority group transfer

• SPI /MibSPI Detection of Slave de-synchronization (Master only)• SPI / MibSPI ENA Signal Time-out (Master only):

– To avoid stalling the MibSPI by a non-responsive slave device• SPI/MibSPI Data Length Error:

– To detect any mismatch in length of received/ transmitted data with the programmed character length

• Modulo Count Parallel Mode (Optional mode):– Special parallel mode to accommodate some specific slave devices

76

Standard SPI Mode - Block DiagramVBUS Write VBUS Read

TX SHIFT REGISTER

TX BUF

RX BUF

nSPISCS[7:0]

nSPIENA

SPICLK

SPISIMO SPISOMI Pre

scal

e

Clo

ck P

olar

ity

Clo

ck P

hase

CLKMOD

ModeGeneration

Logic

DMA REQ EN

RX_DMA_REQ

RXOVRN

RXEMPTY

SPI BUF

SPI CLOCK GENERATION LOGIC

VBUS Clock

INT_LVL

RXOVR INT ENA

RX INT ENA

TX INT ENA

Kernel FSM

DMA REQ EN

TXFULL

RX SHIFT REGISTER

16

16 16

SPIDAT0 SPIDAT1

16

CHARLEN

TX_DMA_REQ

16

16

INT_REQ0

INT_REQ1

77

MibSPI Multibuffer Mode - Block DiagramVBUS

TX SHIFT REGISTER

Multibuffer Control

nSPISCS[7:0]

nSPIENA

SPICLK

SPISIMO SPISOMI Pre

scal

e

Clo

ck P

olar

ity

Clo

ck P

hase

CLKMOD

ModeGeneration

Logic

DMAREQ[15:0]

Ctrl Field

SPI CLOCK GENERATION LOGICVBUS Clock

Kernel FSM

RX SHIFT REGISTER CHARLEN

16

Sequencer FSM

SPIBUF Status

1616 16

16

16

InterruptGenerator

DMA CONTROL LOGIC

Trigger CONTROL LOGIC

CrtlField

TXBuffer

StatField

RXBuffer

Multibuffer RAM

16

Tick Counter

TRG_SRC[13:0]

2

INTREQ[1:0]

SPI Kernel

Multibuffer Logic

78

MASTER SLAVE

(MASTER = 1 ; CLKMOD = 1) (MASTER = 0 ; CLKMOD = 0)

SPIDAT1 SPIDAT0

MSB LSB MSB LSB

WRITE TO SPIDAT1

SOMI

SIMO

SOMI

SIMO

SPICLK SPICLK

nSCS[7:0] nSCS

nENABLE nENABLE

WRITE TO SPIDAT0

SPICLK

SIMO

SOMI

WRITE TO SPIDAT0 (SLAVE)

nENABLE

WRITE TO SPIDAT1 (MASTER)

nSCS

Transfer Mode - Five Pin Option:Hardware Handshake

79

SPI / MibSPI Data Formats

• Data word length must be programmed in master mode and in slave mode

• For words with fewer than 16 bits Data must be right-justified when it is written to the MibSPI for transmission irrespective of its character length or word length

• The figure below shows how a 12-bit word (0xEC9) needs to be written to the transmit buffer in order to be transmitted correctly:

• The Received data is always stored right justified irrespective of the character length or direction of Shifting and is padded with leading ‘0’s when character length is less than 16.

• SPI / MibSPI supports automatic right-alignment of receive data independent from shift direction and data word length

• 2 consecutive accesses to the same slave are possible

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

01 1 1 1 1 0 0 1 0 0 1x x x x

80

CLOCK POLARITY = 0, CLOCK PHASE = 0

WRITE SPIDAT

SPICLK

SPISIMO

SPISOMI

SAMPLE INRECEPTION

MSB D6 D5 D4 D3 D2 D1

D0

LSB

D6 D5 D4 D3 D2 D1D7

CLOCK PHASE = 0 (SPICLK WITHOUT DELAY)

- DATA IS OUTPUT ON THE RISING EDGE OF SPICLK- INPUT DATA IS LATCHED ON THE FALLING EDGE OF SPICLK- A WRITE TO THE SPIDAT REGISTER STARTS SPICLK

1 2 3 4 5 6 7 8

Clock Options

81

Multibuffer RAM

• Size depends on the implementation– Number of buffers: 0..127

• Divided into different groups with individual configuration

• For each group a trigger event can be chosen

– One shot or continuous option– Trigger event conditions can be

set up (e.g. rising edge)

• Up to 15 trigger sources are available– External events, tick counter,

buffer array management

• Interrupt generation – Upon finishing transfer group– Suspend (provide new data or

consume received data)

Buffer 0Buffer 1

Buffer 17

Buffer 18

Buffer 31

Buffer 32

Buffer 63

Transfer group0 :18 buffersPSTART0 = 0

Transfer group1 :14 buffersPSTART1 = 18

Next (3rd) transfer group

OR (if last possible transfer group is used)

LPEND = 32

Buffers 32 .. 63 are unused or undefined

Example for a 32 buffers dual transfer group (64buffer RAM size)

82

SPI / MibSPI Parallel Mode

• In order to achieve higher data flow, the parallel mode of the SPI / MibSPI enables the module to send data over more than one data line (Parallel 2, or 4).

• Figure of Parallel Mode with Shift register MSB first:

• Notes: – When parallel mode is used, the data length must be set as 16 bits– If parity is enabled one additional SPICLK will trigger the parity bit transfer

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SO

MI7

SO

MI6

SO

MI5

SO

MI4

SO

MI3

SO

MI2

SO

MI1

SO

MI0

SIM

O7

SIM

O6

SIM

O5

SIM

O4

SIM

O3

SIM

O2

SIM

O1

SIM

O0

MULTIPLEXER

DEMULTIPLEXER

PSIMO[7:0]

SOMI[7:0]

Parallel Mode

Shift Register as inSPI / MibSPI

83

tC2TDELAY = (C2TDELAY / VCLK) + 2

tC2EDELAY = (C2EDELAY / SPICLK)

tT2CDELAY = (T2CDELAY / VCLK) + 1

Timing Setup – Delay Register (SPIDELAY)

SCSx

ENAx

SPICLK

VBUSPCLK

SOMI

tT2EDELAY = (T2EDELAY / SPICLK)

CSHOLD = 1 (held active/ dotted line) CSHOLD = 0 (set CS high after transmission)

WDELAY

DATA

84

TMS570LS: Controller Area Network (DCAN)

85

DCAN Architecture• Full CAN according to protocol

version 2.0 part A, B• CAN Core

– handles all CAN protocol functions

• Message Handler– controls data transfer

between CAN Core, Message Interface registers and RAM

– handles acceptance filtering and interrupts

• Message RAM– 64 mailboxes (DCAN 1&2)– 32 mailboxes (DCAN 3)

• Registers and Message Object access (IFx)

– Status and configuration registers for module setup and indirect Message Object access through interface registers (IFx)

• Module Interface– 32-bit interface to VBUS

clock domain

DCAN

MessageRAM Interface

Module Interface

CAN Core

Message Handler

Registers & MO access

CTRL VBUSP

CAN_TX

MessageRAM

(8, 16 or 32 bit)INT requests DMA requests

VCLKA

CAN_CLK

CAN_RXVCLK

Test Modes only

86

DCAN Features Overview

• Full CAN according to protocol version 2.0 part A, B• Standard and Extended Identifiers• Programmable Bit Timing, Bit rates up to 1 MBit/s• Up to 64 Message Objects (MO) / Mailboxes• Identifier Masks for each Message Object• Programmable FIFO mode for Message Objects• Dual clock feature• Possible automatic retransmission of a frame in case of lost arbitration or

error• Bus diagnostic: Bus off, Bus error passive, Bus error warning, Bus stuck

dominant• Frame error report: CRC, Stuff, Form, Bit and Acknowledgement errors• Programmable loop-back modes for self-test operation• Suspend modes for debug support• Parity check mechanism for all RAM modules

87

TMS570LS: FlexRay Controller

88

FlexRay Block Diagram

• FTU: FlexRay Transfer Unit

• IBF: Input Buffer

• OBF: Output Buffer

• INT: Interrupt Control

• TBF A/B: Transient Buffer RAM

• PRT A/B: FlexRay Channel Protocol Controller

• GTU: Global Time Unit

• SUC: System Universal Control

• FSP: Frame and Symbol Processing

• NEM: Network Management

89

FlexRay Key Features

• Open Bus System

• Support of redundant transmission channels

• Data rate of 10 Mbit/sec per channel

• Support of a fault tolerant synchronized global time base

• Static and dynamic data transmission (scalable)– Deterministic data transmission– Arbitration free transmission

• Fault tolerant and time triggered services implemented in hardware

• Support of optical and electrical physical layers

90

FlexRay on TMS570LS (1/2)

• Bosch FlexRay Core (E-Ray)

• Conform to FlexRay Protocol Specification V2.1

• Data rates of up to 10 Mbit/s on each of the 2 channels

• 8 Kbyte of Message RAM for storage of– 128 message buffers with max. 48 byte data section or – 30 message buffers with 254 byte data section– Different payload lengths possible

• Parity Protection of Message RAM

• Message Handler controls– Message RAM access arbitration– Acceptance Filtering– Maintaining the transmission schedule– Providing status information

91

• Each message buffer can be configured as – Receive buffer – Transmit buffer

• Each message buffer can be assigned to – Static segment of the Communication Cycle– Dynamic segment of the Communication Cycle– Part of a receive FIFO

• Direct CPU access to message buffers via input and output buffers

• Dedicated Transfer Unit (DMA-like) for automatic data transfer to and from message buffers without CPU interaction

• Filtering for frame ID, channel ID and cycle counter

• Maskable module interrupts

• Network Management supported

FlexRay on TMS570LS (2/2)

92

FlexRay Communication Structure

staticsegment

dynamicsegment

symbolwindow NIT static

segmentdynamicsegment

symbolwindow NIT

payloadhea der trailer CID payloadhea

der trailer CID

the payload length can vary

slot 1 slot 2 slot 3 … slot m-1 slot m

m + 1

m + 2

m + 3

dynamicslot m+4

m + 5

m + 6

dynamicslot 7

.

.

.

m + x

Cycle [n] Cycle [n+1] Cycle […]

93

FlexRay Communication Cycle

Static Segment Dynamic Segment

94

FlexRay Message Frame Format

95

FTU Data Transfer Scheme

FTUTCR

TBAC

ontro

l

VBUS

Data RAM

Array ofStruct { Header, Payload }

CPUMessage RAM

FlexRay

Header Partition

Data (Payload)Partition

FlexRay Core

Prot

ocol

Con

trol

ler

Stat

e M

achi

ne

Flex

Ray

Bus

Trigger Event Trigger

Interrupt

96

FlexRay Transfer Unit Key Features

• Data Transfer without CPU interaction– From FlexRay Message RAM to Data RAM (Read) – From Data RAM to FlexRay Message RAM (Write)

• Transfer Types– data and header section– header section only– data section only

• Transfer Configuration RAM (with Parity)– Configures the transfer sequence– Parity protection

• Triggers to Start a Transfer– CPU driven (single transfer sequence)– Event driven (single or continuous transfer sequence)

97

FlexRay Transfer Unit Key Features…

• Different Transfer Conditions– If the status flags (header section) of the respective

message buffer has been updated – If the data section of the respective message buffer has

been updated– Always

• Maskable interrupt generation when Message Buffer transfer is finished

• Memory Protection Unit– One memory section (start- and end address) can be

defined– No memory section is setup after reset

98

TMS570LS: Local Interconnect Network (LIN)

99

Typical LIN Applications

Rear Door Lock, window

Mirror

Mirror

BCM Gateway

Passenger´s Door Lock, window

Driver´s Door Lock, window

Fan

Damper

Door Control

Light

Light

Levelizer

Levelizer

CompressorCAN

Climate Control

Wipers

Dashboard

Rear Wiper

Sun Roof

Driver´s Seat

Steering wheel

Rear Door Lock, window

100

LIN Communication Concept

• Single Master concept with max. 16 nodes in one LIN cluster• LIN supports baud rates from 1 to 20KHz• Single wire low cost bus system often used as a sub network to comfort CAN.

101

LIN Message Frame

MASTER

• Synch break signalling beginning of a new message

• Synch field: 0x55• ID Field:

ID 0x00 to 0x3F (0 to 63)• Diagnostics:

ID 0x3C (master request) ID 0x3D (slave response)

• User Defined: ID 0x3E

SLAVE

• Response with 0 to 8 data fields

• Checksum field – classic CS LIN1.3

– over data bits only – enhanced CS LIN2.0

– over data bits and the protected identifier

SDEL1..4 Tbit

SYNCH BREAK13 + (0..7) Tbit

SYNCH FIELD10 Tbit

ID FIELD10 Tbit

STAR

T BI

T

STO

P BI

T

01010101

STA

RT

BIT

STO

P B

IT

STAR

T BI

T

STO

P BI

T

STAR

T BI

T

STO

P BI

T

Data FIELD10 Tbit

STA

RT

BIT

STO

P BI

T

Checksum FIELD10 Tbit

P0 P1

102

• Compatible with LIN 1.3 or 2.0• LIN 2.0 Master Compliant • HW LIN protocol handler

– Multi-buffered receive and transmit units

– Automatic checksum generation and validation

– ID masks for message filtering

– DMA capability• Synch break detection• Slave automatic synchronization• Optional baud rate update• Synchronization validation• Automatic bit monitoring• Automatic error detection• SCI (UART) mode

– Max 3.125Mbps with 100MHz VCLK

BLIN

SCI

8 RECEIVE BUFFERS

8 TRANSMIT BUFFERS

INTERFACE

DMA CONTROL

READ DATA BUS

WRITE DATA BUS

LINRX

LINTX

SCICLK

ADDRESS BUS

MASK FILTERS

SYNCHRONIZER

COUNTER

TIMEOUT CONTROL

COMPARE

FSM

TXRX ERROR DETECTOR

(TED)

CHECKSUM CALCULATOR

BIT MONITOR

ID PARITY CHECKER

LIN Key Features

103

Write Data to Write Data to TX BufferTX Buffer

LIN Module

Process Error Process Error InterruptInterrupt

Application Software

Sync Break is generatedSync Break is generatedSync Field is generatedSync Field is generatedIdentifier is transmittedIdentifier is transmitted

TX BufferTX Buffer

Transmit DataTransmit Data

TXRDY Flag is set after TXRDY Flag is set after complete message is complete message is transmittedtransmitted

Error Flag is setError Flag is set

orProcess other taskProcess other task

Write identifier to Write identifier to ID registerID register

• Application software handles the preparation of transmitted data and starts the transmission with writing the ID.

LIN: Master Transmission

Right identifier receivedRight identifier received

Yes

104

Write identifierWrite identifierto ID registerto ID register

LIN Module

Process Error Process Error InterruptInterrupt

Application Software

Process other tasksProcess other tasks

Sync Break is generatedSync Break is generatedSync Field is generatedSync Field is generatedIdentifier is transmittedIdentifier is transmitted

Received DataReceived Data

RRX BufferX Buffer

RXRDY Flag is set after RXRDY Flag is set after complete message is receivedcomplete message is received

Error Flag is setError Flag is set

or

Right identifier receivedRight identifier received

Yes

LIN: Master Reception

• Application software starts the transmission with writing the ID and handles the received data.

105

• Programmable Frame Format1 Start Bit1 to 8 Data Bits0 or 1 Address Bit0 or 1 Parity Bit1 or 2 Stop Bits

• Asynchronous Communications Format• 2 Multiprocessor Modes with Wake-up Capability

Idle-Line Mode; Address-Bit Mode• Programmable Baud RatE

– more than 16 700 000 different Baud Rates• Error Detection

– Parity, Overrun and Framing Error– Break Detect

• Noise Protection Capability• Double-buffered Receive and Transmit Function

TMS570 LIN – SCI Mode Features

106

LAB3: PC Communication Using SCI

107

Overview

• In this project we will:– Edit our existing HALCoGen project to setup the SCI module– Write code that prompts the user to enter a characters which are echoed

in the PC terminal

108

Enabling the SCI Module

• Reopen the HALCoGen project• Go back to the ‘Driver Enable’ tab.

– For this lab we will be using the SCI and GIO modules

• Click the ‘VIM Channel 0-31’ tab

109

Enabling the SCI Interrupt

• On this page you will see two subgroups– The left group lists all available interrupts– The right group allows you to enable these

interrupts• Match the displayed setting below to enable the

LIN1/SCI1 High interrupt

110

Configuring the SCI Peripheral

• On the top bar of the ribbon click “SCI1”• Now that we have enabled the interrupt, we need to tell the device when to

interrupt.– For this lab we will select the “RX INT”, so that an interrupt is generated

whenever the SCI receives data

111

Regenerate our Code

• All of the setting for this project are complete.• We will need to regenerate our code to apply the new settings.

– File > Generate Code• As long as you typed all of your custom code inside the USER CODE

blocks, then you will not lose any code.• Once this is complete reopen your project in Code Composer Studio

112

Communicating with the SCI Module

• In Code Composer Studio, insert the following into User Code 1 in the C/C++ perspective

• This will include the SCI header file as well as creating a variable that can later be used for storing received SCI characters

/* USER CODE BEGIN (1) */#include "het.h"#include "sci.h"

/* Stores user character */static unsigned char command;

/* USER CODE END */

113

Initializing the Modules• Insert the following into User Code 3

/* USER CODE BEGIN (3) *//* Enable IRQ */_enable_IRQ();

/* Initialize SCI module */sciInit();

/* Set HET port pins to output */gioSetDirection(hetPORT, 0xFFFFFFFF);

/* Set HET port pin 1 high */gioSetBit(hetPORT, 1, 1);

/* Send user prompt */sciSend(sciREG1, 21, (unsigned char *)"Please press a key!\r\n");

/* Await user character */sciReceive(sciREG1, 1, (unsigned char *)&command);

/* Infinite loop */while(1);

/* USER CODE END */

114

Handling SCI Interrupts

• Lastly, insert this block into User Code 4 before the gioNotification

• Each interrupt on the microcontroller will respond by calling a notification function in which you tell the TMS570 how to respond.

/* USER CODE BEGIN (4) *//* Notification called upon reception of character */void sciNotification(sciBASE_t *sci, unsigned flags){

/* Echo received character */sciSend(sci, 1,(unsigned char *)&command);

/* Await further character */sciReceive(sci, 1,(unsigned char *)&command);

}

115

Building and Deploying the Code

• The coding segment for this project is now complete, go ahead and build your project and then program it to the flash.

116

Testing your code

• Upon Completion open the TMS570 console or preferred terminal program.• Ensure the following properties

– Baud rate: 9600– Data bits: 8– No parity, 2 Stop bits

• Click the ‘Terminate All’ box in CCS then hit reset on the board.• You should now see the ‘Please press a key!’ prompt in the console window.• When a character is typed, the microcontroller will ‘echo’ the character back to

the terminal program.

117

TMS570LS: External Memory Interface (EMIF)

118

EMIF: Block Diagram

119

EMIF: Main Features

• Interfaces to asynchronous memories

• 4 addressable chip selects of up to 16MB each

• 16-bit data bus width

• Programmable cycle timings

• Select strobe mode

• Extended wait mode

• Data bus parking

• Allows overlay of up to 4MB of on-chip flash to external memory via Parameter Overlay Module (POM)

120

TMS570LS: Multi-Buffered ADC (MibADC)

121

MibADC Block Diagram

CONTROL AND STATUSSEQUENCER

ADIN31..........

ADIN0

VrefLO VrefHI VSSA VCCA

Chnsel Swtsel(Test / Cal)

ConversionGroup

Selection

ADEVT

Interruptrequests

PERIPHERAL BUS (VBUS)16

Internal Event 1

Internal Event 7

Event Logic EVENT

GROUP1EVENTFIFO

GROUP1FIFO

GROUP2FIFO

Result Formatting- Channel ID mask- 8/10/12 bit mode mask

DMArequests

3

DMA requests

32:1

Mul

tiple

xer

GIO Control

5

.

.

InterruptThreshold+ counters

EVENT,GROUP1GROUP2

3

Calibration &Error

Correction

Ctrl Chn

ADC RAM

w/ Parity

GROUP2

w/ Autoinitializationw/ RAM Test

Self-test& Calibration

Sample Cap

Discharge

10bit / 12bitAnalog – Digital Converter

(successive approximation)

CAP Dis. FIFO empty

ADCL K

6 Magnitude Threshold Interrupt Sources

5

Prescaler

5VCLK

122

• Configurable 10-bit or 12-bit resolution• Up to 24 channels (8 Shared Channels)• Sequential multi-channel conversion in ascending order• Two conversion modes

– Single conversion– Continuous conversion

• Three conversion groups w/ programmable sample and acquisition times– Two software- or event-triggered conversion groups: Group1 and Group2– One event-triggered-only conversion group: Event Group

• Three size adjustable memory regions– Channel identifier stored with conversion result

• Up to 8 event trigger options• Enhanced interrupt capability w/ programmable interrupt threshold counter• DMA request generation capability• Power-down mode• Embedded self-test & calibration• External event pin (ADEVT) can be programmed as general-purpose I/O

MibADC Main Features

123

MibADC Operation Modes

• Conversion mode– normal active mode for converting the selected external

input voltage

• Sample Capacitor Discharge mode– active mode that grounds the ADC sampling capacitor

• Calibration mode– special active mode for calibration using internal

reference voltages

• Self-test mode– active mode for failure-detection using internal reference

voltages

• Power-down mode– inactive mode in which the ADC internal clock is stopped

124

MibADC Conversion Groups

Event group select (ADEVSEL)

Event group FIFO

12 value8 value

read

ADEVBUFFER

ADG1SEL ADG2SEL

Input Channel Select Registers

Group 1 FIFO

9 value 3 value

Group 2 FIFO

read

ADG1BUFFER

read

ADG2BUFFER

31 0 31 0 31 0

11 1 1

126

MibADC Interrupts

• Conversion Group End Interrupt – All channels that are assigned to a particular group are converted

• Conversion Group Buffers Threshold Interrupt– Number of conversion results exceed threshold register value

• Conversion Group Buffers Overrun Interrupt – Number of ADC conversions exceed the number of buffers allocated

for that conversion group

• Magnitude Threshold Interrupt– Magnitude comparison of conversion result on up to six channels;

alternately, comparison can be made between the conversion result from another channel.

• Parity Error Interrupt– Parity error following a read from the ADC RAM

127

TMS570LS Support Structure

128

TMS570 Support Structure

• TMS570 Web Page: www.ti.com/TMS570– Data Sheets– Technical Reference Manual– Application Notes– Software & Tools Downloads and Updates– Order Evaluation and Development Kits

• TMS570 Forum: http://e2e.ti.com/support/microcontrollers/tms570/default.aspx

– News and Announcements – Useful Links– Ask Technical Questions– Search for Technical Content

• TMS570 WIKI: • http://processors.wiki.ti.com/index.php/TMS570

– How to guides– Intro Videos– General Information

129

TMS570 Microcontroller Forum Overview

• Forum Guidelines:– At least one person will monitor the forum at all times (work days)– All questions posted in the forum will have a response in 24hrs or less

Forum Flow:TMS570 Forum

TI E2E forum for questions about TMS570 devices

Answer Known ?

YES

Post Answer Within 24hrs

NO

Post ‘Question Received’ Confirmation Within

24hrs

Forward Question to World Wide

Team

World Wide Apps Team:-United States

- Europe-India

Post Answer

130

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