ARCHITECTURE OF DIGITAL SIGNAL PROCESSORTMS320C54X

On completion of this presentation we will be able to Understand the architectural details of the DSP TMS320C54XUnderstand the bus structure of the DSP TMS320C54XUnderstand the memory organization of DSP TMS320C54XUnderstand the pipelining mechanism in the DSP TMS320C54XKnow the different on-chip peripherals available in the DSP TMS320C54XOBJECTIVES

IMPORTANT FEATURES/SPECIFICATIONS16-bit fixed point processorMore DSP application specific in its hardware and instruction set when comparing with its predecessors 2X,2XX and 5X processorsEight memory buses40-bit ALUTwo 40-bit accumulators A&B40-bit barrel shifter with 0-31 left shift and 0-15 right shift capabilities17x17 multiplier

40-bit adderTwo auxiliary ALUs ARAU0 & ARAU1Eight auxiliary registers AR0 AR716- bit circular buffer register BK16- bit program counter(PC) and 7-bit program counter extension register(XPC)16-bit stack pointerThree status registers ST0,ST1 and PMST

Three 16-bit registers(BRC,RSA and REA) for block repetition operationTwo 16- bit registers for interrupt handling (IMR &IFR)Two general purpose I/O pins BIO and XFWait state generator SWWR16-bit hardware timerClock generator Synchronous, TDM and buffered Serial I/O ports

FUNCTIONAL BLOCK DIAGRAM OF TMS320C54XX

BUS STRUCTURE

The C54X bus structure is built around eight16-bit buses namely PB,CB,DB,EB,PAB,CAB,DAB,EABPB carries the program code, immediate operands and data operands stored in program memoryCB and DB carries the operands that are read from the data memoryEB carries the operands that are to be written into the data memory

Four address buses PAB,CAB,DAB,EAB are used to carry the addresses that are needed for buses PB,CB,DB,EB respectively.Three addresses one for program memory and two for data memory can be generated in parallel in one cycleOn-chip bi-directional bus is used to access the on-chip peripherals. This bus is connected to DB and EB through bus exchanger in the CPU interface

INTERNAL MEMORY ORGANIZATIONThe internal (on-chip) memory of C54X DSP consists of 4K x 16-bit ROM , 64K x 16-bit DARAM and 64K x 16-bit SARAM .The external memory consists of 16K x 16-bit (3-wait state) SARAM and 256K x 16-bit 12-wait state Flash memory.ROM/SARAM allows one access per cycle. Whereas the DARAM allows two accesses per cycle. External memory access speed is determined by number of wait states.

INTERNAL MEMORY ORGANIZATIONThe memory of 54X DSP is organized into three individually selectable memory spaces; program memory space, data memory space and I/O space.These memory spaces can be mapped into one or more of the followinga)ROM b)DARAM c) SARAMAll memories can be either on-chip or off-chip

ON-CHIP ROMThe on-chip ROM is usually a part of the program memoryIf the device possess the smaller amount of ROM it contains the boot loader programIf the device possess the larger amount of ROM a part of the ROM may be mapped into both program and data memory.

ON-CHIP DARAMIt is a dual access RAM can be accessed twice in single machine cycleThis memory is mostly mapped into data space with intention to store the data values.Some times using overlay (OVLY) mode a part of this memory can be mapped into the program memoryON-CHIP SARAMEach block of this memory is accessible once per machine cycle for either read or write.This memory also mostly mapped into the data spaceBoth DARAM and SARAM can also be mapped into program space to store the program codeThe on-chip RAM is organized in pages and each page contains 128 word locations

PROGRAM AND DATA MEMORY MAPS

MEMORY MAPPED REGISTERSThe 54xx processors possess two sets of memory mapped registers namely CPU registers and peripheral registers.These registers are mapped on page0 of data memory from the address 00h to 5fhThe memory mapped access provides a convenient way to transfer information between accumulator and other registers.The CPU MMRs are used in operations that are being taken place within the CPU. Whereas the peripheral MMRs are for control the operations of peripheral devices like serial codec, DMA, wait state generator etc.

CPU REGISTERS

NAMEADDRESSIMR(INTERRUPT MASK REG)00IFR(INTERRUPT FLAG REG)01ST0(STATUS REG0)06ST1(STATUS REG1)07AL(ACCUMULATOR A LW)08AH(ACCUMULATOR A HW)09AG(ACCUMULATOR A GUARD)0ABL (ACCUMULATOR B LW)0BBH (ACCUMULATOR B HW)0CBG (ACCUMULATOR B GUARD)0DTREG(TEMPERARY REG)0ETRN(TRANSITION REG)0F

AR0 (AUXILIARY REG0)10AR1 (AUXILIARY REG1)11AR2 (AUXILIARY REG2)12AR3 (AUXILIARY REG3)13AR4 (AUXILIARY REG4)14AR5 (AUXILIARY REG5)15AR6 (AUXILIARY REG6)16AR7 (AUXILIARY REG7)17SP (STACK POINTER)18BK (CIRCULAR BUFFER SIZE REG)19BRC (BLOCK REPETITION COUNTER)1ARSA (REPETITION START ADDRESS REG)1BREA (REPETITION END ADDRESS REG)1CPMST(PROCESSOR MODE STATUS REG)1DXPC(PROGRAM COUNTER EXTENSION REG)1E

INTERRUPT REGISTERSIMR,IFRInterrupt mask register(IMR) specifies the interrupts that are to be masked at required timeInterrupt flag register(IFR) indicates the current status of the interrupts

STATUS REGISTER(ST0)It is a memory mapped register indicates the status of various conditions after different operationsARP:Auxiliary register pointer used to specify the ARx in indirect data memory addressing when CPU is working in compatibility mode(CMPT=1). DP: is data page pointer specifies the 9 higher order bits of 16-bit address in direct addressing mode

TC: the test control flag affected by different instructions such as CMPS, BIT. Some conditional branching instructions use TC status to take the branching decisionC:carry flag is set to 1if carry generated after addition and reset to 0 if borrow results after subtractionOVA: overflow flag for accumulator A. sets when overflow occurs and the destination is accumulator AOVB: overflow flag for accumulator B. sets when overflow occurs and the destination is accumulator B

STATUS REGISTER ST1This register indicates the status of modes and instructions executed by the processorBRAF: Block repeat active flag activate/deactivates the block repetition operation when BRAF=1 block repetition is active.CPL: Compiler mode. Used to select the DP or SP in direct addressing. When CPL=0, DP is used and SP is used when CPL=1

XF: certain DSPs provide a general purpose output that can be used to drive an external logic. The XF bit is used to control the state of the output.HM: Hold mode. Determines whether the processor continues its internal execution or not when it is in active hold mode.(HM=1;stops all internal execution)INTM: Interrupt mode. Globally masks or enables all interrupts.(INTM=1masks all maskable interrupts)OVM: Overflow mode. Determines what is to be loaded into the destination accumulator when overflow occurs. When OVM=1 overflowing data are saturated to the largest positive (007FFFFFFFH} or negative number(FF80000000H) that can be represented in 32-bit 2s complement notation.

SXM: Sign extension mode. Enables or suppress the sign extension. SXM=1 sign extension is enabled; SXM=0 sign extension is disabledC16: Selects the dual 16-bit mode or double precision arithmetic mode for ALU operation. When C16=1 ALU is allowed to perform two 16-bit operations in same cycle. For example DADD instruction adds two 16-bit numbers in single cycle if C16 is set to 1. if C16=0 ALU is allowed to perform the normal double precision mode.FRCT: Fractional mode. Multiplier result is shifted left by one bit when this bit is set. This mode is utilized to remove extra sign bit that appears when two Q-15 numbers are multiplied.

CMPT: Compatibility mode for the ARP in indirect addressing. When CMPT=0 CPU works in the standard mode. In this mode the ARP is not updated and it should be set to 0. when CMPT=1 the CPU works in compatibility mode and ARP field is updated in the indirect addressing mode.ASM: Accumulator shift mode. In certain arithmetic operations an arithmetic shift on operand is required before performing the operation. This shift is provided by the 5-bit ASM field which specifies the shift value from 16 to +15 range.

PROCESSOR MODE STATUS REGISTER (PMST)This register contains the control information and memory setup status

IPTR: Interrupt vector pointer. 9-bit field points to the interrupt vector table. By default the interrupt vector table is located in the address rangeFF80H TO FFFFH in the program memory space. However after reset this table can be dynamically changed to any 128 word page in the program space. The upper 9 bits of the beginning address of the interrupt vector table is hold by IPTR field. The 7 lower bits of the beginning address are always 0.

MP/MC: Microprocessor/Micro computer mode, enables or disables the ON-CHIP ROM for program memory space. When MP/MC=0 the on-chip ROM is visible in the program space. When MP/MC=1 the on-chip ROM is not visible in the program spaceOVLY: RAM overlay mode. Enables or disables the ON-CHIP DARAM to be mapped into program memory. When OVLY=0 the on-chip RAM is visible only in the data memory space. When OVLY=1 the on-chip RAM is visible in the data memory space as well as the program space

AVIS: Address visibility mode. Enables or disables the internal program address to be visible at address pins. When AVIS=1 the addresses of all internal bus accesses during on-chip access are presented on the external bus.DROM: Data ROM mode. Enables or disables the ON-CHIP ROM to be mapped into data memory space. When DROM=0 the on-chip ROM is visible in the data space.CLKOFF: CLOCKOUT OFF. When this bit is set, the output of CLOCKOUT is disabled and remains at high level. The clock output is usually disabled to minimize the RF noise that it generates.

SMUL: Saturation on multiplication. This bit enables or disables the intermediate saturation(after multiplication in) in MAC and MAS operations in the case of overflow. For this function is to be fully functional the OVM bit must also be set. When SMUL=0 intermediate saturation is enabled and it is disabled when SMUL=1.SST: Saturation on store. This bit enables or disables the automatic saturation, that can be performed when writing the contents of an accumulator to memory. When SST=0, saturation to memory writes is disabled and it is enabled when SST=1.

ACCUMULATORSTwo 40-bit accumulators; Accumulator A and Accumulator B

Each accumulator splits into three partsAccumulator low word(15-0 bits)Accumulator high word(31-16 bits) and Accumulator guard bits(39-32 bits)Guard bits are used as head margin for computationsAccumulators are configured as destination registers for either MAC unit or ALU

TEMPORARY REGISTER (T)Can be used to hold the one of the multiplicands Holds the shift count in instructions with shift operationsTREG(3-0) are used to hold the dynamic bit address for the BITT instructionHolds the branch metrics used in ACS operation of veterbi decoding

TRANSITION REGISTER (TRN)16-bit memory mapped registerHolds the transition decision in connection with viterbi algorithm CMPS instruction updates TRN in Compare select and store (CSS) operation

AUXILIARY REGISTERS (AR0-AR7)Eight 16-bit memory mapped registersUsed in indirect addressing to generate the 16-bit address for data memory spaceCan also be used as general purpose registers and counters

STACK POINTER (SP)It is a 16- bit memory mapped register. It always points to top of the stackThis register is updated on execution of PUSHD,PUSHM,POPD and POPM instructionsIn PUSH operation SP is pre-decremented and data is pushed to the memory location pointed by SP. In POP operation the content of memory location pointed by SP is popped and then SP is incremented so that it is pointed to top of the stack.

CIRCULAR BUFFER SIZE REGISTER(BK)This memory mapped register is used in connection with circular addressing mode. Circular addressing mode is very essential in signal processing operations like convolutions correlations etc.This register should be loaded with the size of the circular buffer that is used in circular addressing mode.

BLOCK REPEAT REGISTERES(BRC,RSA,REA)There may be occasions where you have to execute a block of instructions repeatedly.The Block repetition counter(BRC) specifies the number of times the block of instructions are to be executed.Block repeat starting address register(RSA) holds the starting address of the block of instructions which is nothing but the address of the following instruction of RPTB instruction.Repeat ending address register(REA) holds the end address of the block to be repeated. This address should be specified in the RPTB instruction.

ARITHMETIC LOGIC UNIT(ALU)40-bit ALUPerforms wide range of arithmetic and logical operations in single cycle.The result is usually transferred to destination accumulator either A or BIn some cases the destination may be a data memory location

ALUThe x-input is either barrel shifter output (or) a data memory operand from data bus(DB)The y-input is from one of the accumulators or T register or from data bus CBWhen the data operand is received from DB/CB bus the 40-bit ALU input is sign extended when SXM=1 Overflow of the result can be prevented through ALU saturation logicALU saturation logic is enabled by setting OVM flag in ST1

ALUOVA/OVB flags of ST0 are affected if overflow occursCarry flag is affected after arithmetic, shift and rotate operationsALU can be operated in dual 16-bit mode by setting C16 flag of ST1Carry flag is not affected by logical or other non arithmetic operations

BARREL SHIFTERAccomplish the required number of shift of data in single cycle.Performs the pre-scaling of input data memory operand or accumulator content before passing it to ALUPerforms post-scaling accumulator before storing the accumulator value into data memory

MULTIPLIER/ADDER UNIT

MULTIPLIER/ADDER UNITPerforms the multiply and accumulate (MAC) operation in one pipeline phase cycle17 x 17 dedicated hardware multiplier40- bit dedicated adderThree multiplexers Sign extension controlFractional mode controlZero detector, RounderOverflow/saturation logic

COMPARE SELECT AND STORE UNIT

COMPARE SELECT AND STORE UNITApplication specific hardware unit dedicated to ACS operations of Viterbi operatorALU performs the 16-bit double addition part of ACS operation by configuring ALU in dual 16-bit mode.CMPS instruction is used to implement the CSS operationTRN register and TC bit of ST0 are updated

ADDRESS GENERATION UNITSData address generation unit(DAGEN) computes the addresses of data memory operands based on the addressing mode specified in the instructionProgram address generation unit (PAGEN) loads the program counter(PC) with the address of instruction to be executed.PAGEN usually increments the PC when sequential instructions are executed.PAGEN loads the PC with non-sequential value when branching like operations happened Some instructions may use absolute addressing to access the data items stored in program memory

THE C54X PIPELINEThe C54X instruction pipeline consists of 6 levelsPrefetchFetchDecode AccessReadexecute

ON-CHIP PERIPHERALSGeneral purpose I/O pins BIO,XFSoftware programmable wait-state generatorHardware timerClock generatorSerial ports * synchronous* Buffered* TDM