TLE8110 - Preliminary Application-Note - SPI and Daisy-Chain - Rev.0.2

7/26/2019 TLE8110 - Preliminary Application-Note - SPI and Daisy-Chain - Rev.0.2

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TLE8110EESPI and Daisy-Chain

Automot ive Power

Appl icat ion NoteThis document is subject to changes without further notice to customer

Rev.0.2, 2011-06-14


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CONFIDENTIAL

Application Note 2 Rev.0.2, 2011-06-14This document is subject to changes without further notice to customer

Abstract

Note: The following information is given as a hint for the usage of the device only and shall not be regarded as a

description or warranty of a certain functionality, condition or quality of the device.

This Application Note is intended to describe the TLE8110EE daisy-chain capability and to provide the right

instruments in order to implement a reliable SPI communication in a daisy-chain environment.

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 SPI communication and compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Complete SPI cycle (normal 16-bit protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Complete SPI cycle with compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 16-bit commands and compactCONTROL (2x8-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Daisy-Chain connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 TLE8110EE in daisy-chain environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1.1 Rule #1: all TLE8110EE routed at the beginning of the daisy-chain . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.2 Rule #2: do not use compactCONTROL (2x8-bit protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.3 Rule #3: avoid compactCONTROL patterns as first 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.4 Rule #4: if DRA/DRACL is issued, NOP command must be sent to next device . . . . . . . . . . . . . . 10

3.1.5 Rule #5: if DRA/DRACL is issued, response of next device must be ignored . . . . . . . . . . . . . . . . . 10

3.2 Case of several TLE8110EE connected in daisy-chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 TLE8110EE - normal 16-bit SPI cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2 TLE8110EE - SPI cycle issuing a compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 TLE8110EE in a daisy-chain - normal SPI cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4 Issue: daisy-chain cycle with first 8-bit as compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.4.1 Solution: 8-bit (00H) upfront extention of the SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.5 Issue: DRACL to device.n, response=compactCONTROL for device.n+1 . . . . . . . . . . . . . . . . . . . . . 26

5.5.1 Solution: NOP to device.n+1, next response ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31


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IntroductionCONFIDENTIAL


1 Introduction

The TLE8110EE is equipped with a 16-bit Serial Peripheral Interface (SPI), for controlling the device and to query

the diagnosis status. The use of a modulo-8 counter, for checking the SPI frame length, makes the device capable

of daisy-chaining with other devices as long as the total SPI frame is a multiple of 8-bit. Furthermore the

TLE8110EE implements an efficient communication feature called compactCONTROL(or 2x8-bit protocol) which

allows a significant reduction of the Controller workload.

Attention: The 2x8-bit protocol is not intended for a daisy-chain operation and might, under certain

conditions, interfere with the 16-bit protocol, making the daisy-chain impracticable. In this

document a solution will be presented which allows to reliably operate the device in a daisy-

chain environment.

Note: From now on, in this document, the bits 15 to 8 of an SPI word will be referred to as high-byte and the bits

7 to 0 as low-byte, for more flexibility.

Note: Fictitious names, instead of boolean values, will be used for SPI commands/responses that may notcorrespond to the names used in the data sheet.

Note: All the figures will show a data flow from the right to the left, in order to have the same view as we would

observe on the oscilloscope measurement and avoid any confusion, see Figure 1.

Figure 1 SPI data flow

SPI data flow

Input dataMSB LSB

1 2 3 4 5 6 7 8

Slave

TLE8110

SI

CS

CLK

SO

Master

XC2700

16/32-bit C

AUDO MAX

TriCore

32-bit C

SI

CS

time0

Output dataMSB LSB

0

CLK

SO

time

MOSI (from master)MISO (to master)

data flow


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SPI communication and compactCONTROLCONFIDENTIAL


2 SPI communication and compactCONTROL

2.1 Complete SPI cycle (normal 16-bit protocol)

In Figure 1 a complete SPI cycle is shown, where in 16 clock pulses a complete command is shifted from

Controller into the TLE8110EE and a complete response is shifted out from the TLE8110EE to the C. The SPI

cycle is composed of the following steps:

1. Cycle-1: CS high-to-low

the reponse to the previous cycle-0 command is made available in the TLE8110EE shift register

2. Cycle-1: Clock 1 to 16

response to cycle-0 is shifted from SO pin to the C (1 bit each clock pulse)

command of cycle-1 is shifted from C into SI pin (1 bit each clock pulse)

3. Cycle-1: CS low-to-high

command of cycle-1 is interpreted by the device


the reponse to cycle-1 command is made available in the TLE8110EE shift register

5. etc.

For detailed visual description please refer to Chapter 5.1.

Figure 2 Normal 16-bit SPI cycle

SPI cycle

MOSI (from C)MISO (to C)

TLE8110

command

(of cycle-0)

command

(of cycle-1)

16-bit

cycle-1 CS high-to-low:

response to previous cycle-0 made availableTLE8110

response

(to cycle-0)

data flow

command

(of cycle-1)

cycle-1 Clock=8:

8-bit of response to cycle -0 shifted out

8-bit of command of cycle -1 shifted inTLE8110

response

(to cycle-0)

command

(of cycle-1)

cycle-1 Clock=16:

complete response to cycle-0 shifted out

complete command of cycle-1 shifted inTLE8110

response

(to cycle -0)

command

(of cycle-1)

cycle-1 CS low-to-high:

command of cycle-1 interpretedTLE8110

response

(to cycle -0)

command

(of cycle-1)



command

(of cycle-2)

response

(to cycle-1)

cycle-2 Clock=8:

8-bit of response to cycle -1 shifted out

8-bit of command of cycle-2 shifted inTLE8110

command

(of cycle-2)

response

(to cycle-1)

0

time

CS

CLK

SPIcycle-1

SPIcycle-2

16-clocks

high-byte

low-byte

high-byte


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2.2 Complete SPI cycle with compactCONTROL

In Figure 2 a complete SPI cycle is shown, where the 2x8-bit protocol (compactCONTROL) is used for the

TLE8110EE. The SPI cycle is composed of the following steps:


the reponse to the previous cycle-0 command is made available in the TLE8110EE shift register


high-byte of the response to cycle-0 is shifted from SO pin to the Controller

high-byte of compactCONTROLis shifted from Controller into SI pin

low-byte of the response to cycle-0 is overridden with Diagnosis Output Register content (DOx)


modified response to cycle-0 is shifted from SO pin to C (low-byte overridden)

complete compactCONTROLcommand is shifted from C into SI pin

4. Cycle-1: CS low-to-high

complete compactCONTROL command of cycle-1 is interpreted by the device5. Cycle-2: CS high-to-low

Output Pin Feedback Register content (OPF) is provided as high-byte of the reponse

6. etc.


Figure 3 SPI cycle with compactCONTROL

SPI cycle - compactCONTROL


TLE8110

command

(of cycle-0)compactCONTROL

16-bit



response

(to cycle-0)

data flow

compactCONTROL

cycle-1 Clock=8:

8-bit of compactCONTROL shifted in

low-byte of response overridden with DOxTLE8110

response

(to cycle-0)compactCONTROL

cycle-1 Clock=16:

modified response shifted outTLE8110

response

(to cycle -0)compactCONTROL


full compactCONTROL interpretedTLE8110

response

(to cycle -0)compactCONTROL


OPF made available as response high-byteTLE8110

compactCONTROL

cycle-2 Clock=8:

DOx content as response low-byteTLE8110

compactCONTROL

0

time

CS

CLK

SPIcycle-1

SPIcycle-2

16-clocks

DOx

OPF 00H

OPF

DOx

DOx

high-byte

low-byte

high-byte


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2.3 16-bit commands and compactCONTROL(2x8-bit)

The use of the highly efficient compactCONTROLcommunication can interfere with the standard 16-bit response

related to the previous frame, as can be deducted from the above paragraphs. Therefore, as also suggested inthe TLE8110EE data sheet, it is required to issue a NOP command to the device any time that there is a switch

between 16-bit and 2x8-bit protocol. Sending a NOP command before switching to 2x8-bit protocol will have the

effect of ignoring the response related to the SPI cycle immediately before a compactCONTROLcommand is

issued, please refer to the device data sheet for more details.


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Daisy-Chain connectionCONFIDENTIAL


3 Daisy-Chain connection

The TLE8110EE is designed to be connected in a daisy-chain configuration, the first device output (SO) being

connected to the second device input (SI) etc, Figure 4. Devices designed for daisy-chaining, after having

transferred their own response data on the SO, basically shift through the data as seen on the SI input. In this

configuration the entire SPI chain acts as a shift register. The Controller will send, in cascade, the data addressed

to each device on the MOSI line (Master-Out Slave-In), first the data to the last device (cmd.n, cmd.n-1, etc.). At

the same time all the responses will be shifted on the MISO line (Master-In Slave-Out), first the response of the

last device (resp.n, resp.n-1 etc.), Figure 5. For a detailed visual description please refer to Chapter 5.3.

Figure 4 Daisy-Chain Connection

Figure 5 TLE8110EE in daisy-chain, SPI cycle

daisy -chain connection

slave.1

TLE8110

SI

CS CLK

SO

XC270016/32-bit C

AUDO MAX

TriCore

32-bit C

SI

CS

CLK

SO

data flow

slave.2

TLE8110

SI

CS CLK

SOslave.3

Other

SI

CS CLK

SO

slave.1TLE8110

cmd.1

(of cycle-0)

slave.1TLE8110

rsp.1

(to cycle-0)

data flow

slave.1TLE8110

slave.1TLE8110

slave.1TLE8110

slave.1TLE8110

rsp.1

(to cycle-1)

slave.1TLE8110

SPI cycle - Daisy-Chain


slave.2TLE8110

cmd.2

(of cycle -0)

cmd.2

(of cycle-1)

32-bit


rsp.0 to previous cycle-0 made availableslave.2TLE8110

rsp.2

(to cycle -0)

cycle-1 Clock=8:

8-bit of rsp.0 to cycle-0 shifted out

8-bit of cmd.1 of cycle-1 shifted inslave.2

TLE8110

cycle-1 Clock=32:

complete rsp.0 to cycle-0 shifted out

complete cmd.1 of cycle-1 shifted inslave.2

TLE8110


cmd.1 of cycle-1 interpretedslave.2TLE8110


rsp.0 to previous cycle-1 made availableslave.2TLE8110

rsp.2

(to cycle -1)

cycle-2 Clock=8:

8-bit of rsp.0 to cycle-1 shifted out

8-bit of cmd.1 of cycle-2 shifted inslave.2

TLE8110

0

time

CS

CLK

SPIcycle-1

SPIcycle-2

32-clocks

cmd.1

(of cycle-1)

rsp.1

(to cycle-0)

rsp.2

(to cycle-0)

rsp.1

(to cycle-0)

rsp.2

(to cycle-0)

cmd.2

(of cycle-1)

cmd.1

(of cycle-1)

cmd.2

(of cycle-1)

cmd.1

(of cycle-1)

cmd.2

(of cycle -1)

cmd.1

(of cycle-1)

cmd.2

(of cycle -1)

cmd.1

(of cycle-1)

cmd.2

(of cycle-2)

cmd.1

(of cycle-2)

rsp.1

(to cycle-1)

rsp.2

(to cycle-1)

cmd.2

(of cycle-2)

cmd.1

(of cycle-2)

to slave.2 to slave.1

from slave.2 from slave.1


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3.1 TLE8110EE in daisy-chain environment

Due to its immediate reaction to the first 8-bit shifted at the input, if coinciding with compactCONTROLbit-patterns,

the TLE8110EE requires a special care when connected in a daisy-chain environment.

Note: No unwanted device operation can be set due to an interference of daisy-chain data with compactCONTROL

commands, but only wrong responses can be expected from the TLE8110EE.

Note: The user must ensure that the first 8-bit shifted into the SI input of each TLE8110EE, after the CS high-to-

low transition, are not coinciding with any of the compactCONTROL bit-patterns.

This opens up to a list of basic rules to follow in order to have a reliable SPI communication in a daisy-chain

environment, these few rules are explained in the next paragraphs and some detailed pictures are shown in the

Chapter 5. The full command set with related responses of the TLE8110EE is provided in Figure 6.


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Figure 6 TLE8110 full command set, highlighted daisy-chain critical bit-patterns


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3.1.1 Rule #1: all TLE8110EE routed at the beginning of the daisy-chain

The TLE8110EE can be connected in daisy-chain with any other device (if equipped with 8-bit multiple SPI):

In general the user has no control of the other devices output

The C output can instead be controlled via software

Therefore, in order to have a full control of the bit-patterns shifted into the SI of the TLE8110EE, all TLE8110EE

must be routed at the beginning of the chain and other devices afterward.

3.1.2 Rule #2: do not use compactCONTROL(2x8-bit protocol)

Of course the compactCONTROL featureis not compatible with the daisy-chain connection, therefore it must

not be used.

3.1.3 Rule #3: avoid compactCONTROLpatterns as first 8-bit

In general, if other devices are also connected, according to the rule #1, the first slave on the chain will be a

TLE8110EE, therefore the first 8-bit of the complete SPI frame, even though addressed to the last slave on the

chain, can be interpreted as compactCONTROL,depending on the command set of the last slave. In that case

the response expected from the first TLE8110EE will be altered (low-byte overridden) as shown in Figure 7.

Please refer to Figure 6for bit patterns to avoid as first 8-bit. Since the command set of non-TLE8110EE devices

is not given, the most general solution is to extend the SPI frame with additional 8-bit, all zeros (00H), at the

beginning. This way there will be no command misinterpretation for the first TLE8110EE on the chain. The last

8-bit of the SPI response has to be thrown away cause they do not represent any useful information, see Figure 7.


3.1.4 Rule #4: if DRA/DRACL is issued, NOP command must be sent to next device

The response of a TLE8110EE (slave.n), which is shifted to the next TLE8110EE (slave.n+1) on the chain, can

also be interpreted as a compactCONTROLif two specific commands are issued:

Diagnosis Register A Read command (DCC_DRA as per data sheet) issued

Diagnosis Register A Clear command (DCC_DRACL as per data sheet) issued

Those two commands are the only ones, in the TLE8110EE command set, that, together with specific

combinations of the channels diagnosis status, can trigger a response which might coincide with a

compactCONTROLcommand, see Figure 6and refer to device data sheet for more details. Since there is no

control of the channels diagnosis status, such combinations cannot be avoided: the solution is to send a NOP

command to the next TLE8110EE (slave.n+1) any time a DRA/DRACL command is issued to the previous

TLE8110EE (slave.n), see Figure 8.

3.1.5 Rule #5: if DRA/DRACL is issued, response of next device must be ignored

As a completion of the rule #4, when a DRA/-CL command is issued to the TLE8110EE (slave.n), in the next

SPI cycle the response of the TLE8110EE (slave.n+1) must be ignored , see Figure 8. For detailed visual

description please refer to Chapter 5.5.

3.2 Case of several TLE8110EEconnected in daisy-chain

If several TLE8110EE are connected in daisy-chain and a DRA/-CL command has to be sent to all devices in the

chain, the most efficient way to apply the rules #4 and #5 requires 3 SPI cycles, see Figure 9:

1. Cycle 1: Issue DRA/-CL to all odd devices and NOP command to all even devices on the chain

2. Cycle 2:

Ignore responses of all even devices

Issue DRA/-CL to all even devices and NOP command to all odd devices on the chain (opposite of point 1)

3. Cycle 3: Ignore responses of all odd devices


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Figure 7 First 8-bit as compactCONTROL

First 8-bit as compactCONTROL

slave.n

Otherrsp.1

(cycle-0)

00H

slave.1

TLE8110rsp.n

(cycle-0)

cmd.n

(cycle-1)

cmd.1

(cycle -1)

slave.n

Other

slave.1

TLE8110

slave.n

Other

slave.1

TLE8110

rsp.1

(cycle-0)

rsp.n

(cycle-0)

cmd.n

(cycle-1)

cmd.1

(cycle-1)DOx

rsp.1

(cycle-0)

rsp.n

(cycle-0)

cmd.n

(cycle-1)

cmd.1

(cycle-1)DOx


if first 8-bit are a

compactCONTROL

wrong response

from slave.1

slave.n

Otherrsp.1

(cycle-0)

slave.1

TLE8110rsp.n

(cycle-0)

cmd.n

(cycle-1)

cmd.1

(cycle-1)


slave.n

Other

slave.1

TLE8110

00Hrsp.1

(cycle-0)

rsp.n

(cycle-0)

cmd.n

(cycle-1)

cmd.1

(cycle -1)

slave.n

Other

slave.1

TLE8110

00Hrsp.1

(cycle-0)

rsp.n

(cycle-0)

cmd.n

(cycle-1)

cmd.1

(cycle-1)

no issue

to be ignored

8-bit extension

daisy-chain SPI frame

Solution: 8-bit (00H) upfront extension of the SPI frame

Issue: first-8-bit of SPI frame (to slave.n) can be interpreted as compactCONTROL by slave .1

daisy-chain SPI frame

SPI data Flow

cycle-1: as first 8-bit slave.1 sees a

compactCONTRL

cycle-1: end of transfer, wrong

response from slave.1

cycle-1: 00H as first 8-bit

cycle-1: end of transfer, right

response from slave.1

data flow


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13/32


14/32


ConclusionCONFIDENTIAL


4 Conclusion

Text...


15/32


AppendixCONFIDENTIAL


5 Appendix

In this Appendix a detailed description of the SPI communication between TLE8110EE and C is presented.

Several circumstances are taken in consideration and for each condition the devices registers content are shown

at different time intervals of the communication.

Note: Fictitious names, instead of boolean values, will be used for SPI commands/responses that may not

correspond to the names used in the device data sheet, see Figure 11for a command/respone names

description.

Figure 10 Commands/Responses names description

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

16-bit command/response R S P A H 0 0 _ R S P A L 0 0 _

Other Used names

CMD = Command DOX_DAT_ = Diagnosis Output content

RSP = Response OPF_DAT_ = Output Pin Feedback content

XXX = other used names CPCTxxx_ = compactCONTROL command

A = to/from device A DRACL_x_ = Diagnosis Register A Clear

H=upper, L=lower DRA_DAT_ = Response to DRA/-CL command

00 = related to cycle-0

01 = related to cycle-1 etc.

high-byte low-byte


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5.1 TLE8110EE - normal 16-bit SPI cycle

Figure 11 CS=High - Starting condition

Figure 12 CS high-to-low - response to cycle-0 is made available at shift register

Figure 13 Clock=1 - first bit transferred (shifted through)

Figure 14 Clock=4 - first 4 bits transferred (shifted through)

Requested Data

R S P _ H 0 0 _ R S P _ L 0 0 _

Shift Register Output Register

SI SI C M D _ H 0 1 _ C M D _ L 0 1 _

Loaded Command Input Register

SO SO

CS CS

CLK CLK

TLE8110 Controller

High

Requested Data


R S P _ H 0 0 _ R S P _ L 0 0 _ SI SI C M D _ H 0 1 _ C M D _ L 0 1 _


SO SO

CS CS

CLK CLK

TLE8110 Controller

High L

Requested Data


S P _ H 0 0 _ R S P _ L 0 0 _ C SI SI M D _ H 0 1 _ C M D _ L 0 1 _


R

SO SO

CS CS

CLK CLK

TLE8110 Controller

High Low

1

Requested Data


H 0 0 _ R S P _ L 0 0 _ C M D _ SI SI H 0 1 _ C M D _ L 0 1 _


R S P _

SO SO

CS CS

CLK CLK

TLE8110 Controller

High Low

1 2 3 4


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Figure 15 Clock=8 - first 8 bits transferred TLE8110EE checks for compactCONTROL(not found)

Figure 16 Clock=16 - data transfer completed

Figure 17 CS low-to-high - Command interpreted by the TLE8110EE

Requested Data


R S P _ L 0 0 _ C M D _ H 0 1 _ SI SI C M D _ L 0 1 _


R S P _ H 0 0 _

SO SO

CS CS

CLK CLK

TLE8110 Controller

ow

1 2 3 4 5 6 7 8

Requested Data

Shift Register Output Register C M D _ H 0 1 _ C M D _ L 0 1 _ SI SI


R S P _ H 0 0 _ R S P _ L 0 0 _

SO SO

CS CS

CLK CLK

TLE8110 Controller

Low

9 10 11 12 13 14 15 16

Requested Data

R S P A H 0 1 _ R S P A L 0 1 _


SI SI


C M D _ H 0 1 _ C M D _ L 0 1 _ R S P _ H 0 0 _ R S P _ L 0 0 _

SO SO

CS CS

CLK CLK

TLE8110 Controller

Low

10 11 12 13 14 15 16


18/32




5.2 TLE8110EE - SPI cycle issuing a compactCONTROL

Figure 18 CS high-to-low - response to previous cycle made available at shift register

Figure 19 Clock=4 - 4 bits transferred (shifted through)

Figure 20 Clock=8 - first 8 bits recognized as compactCONTROL, DOx overrides response low-byte

Figure 21 Clock=16 - data transfer completed

Requested Data


R S P _ H 0 0 _ R S P _ L 0 0 _ SI SI C P C T H 0 1 _ C P C T L 0 1 _


SO SO

D O X _ D A T _ Diagnosis Output Register CS CS

O P F _ D A T _ Output Pin Feedback Register

CLK CLK

TLE8110 Controller

High L

Requested Data


H 0 0 _ R S P _ L 0 0 _ C P C T SI SI H 0 1 _ C P C T L 0 1 _


R S P _

SO SO



CLK CLK

TLE8110 Controller

High Low

1 2 3 4

Requested Data

Shift Register compactCONTROL Output Register

D O X _ D A T _ C P C T H 0 1 _ SI SI C P C T L 0 1 _


R S P _ H 0 0 _

SO SO



CLK CLK

TLE8110 Controller

ow

1 2 3 4 5 6 7 8

Requested Data

Shift Register compactCONTROL Output Register

C P C T H 0 1 _ C P C T L 0 1 _ SI SI


R S P _ H 0 0 _ D O X _ D A T _

SO SO



CLK CLK

TLE8110 Controller

Low

9 10 11 12 13 14 15 16


19/32




Figure 22 CS low-to-high - compactCONTROL interpreted, OPF set as response high-byte

Requested Data

O P F _ D A T _


SI SI


C P C T H 0 1 _ C P C T L 0 1 _ R S P _ H 0 0 _ D O X _ D A T _

SO SO



CLK CLK

TLE8110 Controller

Low

10 11 12 13 14 15 16


20/32




5.3 TLE8110EE in a daisy-chain - normal SPI cycle

Figure 23 CS high-to-low - each device put the response to previous cycle in the shift register

Figure 24 Clock=4 - first 4 bits transferred (shifted through)

Requested Data

R S P B H 0 0 _ R S P B L 0 0 _


R S P B H 0 0 _ R S P B L 0 0 _ SI SI C M D A H 0 1 _ C M D A L 0 1 _ C M D B H 0 1 _ C M D B L 0 1 _


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CS CS

CLK CLK

Requested Data

R S P A H 0 0 _ R S P A L 0 0 _

Shift Register

R S P A H 0 0 _ R S P A L 0 0 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK

TLE8110 device B Controller

TLE8110 device A

H ig h L

Requested Data


H 0 0 _ R S P B L 0 0 _ C M D A SI SI H 0 1 _ C M D A L 0 1 _ C M D B H 0 1 _ C M D B L 0 1 _


R S P A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CS CS

CLK CLK

Requested Data

Shift Register

H 0 0 _ R S P A L 0 0 _ R S P B SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


TLE8110 device A

High Low

1 2 3 4


21/32




Figure 25 CS low-to-high - each device interprets its command

Requested Data


C M D B H 0 1 _ C M D B L 0 1 _ SI SI


C M D B H 0 1 _ C M D B L 0 1 _ R S P A H 0 0 _ R S P A L 0 0 _ R S P B H 0 0 _ R S P B L 0 0 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CS CS

CLK CLK

Requested Data

Shift Register

C M D A H 0 1 _ C M D A L 0 1 _ SI

Loaded Command

C M D A H 0 1 _ C M D A L 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


TLE8110 device A

L H

26 27 28 29 30 31 32


22/32




5.4 Issue: daisy-chain cycle with first 8-bit as compactCONTROL

Figure 26 CS high-to-low - responses made available

Figure 27 Clock=8 - first 8-bit addressed to device.A represent a compactCONTROL for device.B

Requested Data




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

R S P A H 0 0 _ R S P A L 0 0 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


OTHER device A

H ig h L

if first 8-bit addressed to device A

Requested Data coincides w ith compactCONTROL


D O X _ D A T _ C M D A H 0 1 _ SI SI C M D A L 0 1 _ C M D B H 0 1 _ C M D B L 0 1 _


R S P A H 0 0 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

R S P A L 0 0 _ R S P B H 0 0 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


OTHER device A

ow

1 2 3 4 5 6 7 8


23/32




Figure 28 CS low-to-high - wrong response from device.B is retrieved

Requested Data


C M D B H 0 1 _ C M D B L 0 1 _ SI SI


C M D B H 0 1 _ C M D B L 0 1 _ R S P A H 0 0 _ R S P A L 0 0 _ R S P B H 0 0 _ D O X _ D A T _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

C M D A H 0 1 _ C M D A L 0 1 _ SI

Loaded Command

C M D A H 0 1 _ C M D A L 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


OTHER device A

L H

26 27 28 29 30 31 32


24/32




5.4.1 Solution: 8-bit (00H) upfront extention of the SPI frame

Figure 29 CS high-to-low - responses made available

Figure 30 Clock=8 - no misinterpretation as first 8-bit are all zeros (00H)

Requested Data


R S P B H 0 0 _ R S P B L 0 0 _ SI SI 0 0 0 0 0 0 0 0 C M D A H 0 1 _ C M D A L 0 1 _ C M D B H 0 1 _ C M D B L 0 1 _


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO



CLK CLK

Requested Data

Shift Register

R S P A H 0 0 _ R S P A L 0 0 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


OTHER device A

additional 8-bit 00H

H ig h L

no issue

Requested Data


R S P B L 0 0 _ 0 0 0 0 0 0 0 0 SI SI C M D A H 0 1 _ C M D A L 0 1 _ C M D B H 0 1 _ C M D B L 0 1 _


R S P A H 0 0 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO



CLK CLK

Requested Data

Shift Register

R S P A L 0 0 _ R S P B H 0 0 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


OTHER device A

additional 8-bit 00H

ow

1 2 3 4 5 6 7 8


25/32




Figure 31 CS low-to-high - correct response from device.B is retrieved

Requested Data


C M D B H 0 1 _ C M D B L 0 1 _ SI SI


C M D B H 0 1 _ C M D B L 0 1 _ R S P A H 0 0 _ R S P A L 0 0 _ R S P B H 0 0 _ R S P B L 0 0 _ 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO



CLK CLK

Requested Data

Shift Register

C M D A H 0 1 _ C M D A L 0 1 _ SI

Loaded Command

C M D A H 0 1 _ C M D A L 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

CS

CLK


OTHER device A

last 8-bit to be ignored

L H

34 35 36 37 38 39 40


26/32




5.5 Issue: DRACL to device.n, response=compactCONTROLfor device.n+1

Figure 32 Cycle-1 - CS high-to-low - DRACL issued to device.n (B)

Figure 33 Cycle-1 - CS high-to-low - DRACL interpreted, response represents compactCONTROL

Requested Data


R S P A H 0 0 _ R S P A L 0 0 _ SI SI C M D A H 0 1 _ C M D A L 0 1 _ D R A C L _ H _ D R A C L _ L _


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

R S P B H 0 0 _ R S P B L 0 0 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO

D O X _ D A T _ Diagnos is Out put Regis ter CS


CLK

TLE8110 device B (n) Controller

TLE8110 device A (n+1)

H ig h L

response to DRA/DRACL

Requested Data can coincide w ith compactCONTROL

R S P B H 0 1 _ R S P B L 0 1 _


SI SI


D R A C L _ H _ D R A C L _ L _ R S P B H 0 0 _ R S P B L 0 0 _ R S P A H 0 0 _ R S P A L 0 0 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

R S P A H 0 1 _ R S P A L 0 1 _

Shift Register

SI

Loaded Command

C M D A H 0 1 _ C M D A L 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



L H

26 27 28 29 30 31 32


27/32




Figure 34 Cycle-2 - Clock=8 - device.n+1 (A) sees response of device.n (B) as a compactCONTROL

Figure 35 Cycle-2 - CS low-to-high - wrong response retrieved from device.n+1 (A)

Requested Data


R S P B L 0 1 _ C M D A H 0 2 _ SI SI C M D A L 0 2 _ C M D B H 0 2 _ C M D B L 0 2 _


R S P A H 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

interpreted as compactCONTROL

Requested Data

Shift Register

D O X _ D A T _ R S P B H 0 1 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



ow

1 2 3 4 5 6 7 8

Requested Data


C M D B H 0 2 _ C M D B L 0 2 _ SI SI


C M D B H 0 2 _ C M D B L 0 2 _ R S P A H 0 1 _ D O X _ D A T _ R S P B H 0 1 _ R S P B L 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

C M D A H 0 2 _ C M D A L 0 2 _ SI

Loaded Command

C M D A H 0 2 _ C M D A L 0 2 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



L H

26 27 28 29 30 31 32


28/32




5.5.1 Solution: NOP to device.n+1, next response ignored

Figure 36 Cycle-1 - Clock=4 - DRACL issued to device.n (B) and NOP command to device.n+1 (A)

Figure 37 Cycle-2 - CS high-to-low - Response to DRACL is a compactCONTROL

Requested Data


H 0 0 _ R S P B L 0 0 _ N O P _ SI SI H 0 1 _ N O P _ L 0 1 _ D R A C L _ H _ D R A C L _ L _


R S P A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

H 0 0 _ R S P A L 0 0 _ R S P B SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



High Low

1 2 3 4

Requested Data

R S P B H 0 1 _ R S P B L 0 1 _




15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Shift Register

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



L H

27 28 29 30 31 32


29/32




Figure 38 Cycle-2 - Clock=8 - device.n+1 (A) sees response of device.n (B) as a compactCONTROL

Figure 39 Cycle-2 - CS low-to-high - response from device.n+1 (A) has to be ignored

Requested Data


R S P B L 0 1 _ C M D A H 0 2 _ SI SI C M D A L 0 2 _ C M D B H 0 2 _ C M D B L 0 2 _


0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

D O X _ D A T _ R S P B H 0 1 _ SI

Loaded Command

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



ow

1 2 3 4 5 6 7 8

Requested Data


C M D B H 0 2 _ C M D B L 0 2 _ SI SI


C M D B H 0 2 _ C M D B L 0 2 _ 0 0 0 0 0 0 0 0 D O X _ D A T _ R S P B H 0 1 _ R S P B L 0 1 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO SO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



CLK CLK

Requested Data

Shift Register

C M D A H 0 2 _ C M D A L 0 2 _ SI

Loaded Command

C M D A H 0 2 _ C M D A L 0 2 _

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO



CLK



response to be ignored

L H

26 27 28 29 30 31 32


30/32


Additional InformationCONFIDENTIAL


6 Additional Information

Description ...

Existing App. Note (Title)

For further information you may contact http://www.infineon.com/
http://www.infineon.com/http://www.infineon.com/


31/32


Revision HistoryCONFIDENTIAL


7 Revision History

Revision Date Changes

0.2 2011-06-14 Improved quality of Figure 6and Figure 10, colors fixed

Changed device to slave in daisy-chain description, use of high/low-byteMentioned C examles (XC2700, AUDO MAX)

0.1 2011-06-10 Draft


32/32

Edition 2011-06-14

Published byInfineon Technologies AG81726 Munich, Germany

2011 Infineon Technologies AGAll Rights Reserved.

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DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THEINFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFYANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBYDISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUTLIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANYTHIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE.

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Documents

TLE8110 - Preliminary Application-Note - SPI and Daisy-Chain - Rev.0.2