TLC5971 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB

GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

1 Fm

VCC

GND

PowerSupply

(6 V to 17 V)

DATA

CLK

GND

Controller(1)

¼ ¼

GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

1 Fm

¼ ¼

OptionalDevice DeviceOptional

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

TLC5971SBVS146D –AUGUST 2010–REVISED DECEMBER 2015

TLC5971 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver With 3.3-VLinear Regulator

1 Features 2 ApplicationsRGB LED Cluster Lamp Displays

1• 12 Constant-Current Sink Output Channels• Current Capability: 60 mA Per Channel 3 Description• Grayscale (GS) Control With Enhanced Spectrum

The TLC5971 device is a 12-channel, constant-PWM: current sink driver. Each output channel has16-Bit (65536 Steps) individually adjustable currents with 65536 PWM• Global Brightness Control (BC): grayscale (GS) steps. Also, each color group can be

7-Bit (128 Steps) for Each Color Group controlled by 128 constant-current sink steps with theglobal brightness control (BC) function. GS control• Power-Supply Voltage Range:and BC are accessible through a two-wire signal– Internal Linear Regulator: 6 V to 17 V interface. The maximum current value for each

– Direct Power Supply: 3 V to 5.5 V channel is set by a single external resistor. Allconstant-current outputs are turned off when the IC is• LED Supply Voltage: Up to 17 Vin an overtemperature condition.• Constant-Current Accuracy:

– Channel-to-Channel = ±1% (Typical) Device Information(1)

– Device-to-Device = ±1% (Typical) PART NUMBER PACKAGE BODY SIZE (NOM)• Data Transfer Rate: 20 MHz HTSSOP (20) 6.50 mm × 4.40 mm

TLC5971VQFN (24) 4.00 mm × 4.00 mm• Linear Voltage Regulator: 3.3 V

• Auto Display Repeat Function (1) For all available packages, see the orderable addendum atthe end of the data sheet.• Display Timing Reset Function

• Internal and External Selectable GS Clock• Thermal Shutdown (TSD) With Auto Restart• Unlimited Device Cascading• Operating Temperature Range: –40°C to +85°C

Typical Application Circuit Example (Internal Linear Regulator Using VCC = 6 V to 17 V)

(1) The output voltage range is from 0 V to 3.3 V.NOTE: The number of LEDs in series changes, depending on the VCC voltage.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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TLC5971SBVS146D –AUGUST 2010–REVISED DECEMBER 2015 www.ti.com

Table of Contents8.2 Functional Block Diagram ....................................... 141 Features .................................................................. 18.3 Feature Description................................................. 152 Applications ........................................................... 18.4 Device Functional Modes........................................ 183 Description ............................................................. 18.5 Programming........................................................... 194 Revision History..................................................... 2

9 Application and Implementation ........................ 265 Pin Configuration and Functions ......................... 39.1 Application Information............................................ 266 Specifications......................................................... 49.2 Typical Application .................................................. 266.1 Absolute Maximum Ratings ...................................... 49.3 System Examples ................................................... 316.2 ESD Ratings.............................................................. 4

10 Power Supply Recommendations ..................... 326.3 Recommended Operating Conditions....................... 411 Layout................................................................... 326.4 Thermal Information .................................................. 5

11.1 Layout Guidelines ................................................. 326.5 Electrical Characteristics........................................... 511.2 Layout Example .................................................... 326.6 Switching Characteristics .......................................... 7

12 Device and Documentation Support ................. 336.7 Dissipation Ratings ................................................... 812.1 Community Resources.......................................... 336.8 Typical Characteristics ............................................ 1112.2 Trademarks ........................................................... 337 Parametric Measurement Information ............... 1312.3 Electrostatic Discharge Caution............................ 337.1 Test Circuits ............................................................ 1312.4 Glossary ................................................................ 337.2 Pin Equivalent Input and Output Schematics ......... 13

13 Mechanical, Packaging, and Orderable8 Detailed Description ............................................ 14Information ........................................................... 338.1 Overview ................................................................. 14

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (September 2012) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision B (June 2012) to Revision C Page

• Changed typical application circuit (internal linear regulator), added footnote 1.................................................................... 1• Changed typical application circuit (direct power), added footnote 1................................................................................... 31• Added typical application circuit example (direct power supplying VCC = 3 V to 5.5 V, VLED = 15 V), added footnote 1..... 31

Changes from Revision A (December 2010) to Revision B Page

• Changed IOLKG parameter test conditions in Electrical Characteristics table.......................................................................... 5• Updated Figure 23................................................................................................................................................................ 15• Changed bit 217 description in Table 5................................................................................................................................ 24

Changes from Original (August 2010) to Revision A Page

• Changed Global Brightness Control bullet in Features .......................................................................................................... 1• Changed typical application circuit (internal linear regulator)................................................................................................. 1• Moved Thermal Shutdown and Noise Reduction sections................................................................................................... 18• Updated bit names for BCR, BCG, and BCB in Table 5 ...................................................................................................... 24• Changed typical application circuit (direct power) ................................................................................................................ 31

2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: TLC5971


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IREF

GND

OUTR0

OUTG0

OUTB0

OUTR1

OUTG1

OUTB1

SDTI

SCKI

VREG

VCC

OUTB3

OUTG3

OUTR3

OUTB2

OUTG2

OUTR2

SDTO

SCKO

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PowerPAD

(Bottom Side)

SDTI

SCKI

NC(1)

NC

SCKO

SDTO

GND

NC

IREF

VREG

NC

VCC

1

2

3

4

5

6

18

17

16

15

14

13

Thermal Pad

(Bottom Side)

OU

TB

12

4O

UT

R2

7

OU

TG

12

3O

UT

G2

8

OU

TR

12

2O

UT

B2

9

OU

TB

02

1O

UT

R3

10

OU

TG

02

0O

UT

G3

11

OU

TR

01

9O

UT

B3

12

TLC5971www.ti.com SBVS146D –AUGUST 2010–REVISED DECEMBER 2015

5 Pin Configuration and Functions

PWP PackageRGE Package20-Pin HTSSOP24-Pin VQFNBottom ViewBottom View

NC = not connected

Pin FunctionsPIN

I/O DESCRIPTIONNAME PWP RGESDTI 9 1 I Serial data input for the 224-bit shift register

Serial data shift clock input.Data present on SDTI are shifted to the LSB of the 224-bit shift register with the SCKI rising edgeSCKI 10 2 I Data in the shift register are shifted toward the MSB at each SCKI rising edge.The MSB data of the shift register appear on SDTO.Serial data output of the 224-bit shift register.

SDTO 12 6 O SDTO is connected to the MSB of the 224-bit shift register.Data are clocked out at the SCKI rising edge.Serial data shift clock output.

SCKO 11 5 O The input shift clock signal from SCKI is adjusted to the timing of the serial data output for SDTOand the signal is then output at SCKO.Internal linear voltage regulator output.A decoupling capacitor of 1 µF must be connected. This output can be used for external devices

VREG 20 15 I/O as a 3.3-V power supply. This terminal can be connected with the VREG terminal of otherdevices to increase the supply current. Also, this pin can be supplied with 3 V to 5.5 V from anexternal power supply by connecting it to VCC.Maximum current programming terminal.A resistor connected between IREF and GND sets the maximum current for every constant-IREF 1 16 I/O current output. When this terminal is directly connected to GND, all outputs are forced off. Theexternal resistor should be placed close to the device.

OUTR0 3 19 ORED constant-current outputs.OUTR1 6 22 OMultiple outputs can be configured in parallel to increase the constant-current capability.

OUTR2 13 7 O Different voltages can be applied to each output.OUTR3 16 10 OOUTG0 4 20 O

GREEN constant-current outputs.OUTG1 7 23 OMultiple outputs can be configured in parallel to increase the constant-current capability.

OUTG2 14 8 O Different voltages can be applied to each output.OUTG3 17 11 OOUTB0 5 21 O

BLUE constant-current outputs.OUTB1 8 24 OMultiple outputs can be configured in parallel to increase the constant-current capability.

OUTB2 15 9 O Different voltages can be applied to each output.OUTB3 18 12 OVCC 19 13 — Power-supply terminal

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Pin Functions (continued)PIN

I/O DESCRIPTIONNAME PWP RGEGND,PowerPAD 2 — —(PWP)

Power ground terminalGND,exposed — 18 —thermalpad (RGE)

3, 4, 14,NC — — No internal connection17

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range, unless otherwise noted. (1) (2)

MIN MAX UNIT

Supply voltage, VCC –0.3 18 V

IREF –0.3 VREG + 0.3 VInput voltage

SDTI, SCKI –0.3 VREG + 0.6 V

OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3 –0.3 18 V

Output voltage SDTO, SCKO –0.3 VREG + 0.3 V

VREG –0.3 6 V

OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3 75 mAOutput current (DC)

VREG –30 mA

Operating junction temperature, TJ (max) 150 °C

Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

6.2 ESD RatingsVALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000ElectrostaticV(ESD) Vdischarge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsat TA = –40°C to +85°C, and VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, unless otherwise noted.

MIN NOM MAX UNIT

DC CHARACTERISTICS

VCC Supply voltage, internal voltage regulator used 6 17 V

VREG Supply voltage, VREG connected to VCC 3 3.3 5.5 V

Voltage applied to outputVO 17 V(OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3)

VIH High-level input voltage (SDTI, SCKI) 0.7 × VREG VREG V

VIL Low-level input voltage (SDTI, SCKI) GND 0.3 × VREG V

VIHYS Input voltage hysteresis (SDTI, SCKI) 0.2 × VREG V

IOH High-level output current (SDTO) –2 mA

IOL Low-level output current (SDTO) 2 mA

Constant output sink currentIOLC 60 mA(OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3)




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Recommended Operating Conditions (continued)at TA = –40°C to +85°C, and VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, unless otherwise noted.

MIN NOM MAX UNIT

IREG Voltage regulator output current (VREG) –25 mA

TA Operating free temperature range –40 85 °C

TJ Operating junction temperature –40 125 °C

AC CHARACTERISTICS

fCLK (SCKI) Data clock frequency and GS control clock frequency, SCKI 0.007 20 MHz

tWH/tWL Pulse duration, SCKI 10 ns

tSU Setup time, SDTI – SCKI↑ 5 ns

tH Hold time, SDTI – SCKI↑ 3 ns

6.4 Thermal InformationTLC5971

THERMAL METRIC (1) PWP (HTSSOP) RGE (VQFN) UNIT20 PINS 24 PINS

θJA Junction-to-ambient thermal resistance 68.6 38 °C/WθJCtop Junction-to-case (top) thermal resistance 44.2 40.5 °C/WθJB Junction-to-board thermal resistance 19.3 10.2 °C/WψJT Junction-to-top characterization parameter 2.7 0.3 °C/WψJB Junction-to-board characterization parameter 15.7 10 °C/WθJCbot Junction-to-case (bottom) thermal resistance 1.8 2.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

6.5 Electrical CharacteristicsAt TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwisenoted. Typical values are at TA = 25°C and VCC = 12 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage, SDTO/SCKO IOH = –2 mA VREG – 0.4 VREG V

VOL Low-level output voltage, SDTO/SCKO IOL = 2 mA 0 0.4 V

II Input current, SDTI/SCKI VI = VREG or GND –1 1 µA

SDTI/SCKI = low, BLANK = 1, GSn = FFFFh,ICC 2 4 mABCX = 7Fh, VOUTXn = 1 V, RIREF = 24 kΩ (IOLCMax = 2 mA)

SDTI/SCKI = low, BLANK = 1, GSn = FFFFh,ICC1 6 9 mABCX = 7Fh, VOUTXn = 1 V, RIREF = 1.6 kΩ (IOLCMax = 30 mA)

SDTI = 10 MHz, SCKI = 20 MHz, BLANK = 0,Supply currentICC2 auto repeat enable, external GS clock selected, GSn = FFFFh, 14 22 mA

BCX = 7Fh, VOUTXn = 1 V, RIREF = 1.6 kΩ (IOLCMax = 30 mA)

SDTI = 10 MHz, SCKI = 20 MHz, BLANK = 0,ICC3 auto repeat enable, external GS clock selected, GSn = FFFFh, 21 36 mA

BCX = 7Fh, VOUTXn = 1 V, RIREF = 0.82 kΩ (IOLCMax = 60 mA)

All OUTXn on, BCX = 7Fh, VOUTXn = 1 V,IOLC Constant output current, OUTXn 56.3 60.5 64.7 mAVOUTfix = 1 V, RIREF = 0.82 kΩ (IOLCMax = 60 mA)

All OUTXn off, BCX = 7Fh, VOUTXn = 17 V,IOLKG Leakage output current, OUTXn 0.1 µAVOUTfix = 17 V, RIREF = 0.82 kΩ (IOLCMax = 60 mA)




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100

(I at VCC = 3 V)XnOLC

(I at VCC = 5.5 V) (I at VCC = 3 V)Xn Xn-OLC OLC

5.5 V 3 V-

D (%/V) = ´

I (mA) = 41 ´Xn(IDEAL)OLC

1.21

RIREF ( )W

D (%) =Ideal Output Current

- (Ideal Output Current)(I + I + I + I )X0 X1 X2 X3OLC OLC OLC OLC

4´ 100

D (%) = - 1I XnOLC

(I + I + I + I )X0 X1 X3X2OLC OLC OLC OLC

4

´ 100


Electrical Characteristics (continued)At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwisenoted. Typical values are at TA = 25°C and VCC = 12 V.


Constant-current error (1)All OUTXn on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,ΔIOLC (channel-to-channel in same color group), –3% ±1% 3%RIREF = 0.82 kΩ (IOLCMax = 60 mA)OUTXn

Constant current error (2) All OUTXn on, BCX = 7Fh, VOUTXn = VOUTfix = 1V,ΔIOLC1 (device-to-device in same color group), RIREF = 0.82 kΩ (IOLCMax = 60 mA), at same grouped color output –4% ±1 4%

OUTXn of OUTR0-3, OUTG0-3, and OUTB0-3

Line regulation of constant-current output, All OUTn on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,ΔIOLC2 –1 ±0.5 1 %/VOUTXn (3) RIREF = 0.82 kΩ (IOLCMax = 60 mA)

(1)The deviation of each output in the same color group (OUTR0-OUTR3 or OUTG0-OUTG3 or OUTB0-OUTB3)from the average current from the same color group. Deviation is calculated by Equation 1:

where(a) X = R/G/B,(b) n = 0-3. (1)

(2)The deviation of each color group constant-current average from the ideal constant-current value. Deviation iscalculated by Equation 2:

where(a) X = R/G/B. (2)

Ideal current is calculated by Equation 3 for the OUTRn and OUTGn groups:

where(a) X = R/G/B. (3)

(3)Line regulation is calculated by Equation 4:

where(a) X = R/G/B,(b) n = 0-3. (4)




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100

3 V 1 V-

´

(I at V = 1 V)Xn OUTXnOLC

(I at V = 3 V) (I at V = 1 V)-OLCXn OUTXn OLCXn OUTXnD (%/V) =


Electrical Characteristics (continued)At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwisenoted. Typical values are at TA = 25°C and VCC = 12 V.


Load regulation of constant-current output, All OUTn on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,ΔIOLC3 –3 ±1 3 %/VOUTXn (4) RIREF = 0.82 kΩ (IOLCMax = 60 mA)

TTSD Thermal shutdown temperature Junction temperature(5) 150 165 180 °C

THYS Thermal shutdown hysteresis Junction temperature(5) 5 10 20 °C

VIREF Reference voltage output, IREF RIREF = 0.82 kΩ 1.18 1.21 1.24 V

VREG Linear regulator output voltage, VREG VCC = 6 V to 17 V, IREG = 0 mA to –25 mA 3.1 3.3 3.5 V

ΔVREG Line regulation of linear regulator, VREG VCC = 6 V to 17 V, IREG = 0 mA 90 mV

ΔVREG1 Load regulation of linear regulator, VREG VCC = 12 V, IREG = 0 mA to –25 mA 120 mV

VSTR Undervoltage lockout release, VREG 2.5 2.7 2.9 V

VHYS Undervoltage lockout hysteresis, VREG 300 400 500 mV

(4)Load regulation is calculated by Equation 5:

where(a) X = R/G/B,(b) n = 0-3. (5)

(5) Not tested, specified by design.

6.6 Switching CharacteristicsAt TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, CVREG = 1 µF, CL = 15 pF, RL = 68 Ω, and VLED =5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC = 12 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITtR0 Rise time, SDTO/SCKO 3 10 nstR1 Rise time, OUTXn BCX = 7Fh 5 15 nstF0 Fall time, SDTO/SCKO 3 10 nstF1 Fall time, OUTXn BCX = 7Fh 15 25 nstD0 SCKI↑ to SDTO↑↓ 10 25 60 nstD1 SCKI↑ to SCKO↑ 5 15 40 nstD2

(1) SCKO↑ to SDTO↑↓ 5 10 20 nsSCKI↑ to OUTRn↑↓, BLANK = 0, BCXn =7Fh, OUTTMG = 1tD3 10 25 60 nsOr SCKI↓ to OUTRn↑↓, BLANK = 0,BCXn = 7Fh, OUTTMG = 0SCKI↑ to OUTGn↑↓, BLANK = 0, BCXnPropagation delay = 7Fh, OUTTMG = 1tD4 25 50 90 nsOr SCKI↓ to OUTGn↑↓, BLANK = 0,BCXn = 7Fh, OUTTMG = 0SCKI↑ to OUTBn↑↓, BLANK = 0, BCXn =7Fh, OUTTMG = 1tD5 40 75 120 nsOr SCKI↓ to OUTBn↑↓, BLANK = 0,BCXn = 7Fh, OUTTMG = 0Last SCKI↑ to internal latch pulsetD6

(2) 8/fOSC 16384/fOSC sgenarationtW(SCKO) Shift clock output one pulse width SCKO↑ to SCKO↓ 12 25 35 nsfOSC Internal oscillator frequency 6 10 12 MHz

(1) The propagation delays are calculated by tD2 = tD0 – tD1.(2) The generation timing of the internal latch pulse changes depending on the SCKI clock frequency; see the Internal Latch Pulse

Generation Timing section.




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t , t , t , t , t , t , t :, t , t , tR0 R1 F0 F1 D0 D1 D2 D3 D4 D5

INPUT(1) 50%

50%

90%

10%

OUTPUT

tD

t or tR F

V or VOL OUTXnL

V or VOH OUTXnH

GND

VREG

T , T :WH WL

SCKI(1)

SCKI(1)

SDTI(1)

T , T :SU H

TSU TH

VREG

VREG

GND

VREG

GND

GND

50%

50%

50%

TWH TWL


6.7 Dissipation RatingsDERATING FACTOR POWER RATING POWER RATING POWER RATINGPACKAGE ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C

HTSSOP 20-pin with PowerPAD soldered (1) 25.7 mW/°C 3121 mW 1998 mW 1623 mWQFN 24-pin exposed thermal pad 24.8 mW/°C 3106 mW 1988 mW 1615 mWsoldered (2)

(1) With PowerPAD soldered onto copper area on TI recommended printed circuit board (PCB); 2-oz. copper. For more information, seeapplication report PowerPAD Thermally-Enhanced Package (SLMA002) available for download at www.ti.com.

(2) The package thermal impedance is calculated in accordance with JESD51-5.

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 1. Input Timing

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 2. Output Timing




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WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

tH

WRT

CMD5

WRT

CMD0

DATA

217B

DATA

1BDATA

0B

DATA

2B

1 2 6tWL

222 223 224 1 2 3 4 5 6 7 8 9

t(2)

D6

tWH

Write Command (6 Bits)

DATA

217C

DATA

216C

DATA

215C

WRT

CMD4

Write Data (218 Bits)

DATA

0A

WRT

CMD5

WRT

CMD4

WRT

CMD0

WRT

CMD5

WRT

CMD1WRT

CMD0

DATA

0A

DATA

217B

DATA

2B

DATA

1B

DATA

0B

DATA

1A

DATA

0A

DATA

3B

DATA

2B

DATA

1B

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD5

WRT

CMD4

WRT

CMD2

DATA

217A

DATA

216A

DATA

1A

DATA

0A

DATA

216A

DATA

215A

DATA

0A

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217C

DATA

216C

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217C

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217B

DATA

216B

DATA

215B

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217B

DATA

216B

DATA

215B

DATA

214B

DATA

0B

WRT

CMD5

WRT

CMD4WRT

CMD3

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217B

DATA

216B

DATA

215B

DATA

217ADATA

216A

DATA

1A

DATA

0A

t /tR0 F0

tD0

SDTI

SDTO

SCKI

SCKO

tW(SCKO)

Latch Signal

(Internal)

224-Bit Shift Register

LSB (Internal)


LSB + 1 (Internal)


MSB 1 (Internal)-


MSB (Internal)

Latch Data

(Internal)Previous Data Latest Data (All GS Data are 0001h)

tD1

BLANK Bit in Data Latch

(Internal)

1

0

EXTGCK Bit in Data Latch

(Internal) 0

1

OUTTMG Bit in Data Latch

(Internal) 0

1

tD5

tD4

tD3

OUTR0-R3ON

OFF

tF1(V )OUTXnH

(V )(1)

OUTXnL

ON

OFF(V )OUTXnH

(V )(1)

OUTXnL

ON

OFF(V )OUTXnH

(V )(1)

OUTXnL

tR1

OUTG0-G3

OUTB0-B3

tSU

¼ ¼ ¼ ¼


(1) OUTXn ON-OFF timing depends on previous GS data in the 218-bit data latch.(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal

latch signal generation.

Figure 3. Data Write and OUTXn Switching Timing (OUTTMG = 1)




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WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

tH

WRT

CMD5

WRT

CMD0

DATA

217B

DATA

1BDATA

0B

DATA

2B

1 2 6tWL

222 223 224 1 2 3 4 5 6 7 8 9

t(2)

D6

tWH

Write Command (6 Bits)

DATA

217C

DATA

216C

DATA

215C

WRT

CMD4

Write Data (218 Bits)

DATA

0A

WRT

CMD5

WRT

CMD4

WRT

CMD0

WRT

CMD5

WRT

CMD1WRT

CMD0

DATA

0A

DATA

217B

DATA

2B

DATA

1B

DATA

0B

DATA

1A

DATA

0A

DATA

3B

DATA

2B

DATA

1B

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD5

WRT

CMD4

WRT

CMD2

DATA

217A

DATA

216A

DATA

1A

DATA

0A

DATA

216A

DATA

215A

DATA

0A

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217C

DATA

216C

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217C

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217B

DATA

216B

DATA

215B

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217B

DATA

216B

DATA

215B

DATA

214B

DATA

0B

WRT

CMD5

WRT

CMD4WRT

CMD3

WRT

CMD5

WRT

CMD4

WRT

CMD3

WRT

CMD2

WRT

CMD1

WRT

CMD0

DATA

217B

DATA

216B

DATA

215B

DATA

217ADATA

216A

DATA

1A

DATA

0A

t /tR0 F0

tD0

SDTI

SDTO

SCKI

SCKO

tW(SCKO)

Latch Signal

(Internal)


LSB (Internal)


LSB + 1 (Internal)


MSB 1 (Internal)-


MSB (Internal)

Latch Data

(Internal)Previous Data Latest Data (All GS Data are 0001h)

tD1


(Internal)

1

0

EXTGCK Bit in Data Latch

(Internal) 0

1

OUTTMG Bit in Data Latch

(Internal)

tD5

tD4

tD3

OUTR0-R3ON

OFF

tF1(V )OUTXnH

(V )(1)

OUTXnL

ON

OFF(V )OUTXnH

(V )(1)

OUTXnL

ON

OFF(V )OUTXnH

(V )(1)

OUTXnL

tR1

OUTG0-G3

OUTB0-B3

tSU

1

0

¼ ¼¼¼


(1) OUTXn ON-OFF timing depends on previous GS data in the 218-bit data latch.(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal

latch signal generation.

Figure 4. Data Write and OUTXn Switching Timing (OUTTMG = 0)




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3

2

1

0

1

2

3

-

-

-

0 60

Output Current (mA)

DI

(%)

OL

C

10 20

T = +25 C

VCC = 12 V

BCx = 7Fh

°A

30 5040

3

2

1

0

1

2

3

-

-

-

-40 100

Ambient Temperature ( C)°

DI

(%)

OLC

-20 0

I = 60 mA

VCC = 12 V

BCx = 7Fh

OLCMax

20 6040 80

70

60

50

40

30

20

10

00 3

Output Voltage (V)

Outp

ut C

urr

ent (m

A)

0.5 1

I = 60 mAOLCMax I = 50 mAOLCMax

I = 40 mAOLCMax

I = 30 mAOLCMax

I = 20 mAOLCMax

I = 10 mAOLCMax

T = +25 C, VCC = 12 V, BCx = 7Fh°A

I = 5 mAOLCMaxI = 2 mAOLCMax

1.5 2.52

64

63

62

61

60

59

58

57

56

55

540 3

Output Voltage (V)

Outp

ut C

urr

ent (m

A)

0.5 1

I = 60 mA

VCC = 12 V

BCx = 7Fh

OLCMax

1.5 2.52

T = 40 C- °A

T = +25 C°A

T = +85 C°A

100

10

1

0.10 70

I , Output Current (mA)OLC

R,

Re

fere

nce

Re

sis

tor

(k)

WIR

EF

10 20 30 5040 60

24.805

9.922

4.9613.307

2.481

1.984

1.654

1.417

1.240

1.102

0.992

0.902

0.827

4000

3000

2000

1000

0-40 100

Free-Air Temperature ( C)°

Pow

er

Dis

sip

ation R

ate

(m

W)

-20 0 20 6040 80

TLC5971PWP

TLC5971RGE


6.8 Typical CharacteristicsAt TA = 25°C and VCC = 24 V, unless otherwise noted.

Figure 6. Power Dissipation vs TemperatureFigure 5. Reference Resistor vs Output Current

Figure 7. Output Current vs Output Voltage Figure 8. Output Current vs Output Voltage

Figure 9. Constant-Current Error vs Output Current Figure 10. Constant-Current Error vs Ambient Temperature(Channel-to-Channel in Color Group) (Channel-to-Channel in Color Group)




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3.5

3.45

3.4

3.35

3.3

3.25

3.2

3.15

3.16 18

Supply Voltage, V (V)CC

Lin

ea

r R

eg

ula

tor

Ou

tpu

t V

olta

ge

, V

(V)

RE

G

8 10

T = +25 I = 60 mA,

BCx = 7Fh, GSx = FFFFh

EXTGCK = 0, DSPRPT = 1

A OLCMax°C,

12 14 16

I = 0 mAREG

I = 25 mA-REG

Time (20 ns/div)

CH1 (2 V/div)

CH2 (2 V/div)

CH3 (2 V/div)

CH4 (5 V/div)

CH3

(OUTB0)

C 2

(OUTG0)

H

CH1

(OUTR0)T = +25°C,

I = 60 mA, BCx = 7Fh,GSXn = 0001h, VLED = 5 V,

R = 68

VCC = 12 V

W

A

L

OLCMax

, OUTTMG = 1

CH4

(SCKI)

3.5

3.45

3.4

3.35

3.3

3.25

3.2

3.15

3.10 25

Linear Regulator Output Current, I (mA)REG

Lin

ea

r R

eg

ula

tor

Ou

tpu

t V

olta

ge

, V

(V)

RE

G

5 10

T = +25 I = 60 mA,

VCC = 12 V



A OLCMax°C,

15 20

30

25

20

15

10

5

0-40 100

Ambient Temperature ( C)°

I(m

A)

CC

-20 0

I = 60 mA, VCC = 12 V



SDTI = 10 MHz, SCKI = 20 MHz

OLCMax

20 6040 80

70

60

50

40

30

20

10

00 128

Brightness Control Data (dec)

Ou

tpu

t C

urr

en

t (m

A)

16 32

T = +25

VCC = 12 VA °C

48 8064 11296

I = 60 mAOLCMax

I = 30 mAOLCMax

I = 10 mAOLCMax

I = 2 mAOLCMax

30

25

20

15

10

5

00 60

Output Current (mA)

I(m

A)

CC

10 20

T = +25 C, VCC = 12 V



SDTI = 10 MHz, SCKI = 20 MHz

°A

30 5040


Typical Characteristics (continued)At TA = 25°C and VCC = 24 V, unless otherwise noted.

Figure 11. Global Brightness Control Linearity Figure 12. Supply Current vs Output Current

Figure 13. Supply Current vs Ambient Temperature Figure 14. Linear Regulator Output Voltage vs LinearRegulator Output Current

Figure 15. Linear Regulator Output Voltage vs Supply Figure 16. Constant-Current Output Voltage WaveformVoltage




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OUTXn(1)

GND

VREG

OUTPUT

GND

VREG

INPUT

GND

VREG

IREF

GND

VCC

RIREF

CVREG

VCC

VOUTXn

VOUTfix

OUTR0

OUTXn(1)

OUTB3

¼¼

VREG SDTO/SCKO

CL

(1)

GND

VCC

CVREG

VCC

VREG

OUTXn(1)

CL

(2)

RL

IREF

GND

VCC

RIREF

CVREG

VCCVLED


7 Parametric Measurement Information

7.1 Test Circuits

(1) X = R/G/B, n = 0-3.(2) CL includes measurement probe and stray

(1) CL includes measurement probe and straycapacitance.capacitance.

Figure 17. Rise/Fall Time Test Circuit for OUTXnFigure 18. Rise/Fall Time Test Circuit for

SDTO/SCKO

(1) X = R/G/B, n = 0-3.

Figure 19. Constant-Current Test Circuit for OUTXn

7.2 Pin Equivalent Input and Output Schematics

Figure 20. SDTI/SCKIFigure 21. SDTO/SCKO

(1) X = R/G/B, n = 0-3.

Figure 22. OUTR0 Through OUTB3




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Write

Command

Decode

6

218

SDTO

Refe encer

Current

Control

SCKI

IREF

GND


218-Bit Data Latch

GS Clock

Counter

SCKO

12-Channel Constant Sink Current Driver

with 7-Bit, 3-Grouped BC

3-Grouped Switching Delay

12

LSB MSB

0 223

LSB MSB

0 217

VCC

SDTI

OUTB3OUTG3OUTR3OUTB0OUTG0OUTR0

26

UVLO

21

Thermal

Detection

Clock

Timing

Adjust

3.3 V

REGVREG

Data

Latch

Control

reset

reset

Clock

Select

Internal

Oscillator16-Bit ES-PW Timing ControlM

intlat

1921 intlat

3

16

wrtena

EXTCLK

BLANK

TMGRST

BCX

GSX

BLANK

DSPRPT

OUTTMG

12

2


8 Detailed Description

8.1 OverviewThe TLC5971 is a 12-channel constant current sink driver. Each channel has an individually-adjustable, 65535-step, pulse width modulation (PWM) grayscale (GS) control. Each color has a 128-step brightness control (BC).GS data and BC data are input through a serial single-wire interface port.

The TLC5971 has a 60-mA current capability. The maximum current value of each channel is determined by theexternal resistor. The TLC5971 can work without external CLK signals since it can select to use internal oscillatoror external GS clock.

The TLC5971 is integrated with a linear regulator that can be used for higher VCC power-supply voltage from 6V to 17 V.

8.2 Functional Block Diagram




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12

3

GS Reference Clock(SCKI or Internal Oscillator)

OUTXn(GSDATA = FFFFh)

OUTn is forced offwhen BLANK is ‘1’.

Display period is repeatedby auto refresh function.

OFF

ON

OUTn is not turnedon until the nextBLANK changes

to ‘0’.

DSPRPT = 0(Auto Repeat Off)

BLANK Bitin Data Latch

(Internal)

DSPRPT Bitin Data Latch

(Internal)

2nd Display Period 3rd Display Period1st Display Period

1stDisplay Period

45

65533

6553465535

65536

12

3

45

65533

6553465535

65536

12

3

45

6

78

9

10 1 655342 65535

65536

12

DSPRPT = 1(Auto Repeat On)


8.3 Feature Description

8.3.1 Auto Display Repeat FunctionThis function repeats the total display period without a BLANK bit change, as long as the GS reference clock isavailable. This function can be enabled or disabled with DSPRPT (bit 214) in the data latch. When the DSPRPTbit is 1, this function is enabled and the entire display period repeats without a BLANK bit data change. When theDSPRPT bit is 0, this function is disabled and the entire display period executes only once after the BLANK bit isset to 0 or the internal latch pulse is generated when the display timing reset function is enabled. Figure 23shows the auto display repeat operation timing.

Figure 23. Auto Repeat Display Function

8.3.2 Display Timing Reset FunctionThis function allows the display timing to be initialized using the internal latch pulse, as shown in Figure 24. Thisfunction can be enabled or disabled by TMGRST (bit 215) in the data latch. When the TMGRST bit is 1, the GScounter is reset to 0 and all outputs are forced off when the internal latch pulse is generated. This function is thesame when the BLANK bit changes (such as from 0 to 1 and from 1 to 0). Therefore, the BLANK bit does notneed to be controlled from an external controller to restart the PWM control from the next GS reference clockrising edge. When this bit is 0, the GS counter is not reset and no output is forced off even if the internal latchpulse is generated. Figure 24 shows the display timing reset operation.




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SCKI

N 4-

OUTXn

OUTTMG Bit

in

(Internal)

Data Latch

1

TMGRST Bit

in Data Latch

(Internal)

0 = No BLANK.

1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.

BLANK Bit

in Data Latch

(Internal)

1 = Display timing reset function is enabled.

OFF

ON

EXTCLK Bit

in

(Internal)

Data Latch

1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.

Internal Latch Pulse

(Internal)

Period A

OFF

ONON

GS Counter

for PWM Control

(Internal)

0MM-1M-2M-3M 4- 1

When the TMGRST bit is ‘1’, the GS counter is

reset to ‘0’ at the internal latch pulse generation timing.

Also, OUTXn is forced off at the same time.

2 3

N 3- N 2- N 1- N

8x Period A8x or greater internal

clock period

(1.34 s, min).m

2 3 ¼


Feature Description (continued)

Figure 24. Display Timing Reset Function

8.3.3 Output Timing Select FunctionThis function selects the ON-OFF change timing of the constant-current outputs (OUTXn) set by OUTTMG (bit217) in the data latch. When this bit is 1, OUTXn are turned on or off at the rising edge of the selected GSreference clock. When this bit is 0, OUTXn are turned on or off at the falling edge of the selected clock.Electromagnetic interference (EMI) of the total system can be reduced using this bit setting. For example, whenthe odd number of devices in the system have this bit set to 0 and the even number of devices in the systemhave this bit set to 1, EMI is reduced because the devices change the OUTXn status at a deferent timing.Figure 25 and Figure 26 show the output switching timing when the OUTTMG bit is 1 and 0, respectively.




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tD3

tD5

tD4

SCKI

1

OUTR0-R3

OUTTMG Bit

in Data Latch

(Internal)

65534

EXTCLK Bit

in Data Latch

(Internal)

1

0

0 = OUTXn on-off state changes at the falling edge of the clock selected by the EXTCLK bit.

BLANK Bit

in Data Latch

(Internal)

1 = SCKI used for OUTXn on-off timing control.

OUTG0-G3

OUTB0-B3

OUTXn on-off state changes at the falling

edge of the clock selected by the EXTCLK bit.

OFF

OFF

OFF

ON

ON

ONtD3

tD5

tD4

2 655353 65536¼

tD3

tD5

tD4

SCKI

1

OUTR0-R3

OUTTMG Bit

in Data Latch

(Internal)

65534

EXTCLK Bit

in Data Latch

(Internal)

1

0

1 = OUTXn on-off state changes at the rising edge of the clock selected by the EXTCLK bit.

BLANK Bit

in Data Latch

(Internal)

1 = SCKI used for OUTXn on-off timing control.

OUTG0-G3

OUTB0-B3

OUTXn on-off state changes at the rising

edge of the clock selected by the EXTCLK bit.

OFF

OFF

OFF

ON

ON

ON

2 3 65535 65536¼

tD3

tD5

tD4


Feature Description (continued)

Figure 25. Output ON-OFF Timing With Four-Channel Grouped Delay (OUTTMG = 1)

Figure 26. Output ON-OFF Timing With Four-Channel Grouped Delay (OUTTMG = 0)




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R (k ) =WIREF

V (V)IREF

I (mA)OLCMax

´ 41


Feature Description (continued)8.3.4 Thermal ShutdownThe thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)exceeds the threshold (TTSD = 165°C, typical). When the junction temperature drops below (TTSD – THYS), theoutput control starts at the first GS clock in the next display period.

8.3.5 Noise ReductionLarge surge currents may flow through the IC and the board if all 12 outputs turn on simultaneously at the start ofeach GS cycle. These large current surges could induce detrimental noise and EMI into other circuits. TheTLC5971 turns on the outputs for each color group independently with a 25 ns (typical) rise time. The outputcurrent sinks are grouped into three groups. The first group that is turned on/off are OUTR0-3; the second groupthat is turned on/off are OUTG0-3; and the third group is OUTB0-3. However, the state of each output iscontrolled by the selected GS clock; see the Output Timing Select Function section.

8.4 Device Functional Modes

8.4.1 Maximum Constant Sink Current SettingThe maximum constant sink current value for each channel, IOLCMax, is programmed through a single resistor,RIREF, placed between IREF and GND. The desired value can be calculated with Equation 6:

where:VIREF = the internal reference voltage on the IREF pin (1.21 V, typically, when the the global brightnesscontrol data are at maximum),IOLCMax = 2 mA to 60 mA. (6)

IOLCMax is the maximum current for each output. Each output sinks the IOLCMax current when it is turned on andglobal brightness control data (BC) are set to the maximum value of 7Fh (127d).

RIREF must be between 0.82 kΩ and 24.8 kΩ to hold IOLCMax between 60 mA (typical) and 2 mA (typical).Otherwise, the output may be unstable. Output currents lower than 2 mA can be achieved by setting IOLCMax to 2mA or higher and then using global brightness control to lower the output current. The constant-current sinkvalues for specific external resistor values are shown in Figure 5 and Table 1.

Table 1. Maximum Constant-Current vs External Resistor ValueIOLCMax (mA) RIREF (kΩ, Typical)

60 0.82755 0.90250 0.99245 1.140 1.2435 1.4230 1.6525 1.9820 2.4815 3.3110 4.965 9.922 24.8




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t (ns) = t (ns) GSXnOUT_ON GSCLK ´

I I (mA)OUT OLCMax(mA) = ´

BCX

127d


8.5 Programming

8.5.1 Global Brightness Control (BC) Function (Sink Current Control)The TLC5971 has the capability to adjust all output currents of each color group (OUTR0-3, OUTG0-3, andOUTB0-3) to the same current value. This function is called global brightness (BC) control. The BC data areseven bits long, which allows each color group output current to be adjusted in 128 steps from 0% to 100% ofthe maximum output current, IOLCMax. The BC data are set through the serial interface. When the BC data arechanged, the output current is changed immediately.

When the IC is powered on, all outputs are forced off by BLANK (bit 213). BLANK initializes in the data latch butthe data in the 224-bit shift register and the 218-bit data latch are not set to a default value, except for theBLANK bit. Therefore, BC data must be written to the data latch when BLANK is set to 0.

Equation 7 determines each color group maximum output sink current:

Where:IOLCMax = the maximum channel current for each channel determined by RIREFBC = the global brightness control value in the data latch for the specific color group

(BCX = 0d to 127d, X = R/G/B) (7)

Table 2 summarizes the BC data value versus the output current ratio and set current value.

Table 2. BC Data vs Current Ratio and Set Current ValueOUTPUT CURRENT

BC DATA BC DATA RATIO TO IOLCMax 60 mA IOLCMax 2 mA IOLCMaxBC DATA (BINARY) (DECIMAL) (HEX) (%, TYPICAL) (mA, TYPICAL) (mA, TYPICAL)

000 0000 0 00 0 0 0000 0001 1 01 0.8 0.47 0.02000 0010 2 02 1.6 0.94 0.03

— — — — — —111 1101 125 7D 98.4 59.06 1.97111 1110 126 7E 99.2 59.53 1.98111 1111 127 7F 100 60 2

8.5.2 Grayscale (GS) Function (PWM Control)The TLC5971 can adjust the brightness of each output channel using the enhanced spectrum pulse widthmodulation (ES-PWM) control scheme. The PWM bit length for each output is 16 bits. The use of the 16-bitlength results in 65536 brightness steps from 0% to 100% brightness.

The PWM operation for all color groups is controlled by a 16-bit grayscale (GS) counter. The GS counterincrements on each rising or falling edge of the external or internal GS reference clock that is selected byOUTTMG (bit 217) and EXTGCK (bit 216) in the data latch. When the external GS clock is selected, the GScounter uses the SCKI clock as the grayscale clock. The GS counter is reset to 0000h and all outputs are forcedoff when BLANK (bit 213) is set to 1 in the data latch and the counter value is held at 0 while BLANK is 1, even ifthe GS reference clock is toggled in between.

Equation 8 calculates each output (OUTXn) total on-time (tOUT_ON):

Where:tGSCLK = one period of the selected GS reference clock

(internal clock = 100ns typical, external clock = the period of SCKI)GSXn = the programmed GS value for OUTXn (0d to 65535d) (8)




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Table 3 summarizes the GS data values versus the output total ON-time and duty cycle. When the IC is poweredup, BLANK (bit 213) is set to 1 to force all outputs off; however, the 224-bit shift register and the 218-bit datalatch are not set to default values. Therefore, the GS data must be written to the data latch when BLANK (bit213) is set to 0.

Table 3. Output Duty Cycle and Total On-Time versus GS DataGS DATA GS DATA

(DECIMAL) GS DATA (HEX) ON-TIME DUTY (%) (DECIMAL) GS DATA (HEX) ON-TIME DUTY (%)0 0 0 32768 8000 50.0011 1 0.002 32769 8001 50.0022 2 0.003 32770 8002 50.0043 3 0.005 32771 8003 50.005— — — — — —

8191 1FFF 12.499 40959 9FFF 62.4998192 2000 12.5 40960 A000 62.5018193 2001 12.502 40961 A001 62.502

— — — — — —16383 3FFF 24.999 49149 BFFF 74.99716384 4000 25 49150 C000 74.99816385 4001 25.002 49151 C001 75

— — — — — —24575 5FFF 37.499 57343 DFFF 87.524576 6000 37.501 57344 E000 87.50124577 6001 37.502 57345 E001 87.503

— — — — — —32765 7FFD 49.996 65533 FFFD 99.99732766 7FFE 49.998 65534 FFFE 99.99832767 7FFF 49.999 65535 FFFF 100

8.5.3 Enhanced Spectrum (ES) PWM ControlEnhanced spectrum (ES) PWM has the total display period divided into 128 display segments. The total displayperiod refers the period between the first grayscale clock input to the 65536th grayscale clock input after BLANK(bit 213) is set to 0. Each display period has 512 grayscale values, maximum. Each output on-time changesdepending on the grayscale data. Refer to Table 4 for sequence information and Figure 27 for timing information.

Table 4. ES-PWM Drive Turnon Time LengthGS DATA GS DATA

(DEC) (HEX) OUTn DRIVER OPERATION0 0000h Does not turn on1 0001h Turns on during one GS clock period in the 1st display period2 0002h Turns on during one GS clock period in the 1st and 65th display period3 0003h Turns on during one GS clock period in the 1st, 33rd, and 65th display period4 0004h Turns on during one GS clock period in the 1st, 33rd, 65th, and 97th display period5 0005h Turns on during one GS clock period in the 1st, 17th, 33rd, 65th, and 97th display period6 0006h Turns on during one GS clock period in the 1st, 17th, 33rd, 65th, 81st, and 97th display period

The number of display periods that OUTXn is turned on during one GS clock is incremented by the GSdata increasing in the following order. The order of display periods that the output turns on are:1, 65, 33, 97, 17, 81, 49, 113, 9, 73, 41, 105, 25, 89, 57, 121, 5, 69, 37, 101, 21, 85, 53, 117, 13, 77,45, 109, 29, 93, 61, 125, 3, 67, 35, 99, 19, 83, 51, 115, 11, 75, 43, 107, 27, 91, 59, 123, 7, 71, 39, 103,— — 23, 87, 55, 119, 15, 79, 47, 111, 31, 95, 63, 127, 2, 66, 34, 98, 18, 82, 50, 114, 10, 74, 42, 106, 26, 90,58, 122, 6, 70, 38, 102, 22, 86, 54, 118, 14, 78, 46, 110, 30, 94, 62, 126, 4, 68, 36, 100, 20, 84, 52,116, 12, 76, 44, 108, 28, 92, 60, 124, 8, 72, 40, 104, 24, 88, 56, 120, 16, 80, 48, 112, 32, 96, 64, and128.




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Table 4. ES-PWM Drive Turnon Time Length (continued)GS DATA GS DATA

(DEC) (HEX) OUTn DRIVER OPERATIONTurns on during one GS clock period in the 1st to 127th display period, but does not turn on in the127 007Fh 128th display period

128 0080h Turns on during one GS clock period in all display periods (1st to 128th)Turns on during two GS clock periods in the 1st display period and one GS clock period in the next129 0081h display periodThe number of display periods where OUTn is turned on for two GS clocks is incremented by the— — increased GS data similar to the previous case where the GS value is 1 trough 127Turns on during two GS clock periods in the 1st to 127th display period, but only turns on during one255 00FFh GS clock period in the 128th display period

256 0100h Turns on during two GS clock periods in all display periods (1st to 128th)Turns on during three GS clock periods in the 1st display period and two GS clock periods in the next257 0101h display periodDisplay periods with OUTn turned on is incremented by the increased GS datasimilar to 0101h— — operationTurns on during 511 GS clock periods in the 1st to 127th display period, but only turns on 510 GS65478 FEFFh clock periods in the 128th display period

65280 FF00h Turns on during 511 GS clock periods in all display periods (1st to 128th)Turns on during 512 GS clock periods in the 1st display period and 511 GS clock periods in the 2nd to65281 FF01h 128th display periods

— — —Turns on during 512 GS clock periods in the 1st to 63th and 65th to 127th display periods, and turns on65534 FFFEh 511 GS clock periods in the 64th and 128th display periodsTurns on during 512 GS clock periods in the 1st to 127th display period, but only turns on 511 GS65535 FFFFh clock periods in the 128th display period




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1 2

128th

Period

65th

Period

96th

Period

65026

65024511 513

3 512


(Internal)

ON

OFF

ON

OFF

ON

OFF

16382 16385

16383 16386

514 16384

49150 49153

49151 49154

65023

T =

GS Clock 511d´

1st

Period

97th

Period

127th

PeriodHigh Voltage Level

2nd

Period

32nd

Period

64th

Period

33rd

Period

32766 32769

32767 32770

16387 32768 4915232771

1st

Period

49155 6553665025

65534

65535

OUTXn

(GS Data = 0000h)

OUTXn

(GS Data = 0001h)

OUTXn

(GS Data = 0002h)

ON

OFFOUTXn

(GS Data = 0003h)

ON

OFF

ON

OFF

OUTXn

(GS Data = 0004h)

ON

OFF

OUTXn

(GS Data = 0041h)

OUTXn

(GS Data = 0080h)

ON

OFFOUTXn

(GS Data = 0081h)

ON

OFF

ON

OFF

OUTXn

(GS Data = 0082h)

OUTXn

(GS Data = FF80h)

ON

OFF

ON

OFF

OUTXn

(GS Data = FF81h)

OUTXn

(GS Data = FFFEh)

ON

OFFOUTXn

(GS Data = FFFFh)

GS Reference Clock

(Internal)

When the DSPRPT Bit is ‘1’

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´T = GS Clock 1d´

T = GS Clock 2d´ T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´

T = GS Clock 1d´


T = GS Clock 2d´

T = GS Clock 1d´


T = GSCLK 512d´

T =

GS Clock 512d´

T =

GS Clock 511d´

T =

T =

GS Clock 511d´

T = GS Clock 511d in 2nd to 128th Periods´


T = GS Clock 512d in 2nd to 63rd and 65th to 127th Periods,´

T = GS Clock 511d in 64th Period´


T = GS Clock 1d´

T = GS Clock 1d´

Low Voltage Level

T = GS Clock 1d´

GS Clock 512d´

¼¼

¼¼

¼¼

¼¼

¼ ¼ ¼ ¼

¼ ¼ ¼ ¼

¼

¼ ¼


Figure 27. ES-PWM Operation




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6-Bit Write

Command

Decoder

SDTOSCKI

SDTI

To GS timing control circu t.iTo the three groups of 7-bit BC,

PWM timing control, GS clock counter,

and clock select circuit.


LSBMSB

Write

Command

Bit 5

218

Write

Data

Bit 3

218-Bit Data Latch

0123215216217218223

LSB

0123

OUTR0

Bit 3

OUT

TMG

215217

MSB

19226

214

6

Write Command = 25h (100101b)

Inte nalr

Latch Pulse

The internal latch pulse is generated

after eight periods between the last

2 SCKI rising edges with no input.

216 214

EXT

GCK

TMG

RST

DSP

RPT

¼ ¼

¼

Write

Command

Bit 0

Write

Data

Bit 217

Write

Data

Bit 216

Write

Data

Bit 215

Write

Data

Bit 214

Write

Data

Bit 2

Write

Data

Bit 1

Write

Data

Bit 0

OUTR0

Bit 2

OUTR0

Bit 1

OUTR0

Bit 0


8.5.4 Register and Data Latch ConfigurationThe TLC5971 has a 224-bit shift register and a 218-bit data latch that set grayscale (GS) data, global brightnesscontrol (BC), and function control (FC) data into the device. When the internal latch pulse is generated and thedata of the six MSBs in the shift register are 25h, the 218 following data bits in the shift register are copied intothe 218-bit data latch. If the data of the six MSBs is not 25h, the 218 data bits are not copied into the 218-bit datalatch. The data in the data latch are used for GS, BC, and FC functions. Figure 28 shows the shift register andthe data latch configuration.

Figure 28. Common Shift Register and Control Data Latch Configuration

8.5.4.1 224-Bit Shift RegisterThe 224-bit shift register is used to input data from the SDTI pin with the SCKI clock into the TLC5971. Theshifted data in this register is used for GS, BC, and FC. The six MSBs are used for the write command. The LSBof the register is connected to the SDTI pin and the MSB is connected to the SDTO pin. On each SCKI risingedge, the data on SDTI are shifted into the register LSB and all 224 bits are shifted towards the MSB. Theregister MSB is always connected to SDTO. When the device is powered up, the data in the 224-bit shift registeris not set to any default value.

8.5.4.2 218-Bit Data LatchThe 218-bit data latch is used to latch the GS, BC, and FC data. The 218 LSBs in the 244-bit shift register arecopied to the data latch when the internal latch pulse is generated with the 6-bit write command, 25h (100101b).When the device is powered up, the data in the latch are not reset except for BLANK (bit 213) which is set to 1 toforce all outputs off. Therefore, GS, BC, and FC data must be set to the proper values before BLANK is set to 0.The 218-bit data latch configuration is shown in Figure 29 and the data bit assignment is shown in Table 5.




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218-Bit Data Latch

21

OUTTMG

1 =

Rising Edge

MSB

217

¼EXTCLK

1 =

External

216

TMGRST

1 =

Reset

215

DSPRPT

1 =

Repeat

214

BLANK

1 =

Blank

213

BC Data

Bits 6-0

for BLUE

212-206

BC Data

Bits 6-0

for GREEN

205-199

BC Data

Bits 6-0

for RED

198-192

OUTB3

Bit 15

191

OUTB3

Bit 0

176

OUTG0

Bit 0

16

OUTR0

Bit 15

15

OUTG0

Bit 15

31

¼ OUTR0

Bit 0¼

LSB

0

218

From LSB-side of 224-bit shift register.

5 192

To function control (FC) circuit. To global brightness control (BC) circuit. To grayscale timing control (GS) circuit.

Function Control Data (5 Bits) BC Data for OUTRn/Gn/Bn

(7 Bits 3 = 21 Bits)´

¼

GS Data for OUTG0

(16 Bits)

GS Data for OUTB3

(16 Bits)

GS Data for OUTR0

(16 Bits)


Figure 29. 218-Bit Data Latch Configuration

Table 5. Data Latch Bit AssignmentBIT NUMBER BIT NAME CONTROLLED CHANNEL/FUNCTIONS

15-0 GSR0 GS data bits 15 to 0 for OUTR031-16 GSG0 GS data bits 15 to 0 for OUTG047-32 GSB0 GS data bits 15 to 0 for OUTB063-48 GSR1 GS data bits 15 to 0 for OUTR179-64 GSG1 GS data bits 15 to 0 for OUTG195-80 GSB1 GS data bits 15 to 0 for OUTB1

111-96 GSR2 GS data bits 15 to 0 for OUTR2127-112 GSG2 GS data bits 15 to 0 for OUTG2143-128 GSB2 GS data bits 15 to 0 for OUTB2159-144 GSR3 GS data bits 15 to 0 for OUTR3175-160 GSG3 GS data bits 15 to 0 for OUTG3191-176 GSB3 GS data bits 15 to 0 for OUTB3198-192 BCR BC data bits 6 to 0 for OUTR0-3205-199 BCG BC data bits 6 to 0 for OUTG0-3212-206 BCB BC data bits 6 to 0 for OUTB0-3

Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank).When this bit is 0, all constant-current outputs (OUTR0-OUTB3) are controlled by the GS PWM timing213 BLANK controller. When this bit is 1, all constant-current outputs are forced off. The GS counter is reset to 0,and the GS PWM timing controller is initialized. When the IC is powered on, this bit is set to 1.Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled).When this bit is 0, the auto repeat function is disabled. Each constant-current output is only turned on

214 DSPRPT once, according the GS data after BLANK is set to 0 or after the internal latch pulse is generated withthe TMGRST bit set to 1. When this bit is 1, each output turns on and off according to the GS dataevery 65536 GS reference clocks.Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled).When this bit is 1, the GS counter is reset to 0 and all constant-current outputs are forced off when theinternal latch pulse is generated for data latching. This function is the same when BLANK is set to 0.215 TMGRST Therefore, BLANK does not need to be controlled by an external controller when this mode is enabled.When this bit is 0, the GS counter is not reset and no output is forced off even if the internal latch pulseis generated.GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock).

216 EXTGCK When this bit is 1, PWM timing refers to the SCKI clock. When this bit is 0, PWM timing refers to theinternal oscillator clock.GS reference clock edge select bit for OUTXn on-off timing control in FC data (0 = falling edge, 1 =rising edge).217 OUTTMG When this bit is 1, OUTXn are turned on or off at the rising edge of the selected GS reference clock.When this bit is 0, OUTXn are turned on or off at the falling edge of the selected clock.




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218-bit data are copied from shift register

when the internal latch is generated.

N 3-

SCKI

1

Latch Pulse

(Internal)

Period A

The internal latch pulse is generated when the SCKI rising edge is not input during 8 times of

Period A if the 6-bit data of the MSB-side in the 244-bit shift register is the command code .25h

The next SCKI clock should start after 8 or more

clock periods (1.34 s, min) of the internal clock

from the internal latch pulse generation timing.

m

224-Bit Shift

Register Data

(Internal)

218-Bit

Data Latch

(Internal)

Write command 25h + 218-bit data.

N 2- N 1- N2 3 4 ¼


8.5.5 Internal Latch Pulse Generation TimingThe internal latch pulse is generated when the SCKI rising edge does not change for 8x the period between thelast SCKI rising edge and the second to last SCKI rising edge if the data of the six MSBs in the 244-bit shiftregister are the command code 25h. The generation timing changes as a result of the SCKI frequency with thetime range between 16384 times the internal oscillator period (2.74 ms), maximum, and 8x the internal oscillatorperiod (666 ns), minimum. Figure 30 shows the internal latch pulse generation timing.

Figure 30. Data Latch Pulse Generation Timing




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GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

1 Fm

VCC

GND

PowerSupply

(6 V to 17 V)

DATA

CLK

GND

Controller(1)

¼ ¼

GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

1 Fm

¼ ¼

OptionalDevice DeviceOptional


9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe device is a 12-channel, constant sink current, LED driver. This device can be connected in series to drivemany LED lamps with only a few controller ports. Functional control data and PWM control data can be writtenfrom the SDI and SCK input terminal. The PWM timing reference clock can be chosen from the internaloscillation or external SCK signal.

9.2 Typical Application

The output voltage range is from 0 V to 3.3 V.NOTE: The number of LEDs in series changes, depending on the VCC voltage.

Figure 31. Typical Application Circuit Example (Internal Linear Regulator Using VCC = 6 V to 17 V)

9.2.1 Design RequirementsFor this design example, use Table 6 as the input parameters.

Table 6. Design ParametersDESIGN PARAMETER EXAMPLE VALUE

VCC Input Voltage Range 3 V to 5.5 VLED Lamp (VLED) Input Voltage Range Maximum 17 V

SIN, SCLK, LAT and GSCLK Voltage Range Low Level = GND, High Level = VCC

9.2.2 Detailed Design Procedure

9.2.2.1 Define Basic ParametersTo begin the design process, a few parameters must be decided as following"• Maximum output constant-current value for each color LED lamp• Maximum LED forward voltage (Vf) and maximum VLED• Total LEDs and Cascaded IC Number




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VCC

SDTI

SCKI

IREF

GND

SDTO

SCKO

VREF

1st

TLC5971

VLED

DATA

CLK

GND

Controller

¼

3.3 V

VCC

SDTI

SCKI

IREF

GND

SDTO

SCKO

VREF

2nd

TLC5971

¼

VCC

SDTI

SCKI

IREF

GND

SDTO

SCKO

VREF

N 1st-

TLC5971

¼

VCC

SDTI

SCKI

IREF

GND

SDTO

SCKO

VREF

Nth

TLC5971

¼

MSB

Write

Command

(6 bits, 25h)

Function

Control

(5 bits)

BC for

BLUE

(7 bits)

BC for

GREEN

(7 bits)

BC for

RED

(7 Bits)

GS for

OUTB3

(16 Bits)

GS for

OUTG3

(16 Bits)

GS for

OUTR3

(16 Bits)

16 Bits

6´

GS for

OUTB0

(16 Bits)

GS for

OUTG0

(16 Bits)

GS for

OUTR0

(16 Bits)

LSB


9.2.2.2 Data Input Sequence224-bit data packets are sent through single-wire interface for the PWM control of three output channels. Selectthe BC data, FC data and write the GS data to the register following the signal timing.

9.2.2.3 How to Control the TLC5971To set each function mode, BC color, GS output, 6-bit write command, 5-bit FC data, 21-bit BC data for eachcolor group, and 192-bit GS data for OUTXn, a total number of 224 bits must be written into the device.Figure 32 shows the 224-bit data packet configuration.

When N units of the TLC5971 are cascaded (as shown in Figure 33), N × 224 bits must be written from thecontroller into the first device to control all devices. The number of cascaded devices is not limited as long as theproper voltage is supplied to the device at VCC. The packets for all devices must be written again whenever thedata in one packet is changed.

Figure 32. 224-Bit Data Packet Configuration

Figure 33. Cascading Connection of N TLC5971 Units

9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode

When the EXTCLK bit is 0, the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for illumination applications that change the display image atlow frequencies. The data and clock timing is shown in Figure 3 and Figure 34. A writing procedure for thefunction setting and display control follows:1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The

first six bits of the 224-bit data packet are used as the write command. The write command must be 25h(100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch.The EXTCLK bit must be set to 0 for the internal oscillator mode. Also, the DSPRPT bit should be set to 1 torepeat the PWM timing control and BLANK set to 0 to start the PWM control.

3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 ×

N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the lastSCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister arecopied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.




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for

N-2’th

Shift Data From

Controller (SDTI)

Shift Clock From

Controller (SCKI)

OUTXn

VLED Power

224 Shift Clocks

224-Bit Packet

for Nth TLC5971

MSB

224 Shift Clocks

224-Bit Packet

for N 1st TLC5971-

for

3’rd

224-Bit Packet

for 2nd TLC5971

224-Bit Packet

for 1st TLC5971

Next

Data

Next

Shift Clock

PWM Control Start

or data updated

The time that generates the internal latch pulse is 8x the period between the last

SCLK rising edge and the second to last SCLK rising edge. The time changes

depending on the period of the shift clock within the range of 2.74 ms to 666 ns.

The next shift clock should start after 1.34 s

or more from the internal latch pulse generation timing.

m

Latch Pulse

(Internal)

MSB

MSB

MSB

MSB

MSB

LSB

LSB

LSB

LSB

LSB

224 Shift Clocks 224 Shift Clocks


Figure 34. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)

9.2.2.3.2 Data Write and PWM Control with External Grayscale Clock Mode

When the EXTCLK bit is 1, the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for video image applications that change the display image withhigh frequencies or for certain display applications that must synchronize all TLC5971s. The data and clocktiming are shown in Figure 3 and Figure 35. A writing procedure for the display data and display timing controlfollows:1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.2. Write the 224-bit data packet MSB-first for the Nth TLC5971 using the SDTI and SCKI signals. The first six

bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b);otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLKbit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that thePWM control is not repeated, the TMGRST bit should be set to 1 to reset the PWM control timing at theinternal latch pulse generation, and BLANK must be set to 0 to start the PWM control.

3. Write the 224-bit data for the (N – 1) TLC5971 without delay after step 2.4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is 224 × N.

After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKIrising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister arecopied to the 218-bit data latch in all devices.

5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34 µs or more from step 4.The OUTXn are turned on when the output GS data are not 0000h.

6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronizedwith the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.

7. Repeat step 2 to step 6 for the next display period.




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for

2nd

for

N 1st-

Shift Data From

Controller (SDTI)

Shift Clock From

Controller (SCKI)

OUTXn

VLED Power

224 Shift Clocks

224-Bit Packet

for Nth TLC5971

65536 Shift Clocks as GS Clock

224-Bit Packet

for 1st TLC5971

OUTXn is controlled via the PWM

synchronized with SCKI.

The time that generates the internal latch pulse is 8x the period between the last

SCLK rising edge and the second to last SCLK rising edge. The time changes

depending on the period of the shift clock within the range of 2.74 ms to 666 ns.

The next shift clock should start after 1.34 s

or more from the internal latch pulse generation timing.

m

Low

Latch Pulse

(Internal)

224-Bit Packet

for Nth TLC5971

MSB LSB

MSB LSB

MSB LSB MSB

224 Shift Clocks224 Shift

Clocks


Figure 35. Data Packet and Display Start/Update Timing 2 (External Clock Mode)

There is another control procedure that is recommended for a long chain of cascaded devices. The data andclock timings are shown in Figure 3 and Figure 36. When 256 TLC5971 units are cascaded, use the followingprocedure:1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The

EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 sothat the PWM control does not repeat, the TMGRST bit should be set to 1 to reset the PWM control timingwith the internal latch pulse, and BLANK must be set to 0 to start the PWM control.

3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256).After all device data are written, stop the SCKI signal at a high or low level for eight or more periods betweenthe last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shiftresister are copied to the 218-bit data latch in all devices.

4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34 µs or more from step 3 (or step7). These 8192 clock periods are used for the OUTXn PWM control.

5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKIclock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock andone display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used forPWM control and, at the same time, to write data into the shift registers of all cascaded parts.

6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge andthe second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.

7. Repeat step 4 to step 6 for the next display periods.




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Timing clock for 1st display and

2nd display data write.

Shift Clock

for 2nd Display

for

2nd

LSB

for

255th

Shift Data From

Controller (SDTI)

Shift Clock From

Controller (SCKI)

OUTXn

VLED Power

224 Shift Clocks

224-Bit Packet for

256th TLC5971

8192

Shift Clocks

MSB

224-Bit Packet

for 1st TLC5971

OUTXn is controlled via the PWM synchronized

with SCKI for 1st displayperiod.

The time is 8 periods between the last SCLK rising edge and the second to last SCLK rising edge.

The wait time changes between 2.74 ms and 666 ns, depending on the period of the shift clock.

The next shift clock should start after 1.34 s or more from the internal latch pulse generation timing.m

256 224-Bit Packet for

256th TLC5971

´

Low

57344 (256 224)

Shift Clocks

´

Latch Pulse

(Internal)

Low

OFF OFF2nd Display

Period

Timing clock for 1st display.MSB LSB MSB LSB

224 Shift Clocks

224 256 = 57344 Clocks´ 65536 Clocks 65536 Clocks


Figure 36. Data Packet and Display Start/Update Timing 3(External Clock Mode With 256 Cascaded Devices)

9.2.3 Application Curve

Figure 37. Output Waveform With GS Data Latch Input




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GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

PowerSupply

(3 V to 5.5 V)

DATA

CLK

GND

Controller(1)

¼

GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

¼

OptionalDevice Device

VLED

GND

PowerSupply(15 V)

VCC

GND

¼

Optional

¼

VCC

GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

VCC

GND

PowerSupply

(3 V to 5.5 V)

DATA

CLK

GND

Controller(1)

¼

GND

VREG

IREF

SDTI

SCKI

VCC

OUTR0

OUTG0

OUTG3

OUTB3

SDTO

SCKO

¼ ¼

OptionalDevice Device

¼

Optional

VCC


9.3 System Examples

(1) The output operating voltage range is from 0 V to VCC.

Figure 38. Typical Application Circuit Example (Direct Power Supplying VCC = 3 V to 5.5 V)

(1) The output operating voltage range is from 0 V to VCC.

Figure 39. Typical Application Circuit Example(Direct Power Supplying VCC = 3 V to 5.5 V, VLED = 15 V)




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10 Power Supply RecommendationsThe VCC power supply voltage should be decoupled by placing a 0.1-uF ceramic capacitor close to VCC pin andGND plane. Depending on panel size, several electrolytic capacitors must be placed on board equally distributedto get a well regulated LED supply voltage (VLED). VLED voltage ripple should be less than 5% of its nominalvalue.

11 Layout

11.1 Layout Guidelines1. Place the decoupling capacitor near the VCC pin and GND plane.2. Route the GND pattern as widely as possible for large GND currents.3. Connecting wire between the chained ICs should be as short as possible to reduce wire inductance.

11.2 Layout Example

Figure 40. Layout Example




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12 Device and Documentation Support

12.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.2 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TLC5971PWP ACTIVE HTSSOP PWP 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971

TLC5971PWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971

TLC5971RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971

TLC5971RGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TLC5971PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

TLC5971RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TLC5971RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC5971PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0

TLC5971RGER VQFN RGE 24 3000 853.0 449.0 35.0

TLC5971RGET VQFN RGE 24 250 210.0 185.0 35.0




TUBE


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

TLC5971PWP PWP HTSSOP 20 70 530 10.2 3600 3.5




GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.

RGE 24 VQFN - 1 mm max heightPLASTIC QUAD FLATPACK - NO LEAD

4204104/H

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PACKAGE OUTLINE

www.ti.com

4219016 / A 08/2017

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RGE0024H

A

0.08 C

0.1 C A B

0.05 C

B

SYMM

SYMM

4.1

3.9

4.1

3.9

PIN 1 INDEX AREA

1 MAX

0.05

0.00

SEATING PLANE

C

2X 2.5

2.7±0.1

2X

2.5

20X 0.5

1

6

7

12

13

18

19

24

24X

0.30

0.18

24X

0.48

0.28

(0.2) TYP

PIN 1 ID

(OPTIONAL)

25

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

EXAMPLE BOARD LAYOUT

4219016 / A 08/2017

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RGE0024H


SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

2X

(1.1)

2X(1.1)

(3.825)

(3.825)

( 2.7)

1

6

7 12

13

18

1924

25

24X (0.58)

24X (0.24)

20X (0.5)

(R0.05)

(Ø0.2) VIA

TYP

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

EXAMPLE STENCIL DESIGN

4219016 / A 08/2017

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RGE0024H


SYMM

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

(3.825)

(3.825)

(0.694)

TYP

(0.694)

TYP

4X ( 1.188)

1

6

712

13

18

1924

24X (0.24)

24X (0.58)

20X (0.5)

(R0.05) TYP

METAL

TYP

25

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http://www.ti.com/lit/SLMA002

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PACKAGE OUTLINE

C

0.25

GAGE PLANE

0.75

0.50

(1)

A

NOTE 3

6.6

6.4

B

4.5

4.3

6.6

6.2

TYP

18X 0.65

20X

0.30

0.19

2X

5.85

(0.15) TYP

0 - 8

0.15

0.05

2.75

1.98

3.43

2.65

2X 0.95 MAX

NOTE 5

1.2 MAX

4X 0.23 MAX

NOTE 5

PowerPAD TSSOP - 1.2 mm max heightPWP0020U

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

PowerPAD is a trademark of Texas Instruments.

TM

1

20

0.1 C A B

11

10

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.200

THERMAL

PAD

21

4224609/A 09/2018

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EXAMPLE BOARD LAYOUT

(5.8)

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

20X (1.5)

20X (0.45)

18X (0.65)

(3.4)

NOTE 9

(6.5)

NOTE 9

(2.75)

(3.43)

( 0.2) TYP

VIA

(1.1) TYP

(1.3)

TYP



EXPOSE METAL

SYMM

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

1

1011

20

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

21

TM

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

METALSOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-20

SOLDER MASK

DEFINED

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED METAL

4224609/A 09/2018

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EXAMPLE STENCIL DESIGN

20X (1.5)

20X (0.45)

(2.75)

(3.43)

BASED ON

0.125 THICK

STENCIL

18X (0.65)

(R0.05) TYP

(5.8)



NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

TM

SYMM

SYMM

1

10 11

20

BASED ON

0.125 THICK

STENCIL

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

21

4224609/A 09/2018

2.32 X 2.900.175

2.51 X 3.130.15

2.75 X 3.43 (SHOWN)0.125

3.07 X 3.830.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

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