Titre :

Développement de circuits logiques programmables résistants aux aléas

logiques en technologie CMOS submicrométrique

Titre anglais :

Development of Single Event Upset hardened programmable logic devices in

deep submicron CMOSSandro BonaciniSandro Bonacini

OutlineOutline Motivation and objectivesMotivation and objectives CERN and the LHCCERN and the LHC

Radiation environment at the LHCRadiation environment at the LHC Radiation effects on ICsRadiation effects on ICs

Total Ionizing Dose (TID) effects and Total Ionizing Dose (TID) effects and hardeninghardening

Single Event Effects (SEE)Single Event Effects (SEE) Study on SEU hardening techniquesStudy on SEU hardening techniques

Design of SEU-robust registersDesign of SEU-robust registers Experimental resultsExperimental results

Design of a radiation-tolerant Design of a radiation-tolerant FPGAFPGA Study on FPGA architecturesStudy on FPGA architectures Experimental resultsExperimental results

Design of a radiation-tolerant Design of a radiation-tolerant PLDPLD

MotivationMotivation Experimental High-Energy Physics (HEP) would Experimental High-Energy Physics (HEP) would

benefit from the availability of radiation-hard benefit from the availability of radiation-hard programmable logicprogrammable logic FPGAsFPGAs

Fast design development Flexibility (changing requirements, failure recovery, …) Possible use as IP-core

PLDs Glue logic, simple state machines Hard fixes in the late stages of a project

Commercial devices do not attain radiation levels of inner sub-detectors in LHC’s experiments

ObjectivesObjectives Programmable logic componentsProgrammable logic components

TID-tolerant to experiment upgrades inner tracker TID-tolerant to experiment upgrades inner tracker levelslevels

Built-in SEU hardnessBuilt-in SEU hardness Configuration bank and user registers…Configuration bank and user registers… User can avoid utilization of SEU hardening techniques at User can avoid utilization of SEU hardening techniques at

HDL level and/or reconfiguration techniques for program HDL level and/or reconfiguration techniques for program restorationrestoration

FPGAFPGA SRAM-based, ~25k gates, 256 I/OsSRAM-based, ~25k gates, 256 I/Os in 0.13μm CMOSin 0.13μm CMOS

PLD PLD Fuse-based, 10 inputs, 8 bidirectionalFuse-based, 10 inputs, 8 bidirectional in 0.25μm CMOSin 0.25μm CMOS

CERN is a particle CERN is a particle physics research physics research laboratory run by laboratory run by 20 member states20 member states

Currently a new Currently a new accelerator is accelerator is being assembled being assembled at CERNat CERN the Large Hadron the Large Hadron

ColliderCollider … … whose target is whose target is

to accelerate to accelerate protons to an protons to an energy of 7 TeVenergy of 7 TeV

CERN and theCERN and theLarge Hadron Collider Large Hadron Collider

(LHC)(LHC)

Experiments at LHCExperiments at LHC LHC’s beam LHC’s beam

pipe runs on a pipe runs on a 27-km-long 27-km-long underground underground tunneltunnel

Four Four experiments are experiments are based on the based on the LHC and are LHC and are currently being currently being builtbuilt

The experiments The experiments are located are located around the around the proton-proton proton-proton collision pointscollision points

Grenoble

Example of an LHC Example of an LHC experiment:experiment:

the Compact Muon the Compact Muon SolenoidSolenoid Experiments at Experiments at

the LHC have a the LHC have a considerable considerable sizesize Several Several

stories high, stories high, tens of tens of meters longmeters long

Composed by Composed by several sub-several sub-detectorsdetectors

Cover ~all Cover ~all directions directions from from interaction interaction pointpoint

People standing in People standing in superconducting superconducting

coil at coil at 100K100K

Fluence of Fluence of hadrons in CMS hadrons in CMS

inner sub-inner sub-detectorsdetectors

At peak luminosity, up to 10At peak luminosity, up to 1015 15 cmcm-2 -2

hadrons in 10 years of operationhadrons in 10 years of operation Simulations performed with FLUKASimulations performed with FLUKA

7.3

m

>3.2·1014

>1014

>1015

>3.2·1013

>1013

>3.2·1012

>1012

>3.2·1011

>1011

3.2·1014>

1014>

1015>

3.2·1013>

1013>

3.2·1012>

1012>

3.2·1011>

1011>

Fluence of neutrons

(>100keV) and charged hadrons

in cm–2

2.6

m5.2 m

Total Ionizing DoseTotal Ionizing Dosein CMS inner sub-in CMS inner sub-

detectorsdetectors

Up to 35 Mrad in 10 years of Up to 35 Mrad in 10 years of operation at peak luminosityoperation at peak luminosity Dose rate up to 1.5 krad/hDose rate up to 1.5 krad/h

>107

>106

>105

>104

>103

>102

107>

106>

105>

104>

103>

102>

Radiation total dose in rad

7.3

m

2.6

m5.2 m

Total dose effects on MOS Total dose effects on MOS transistors and solutionstransistors and solutions

In order avoid these conductive paths In order avoid these conductive paths it is possible to use (in nMOS it is possible to use (in nMOS transistors)transistors) Enclosed Layout TransistorsEnclosed Layout Transistors p+ guard ringsp+ guard rings

TID inducesTID induces Threshold voltage shiftThreshold voltage shift

Minor issue in deep submicron Minor issue in deep submicron devicesdevices

Leakage current increase in nMOSLeakage current increase in nMOS due to the accumulation of positive due to the accumulation of positive

charge in the field oxide which charge in the field oxide which induces conductive paths in the induces conductive paths in the substratesubstrate

Drain

Source

Gate

Drain

Source

Gate

Si

SiO2

SiO2

Si

SiO2

SiO2

Thick

oxide

Thin

oxide

LOCOS

STI

ELT vs linear ELT vs linear transistorstransistors

-80

-60

-40

-20

0

20

40

60

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08

Total Dose [rad(SiO2 )]

Vth

[m

V]

NMOS, L=0.28

PMOS, L=0.28

Annealing

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

10 100 1000 10000

Dose ( krad( SiO2))

Lea

k (

A)

0.25µm

ELT

Standard

0.25 micron 0.13 micron

Leakage current

Threshold voltage

shift

Total Ionizing Dose Total Ionizing Dose hardeninghardening

Design practices for TID hardeningDesign practices for TID hardening

0.25μm CMOS technology0.25μm CMOS technology Enclosed Layout TransistorsEnclosed Layout Transistors Guard-ringsGuard-rings

0.13μm CMOS technology0.13μm CMOS technology Sufficiently TID-hard for digital logic without ELTSufficiently TID-hard for digital logic without ELT

Faccio and Cervelli, “Radiation-induced edge effects in deep submicron CMOS transistors”,IEEE Transactions on Nuclear Science, vol. 52, December 2005

Use of linear transistors with W>0.30μmUse of linear transistors with W>0.30μm

O.25 micronO.25 micron

O.13 micronO.13 micron

Single-Event Effects Single-Event Effects (SEEs)(SEEs)

Effects due to a single ionizing particle Effects due to a single ionizing particle crossing the devicecrossing the device Single-Event LatchupSingle-Event Latchup

destructive effect which can occur because of the destructive effect which can occur because of the parasitic thyristor formed by the junction structure parasitic thyristor formed by the junction structure present in CMOS ICspresent in CMOS ICs

Deep submicron technologies are becoming less susceptible Deep submicron technologies are becoming less susceptible (low supply voltage, highly doped substrate, trench (low supply voltage, highly doped substrate, trench isolation between wells, …)isolation between wells, …)

Single-Event UpsetSingle-Event Upset Non-destructive effect which alters the data stored in Non-destructive effect which alters the data stored in

a memory circuit by deposition of charge in the a memory circuit by deposition of charge in the circuit nodescircuit nodes

… … gate rupture, snapback, burnout …gate rupture, snapback, burnout …

Single-Event Upsets Single-Event Upsets (SEUs)(SEUs)

An ionizing particle creates An ionizing particle creates electron-hole pairs which are electron-hole pairs which are collected by the electric field of collected by the electric field of junctionsjunctions The voltage on the node The voltage on the node

connected to the junction changesconnected to the junction changes

In a typical SRAM cell if 1 In a typical SRAM cell if 1 of the 2 memory nodes is of the 2 memory nodes is brought above/below Vdd/2 brought above/below Vdd/2 the stored value is the stored value is corruptedcorrupted

p

n+n+

Incident particle

Gate

Drain

Electric field region

MNBMN

i SE

U

Single-Event Transients Single-Event Transients (SETs)(SETs)

SEUs can also be generated indirectly by a SEUs can also be generated indirectly by a particle hit in the combinatorial logic which particle hit in the combinatorial logic which creates a transient pulse propagating through creates a transient pulse propagating through the datapaththe datapath If the pulse reaches the FF during the closing edge If the pulse reaches the FF during the closing edge

of the clock the data is corruptedof the clock the data is corrupted SET-induced-SEU rate is proportional to clock SET-induced-SEU rate is proportional to clock

frequencyfrequency

D-ff

D QD0 Q

CK

D1 D2 D3 D4 D5

1

Study on SEU Study on SEU hardeninghardening

Several ways to protect memories against Several ways to protect memories against SEUsSEUs System-level techniquesSystem-level techniques

Triple Module Redundancy (TMR)Triple Module Redundancy (TMR) Error Correction Coding (ECC)Error Correction Coding (ECC)

Circuit-level techniquesCircuit-level techniques Dual-Interlocked CellDual-Interlocked Cell Whitaker cellWhitaker cell Dooley, Rocket, SERT, …Dooley, Rocket, SERT, …

Device-level techniquesDevice-level techniques Capacitance increase, threshold voltage control, …Capacitance increase, threshold voltage control, …

Hamming EncodingHamming Encoding Tolerates 1 error over Tolerates 1 error over nn bit bit Efficient codingEfficient coding

log2(n + 1) additive bits on n-bit codewords Encoder/decoder is necessaryEncoder/decoder is necessary

Logic complexity grows as O(Logic complexity grows as O(nnloglognn)) Suitable for big RAM blocksSuitable for big RAM blocks

1 enc/dec for a whole memory1 enc/dec for a whole memory Needs refresh routineNeeds refresh routine

Not suitable for FPGAsNot suitable for FPGAs All data must be accessible at all times…All data must be accessible at all times… … … would need huge enc/decwould need huge enc/dec

Difficult implementation of protection Difficult implementation of protection against SETsagainst SETs

Registers

Encoder

Decoder

Combinatoriallogic

Triple Module Triple Module RedundancyRedundancy

Triplicate registers Triplicate registers and use a majority and use a majority voter to decodevoter to decode

Better protection Better protection than ECCthan ECC Tolerates 1 error Tolerates 1 error

over 3 bitover 3 bit Less efficient than Less efficient than

ECCECC 3x area and 3x area and

powerpower Protection against Protection against

SETsSETs Redundant Redundant

combinatorial combinatorial logiclogic

Suitable for high-Suitable for high-speed applicationsspeed applications

CombinatorialLogic

vo2

o1

o3

in

outCombinatorial

Logic

CombinatorialLogic

Registers

Registers

Registers

Dual-Interlocked Cell Dual-Interlocked Cell (DICE)(DICE)

4 memory nodes4 memory nodes Each memory node is Each memory node is

correlated to 2 other correlated to 2 other memory nodesmemory nodes InterlockInterlock

Symmetric cellSymmetric cell Each node is Each node is

equivalent to the equivalent to the othersothers

2 stable states2 stable states (1,0,1,0)(1,0,1,0) (0,1,0,1)(0,1,0,1)

pMOS propagate pMOS propagate right only low valuesright only low values

nMOS propagate left nMOS propagate left only high valuesonly high values

T. Calin, M. Nicolaidis & R. Velazco. “Upset Hardened Memory Design for Submicron CMOS Technology”. IEEE Transactions on Nuclear Science, vol. 43, no. 6, pages 2874-2878, December 1996.

Intrinsically immune to single-node particle Intrinsically immune to single-node particle hitshits

Vulnerable to multiple-node particle hitsVulnerable to multiple-node particle hits

11 0 01- 1z 0zA B C D

Choice for SEU Choice for SEU hardening: DICEhardening: DICE

Using a SEU-robust register circuit Using a SEU-robust register circuit gives the best trade-off between area gives the best trade-off between area occupancy and SEU toleranceoccupancy and SEU tolerance

The DICE is the smallest SEU-robust cellThe DICE is the smallest SEU-robust cell 12 transistors per memory cell12 transistors per memory cell 2x with respect to a traditional SRAM cell2x with respect to a traditional SRAM cell Smaller area than TMR (3x)Smaller area than TMR (3x) Better protection than ECCBetter protection than ECC

A B C D

SEU-robust latchSEU-robust latch

…add clock driven transmission gates to

access memory nodes…

Fully 2Fully 2× redundantredundant 2 inputs2 inputs 2 outputs2 outputs 2 clock 2 clock

buffersbuffers Normally they Normally they

have the same have the same logic levelslogic levels

Q0

Q1

ck0

ck1

ck0n

ck1n

ck1

ck1n

ck0

ck0n

D0

D1

A B C D

A B C D

Register layout for SEU Register layout for SEU robustnessrobustness

SEU-register is composed by a master latch and a slave SEU-register is composed by a master latch and a slave latchlatch Master nodes: MA, MB, MC, MDMaster nodes: MA, MB, MC, MD Slave nodes: SA, SB, SC, SDSlave nodes: SA, SB, SC, SD

Latch is vulnerable to multiple-node particle hits on Latch is vulnerable to multiple-node particle hits on correlated nodescorrelated nodes

The nodes of the two latches are interleaved in order to The nodes of the two latches are interleaved in order to increase the distance between correlated nodesincrease the distance between correlated nodes Less probability of multiple-node particle hitLess probability of multiple-node particle hit

ck0

ck1

ck0n

ck1n

ck1

ck1n

ck0

ck0n

D0

D1

MAMB

MC

MDQ0

Q1

ck0n

ck1n

ck0

ck1

ck1n

ck1

ck0n

ck0

SASB

SC

SDSA&

outputbuffer

clockbuffer MB SB clock

buffer MA

SC&

outputbuffer

clockbuffer MD SD clock

buffer MC

SET protection: SET protection: duplicated logicduplicated logic

Duplicate Duplicate combinatorial logiccombinatorial logic

Use SEU-robust FFUse SEU-robust FF SEU-robust FF has 2 SEU-robust FF has 2

inputs and 2 outputsinputs and 2 outputs Can tolerate an SEU on Can tolerate an SEU on

one of the two inputs.one of the two inputs. Duplicate data path Duplicate data path

alleviates the problem of alleviates the problem of latching erroneous stateslatching erroneous states

SEU-RFF

SEU-RFF

CombinatorialLogic

SEU-RFF

CombinatorialLogic

FF FFCombinatorialLogic

FF

Protection against Protection against Single-Event Single-Event Transients (SETs)Transients (SETs) Which occur in Which occur in

combinatorial logic combinatorial logic and propagate to and propagate to the flip-flopsthe flip-flops

Non SET-robustNon SET-robust

SET-robustSET-robust

Heavy-ion beam testsHeavy-ion beam testson SEU-robust registeron SEU-robust register

Static shift-register testStatic shift-register test Stream in configurationStream in configuration Beam start/stopBeam start/stop Retrieve configuration & compareRetrieve configuration & compare

Dynamic shift-register testDynamic shift-register test Continuous configuration load, Continuous configuration load,

retrieve & compare while retrieve & compare while configuration clock is running and configuration clock is running and beam is onbeam is on

Two test chips were fabricated 0.25μm CMOS

2×2 mm2, 1024 SEU-robust registers

0.13μm CMOS 1×2 mm2, 9216 SEU-robust

registers, 4096 standard library registers

Test controller

USB interface

Device Under Test (back)

Test chip in 0.25μm Test chip in 0.25μm CMOSCMOS

Test results:Test results:

SEU robustness of the register cell up to an LET of 79.6 cm2MeV/mg

no errors observed in either static and dynamic test modes

At an LET of 112 cm2MeV/mg and only in the dynamic test mode, the register cell showed SEU sensitivity, with SEU cross-section of 6.2·10-10

cm2/bit LHC environment: LET up to 17 cm2MeV/mg

Huhtinen and Faccio, “Computational method to estimate Single Event Upset rates in an accelerator environment”, Nuclear Instruments and Methods in Physics Research A 450 (2000) 155-172

For comparison: standard cell flip-flop in same For comparison: standard cell flip-flop in same technology has LETtechnology has LETthth==14.7cm2MeV/mg and σσsatsat =2.59·10-7 cm2/bit

Test type Ion Tilt LETeff Average flux Fluence No. errors[deg] [MeVcm2/mg] [cm-2s-1] [cm-2]

Ar8+ 0 15.1 2.0E+04 1.0E+06 0 ≤ 1.5E-09Kr17+ 0 35.6 1.0E+04 1.0E+06 0 ≤ 1.5E-09Kr17+ 45 51.2 1.5E+04 1.0E+06 0 ≤ 2.1E-09Xe26+ 0 56.3 1.5E+04 1.0E+06 0 ≤ 1.5E-09Kr17+ 60 74.0 1.5E+04 1.0E+06 0 ≤ 2.9E-09Xe26+ 45 79.6 2.0E+04 1.0E+06 0 ≤ 2.1E-09Xe26+ 60 112.0 2.0E+04 1.0E+07 0 ≤ 2.9E-10

N3+ 0 3.5 1.0E+04 1.1E+06 0 ≤ 1.3E-09Ar8+ 0 15.1 2.0E+04 6.0E+06 0 ≤ 2.4E-10Kr17+ 0 35.6 1.0E+04 1.1E+06 0 ≤ 1.3E-09Kr17+ 45 51.2 1.3E+04 2.0E+06 0 ≤ 1.0E-09Xe26+ 0 56.3 1.5E+04 1.0E+06 0 ≤ 1.5E-09Kr17+ 60 74.0 1.5E+04 1.0E+06 0 ≤ 2.9E-09Xe26+ 45 79.6 2.0E+04 6.0E+06 0 ≤ 3.5E-10Xe26+ 60 112.0 2.0E+04 1.1E+07 7 ≤ 1.2E-09

σ[cm2/bit]

Static shift-register test

Dynamic shift-register

test

Test chip in 0.13μm Test chip in 0.13μm CMOSCMOS

0.13μm CMOS0.13μm CMOS Good static mode robustnessGood static mode robustness

no errors up to 45.8 no errors up to 45.8 cm2MeV/mg In dynamic mode register shows sensitivityIn dynamic mode register shows sensitivity

strongly dependent on angle of incidence of the strongly dependent on angle of incidence of the beambeam

Suitable as configuration registerSuitable as configuration register Not suitable as user registerNot suitable as user register

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0

LET [cm2MeV/mg]

Cro

ss

se

cti

on

[cm

2/b

it]

Standardlibraryregister(static test)

Standardlibraryregister(dynamictest)

SEU-robustregister(dynamictest)

Kr25+Ne7+ Ar10+

0° 45°

60° 0° 45°

60° 0° 30°

45°

60°

ion

tilt

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0

LET [cm2MeV/mg]

Cro

ss

se

cti

on

[cm

2/b

it]

Standardlibraryregister(static test)

Standardlibraryregister(dynamictest)

SEU-robustregister(dynamictest)

Kr25+Ne7+ Ar10+

0° 45°

60° 0° 45°

60° 0° 30°

45°

60°

ion

tilt

Comparison of SEU-robust Comparison of SEU-robust registers in 0.25μm and 0.13μm registers in 0.25μm and 0.13μm

CMOSCMOSFeature size [μm]Feature size [μm] 0.250.25 0.130.13

Cell size [μmμm2] 68×11 14.5×3.6

Core power supply voltage [V]

2.5 1.2

Distance between memory Distance between memory nodes [μm]nodes [μm] 1010 2.42.4

Number of metal levels used 2 3

Enclosed layout transistors yes no

Minimum device width [μm][μm] 3.23 0.30

Typical inverter input capacitance [fF]

25 1

Drain area [Drain area [cm2] ≥≥5.85.8·10-9 ≥≥1.21.2·10-9

Static test cross-section Static test cross-section [[cm2/bit] @LET ] @LET ~34~34cm2MeV/mg

≤≤11.5· 10-9 ≤≤11.5· 10-10

Dynamic test LET Dynamic test LET [[cm2MeV/mg] @σ~ @σ~6.7·10-10

cm2/bit112 32.4

Study on FPGA Study on FPGA architecturesarchitectures

FPGAs differ onFPGAs differ on GranularityGranularity

size and implementation size and implementation capability of the Logic Block capability of the Logic Block (LB)(LB)

Routing structureRouting structure Island-styleIsland-style Sea-of-gatesSea-of-gates

I/O signaling capabilitiesI/O signaling capabilities Programming techniqueProgramming technique

SRAM, fuses, Flash, …SRAM, fuses, Flash, … Special-purpose blocksSpecial-purpose blocks

Multipliers, block RAM, Multipliers, block RAM, PLL/DLLs, processor cores, …PLL/DLLs, processor cores, …

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

I/OBlock

Logic BlockLogic Block

Best granularity 4-input-1-output Look-

Up Table (LUT) implements any

boolean function of 4 variables

holds its truth table in 16 configuration registers

can also be used as a 16×1-bit RAM block

31 configuration bits per LB are present and are organized in a shift-register structure

4-inputLUT

CarrychainA[0]

A[1]

A[2]

A[3]

CO

UT

Y

YQ

SEU-RFF

S/R

CIN

CL

K

D

Programmable Programmable interconnectionsinterconnections

Hierarchical routing LB has 17 I/Os 18 wires per

direction 6 long lines 12 short-distance

lines 8 direct neighbor 8 direct neighbor

connectionsconnections Connections

implemented with tristate buffers transmission gates multiplexers

256 configuration 256 configuration registers in totalregisters in total

LBpair

A[0]

B[0]

CLK

DA

SE

T

A[3]

B[3]

A[1

]

B[1

]

RE

S

A[2]

B[2]

DB

YB

YQB

YQ

A

YA

YQBinYBin

A2out

B2out

DBout

YA

out

YQ

Aou

t

To

utT

inYA

inY

QA

inA1o

ut

B1o

ut

RE

Sou

t

YBout

YQBout

B1i

n

RE

Sin

A1i

n

B2in

DBin

A2in

vdd

locallong long clockdouble

loca

llo

nglo

ngdo

uble

Radiation-tolerant Radiation-tolerant FPGAFPGA

Typical FPGA architectureTypical FPGA architecture Array of 32Array of 32×32 Logic Blocks 32 Logic Blocks

(LBs)(LBs) Configurable routingConfigurable routing

SRAM basedSRAM based ReprogrammableReprogrammable

256 I/Os256 I/Os ~25k equivalent gates~25k equivalent gates

2560 total user F/Fs2560 total user F/Fs Possible use as IP-corePossible use as IP-core

Logicblock

Logicblock

Logicblock

Logicblock

Logicblock

Logicblock

Logicblock

Logicblock

Logicblock

Test chip for Logic Test chip for Logic BlockBlock

A test chip was fabricated A test chip was fabricated in 0.25 micron CMOSin 0.25 micron CMOS Containing 32 LBs organized Containing 32 LBs organized

in 4 modulesin 4 modules No programmable No programmable

interconnectionsinterconnections Hardwired connectionsHardwired connections Cascaded LBsCascaded LBs

SEU/SET testing SEU/SET testing performedperformed Heavy-ion beamHeavy-ion beam All LBs configured as 4-way All LBs configured as 4-way

registered XORregistered XOR Clocked at 25 MHzClocked at 25 MHz Pseudo-random data inputPseudo-random data input No errors observedNo errors observed

σ ≤ 9σ ≤ 9.4·10-8 cm2/bit

Ion Tilt LETeff Average flux Fluence No. errors[deg] [MeVcm2/mg] [cm-2s-1] [cm-2]

Kr17+0 35.6 1.0E+04 1.0E+06 0 ≤ 4.7E-08

Xe26+ 0 56.3 2.0E+04 6.0E+06 0 ≤ 7.8E-09

Kr17+60 74.0 1.5E+04 1.0E+06 0 ≤ 9.4E-08

Xe26+45 79.6 2.0E+04 5.0E+06 0 ≤ 1.3E-08

Xe26+60 112.0 2.0E+04 5.0E+06 0 ≤ 1.9E-08

σ[cm2/bit]

Radiation-tolerant PLDRadiation-tolerant PLD

Compatible with 16LV8 Compatible with 16LV8 commercial devicecommercial device

Fuse basedFuse based Laser programmableLaser programmable

10 inputs, 8 programmable 10 inputs, 8 programmable input/outputsinput/outputs

Configurable AND matrix Configurable AND matrix generates mintermsgenerates minterms

Fixed OR matrix sums Fixed OR matrix sums mintermsminterms 8 minterms per output8 minterms per output

Outputs can be registered or Outputs can be registered or notnot

Outputs are fed back to AND Outputs are fed back to AND matrix for generation of matrix for generation of more complex functionsmore complex functions

Mn

M2

M1

M3

M4

M5

M6

M7

M8

Mn-3

Mn-2

Mn-1

A1A2…

…

…

Ap

Q1Q2Qp …

…

OLOLOL

CL

K

…

Fuses & PLD chip Fuses & PLD chip layoutlayout

Fuses consist in a 7Fuses consist in a 7×1 μm1 μm22 metal line (aluminum)metal line (aluminum) Laser programmableLaser programmable 2080 programming fuses2080 programming fuses Occupy 70% of core areaOccupy 70% of core area

Chip size is 2Chip size is 2×2 mm2 mm22

laser

ConclusionsConclusions An SEU-robust register structure was designed

and tested in two CMOS technologies Results obtained in the 0.25 μm technology

demonstrate the register is suitable for the implementation of programmable logic

The 0.13 μm circuit showed good robustness in the static tests but appeared to be sensitive in the dynamic tests

Suitable for configuration storage Additional work is necessary for the FPGA user register

The approach demonstrated the feasibility of the SEU-tolerant radiation-hard PLD and FPGA PLD chip was fabricated and tested The LB of the FPGA design was finalized, work is on

going to complete the FPGA with interconnection infrastructure