Timer Interface Module MTT48 9 - 1 TIMER INTERFACE MODULE (TIM)

Timer Interface Module MTT48 9 - 1

TIMER INTERFACE MODULE (TIM)


Understand input capture function

Understand output compare function

Understand pulse width modulation functions

Program TIM free running reference clock and options

Configure any TIM channel as either:

• Input capture

• Output compare

• PWM

Module Objectives

Initialize TIM and timer reference counter for 250 ns resolution from 8 MHz

system clock

Configure channel 1 as input capture

Configure channel 2 as output compare

Configure channel 3 as buffered 75% duty cycle PWM

TIM Module Exercises


TIMER INTERFACE MODULE

68HC08CPU

SystemIntegration

Module(SIM)

ClockGeneration

Module(CGM)

TimerInterfaceModule(TIM)

DirectMemoryAccessModule(DMA)

SerialCommunications

Interface(SCI)

Internal Bus (IBUS)

SerialPeripheralInterface

(SPI)

RandomAccess

Memory(RAM)

ElectronicallyProgrammable

ROM

LVI

COP

Monitor ROM

IRQ

BREAK

RESET

Four programmable channels• Input captures

– Rising edge, falling edge, or any edge triggering• Output compares

– Set, clear, or toggle actions• Pulse width modulation (PWM)

– Buffered or Unbuffered signal generation

Programmable clock input• System clock with prescaler• External TIM Clock input(4 MHz Maximum Frequency)

Free-running or modulo up-count operation

Counter overflow actions

TIM Counter stop and reset

DMA interrupt generation

Modular Architecture Expandable to 8 Channels


Timer Reference Block Diagram

PRESCALER

PRESCALER SELECT

TCLK

InternalBusClock

PS2 PS1 PS0

INTLogic

TSTOP

PTE3/TCLK

16-Bit Counter

TRST

16-Bit Comparator

TMODH:TMODL

TOF

TOE

To Channel Logic

Data

Bus

16-Bit Latch


Timer Clock Reference

All four timer channels receive their clock reference from

• Free running counter

• Modulo up counter

Consists of:

• 16 bit free running read only timer counter

• 16 bit software read/write modulo register

• 16 bit comparator (timer counter vs. modulo register)– When counter matches modulo register

• Timer Overflow Flag (TOF) set

• Counter resets to $0000

• Counter begins counting again

Generated from software selectable clock source

• External pin TCLK

• Output of 7 bit system clock prescaler


Timer Status and Control Register (TSC)

Timer Status and Control Register (TSC)

• Clock select and prescaler bits (PS2-PS0)

• Timer Overflow Flag (TOF)

Set when 16 bit timer counter resets to $0000

Cleared by reading TSC and then writing logic zero to TOF– If overflow occurs during clearing operation, write has

no effect

1 = Timer has reset

0 = Timer has not reset yet

• Timer Overflow interrupt Enable (TOE)

Enables timer overflow interrupt

1 = Enable interrupt

0 = Disable interrupt

WRITE: 0 TRST

READ: TOF 0 0

RESET: 0 0 1 0 0 0 0 0

TOE TSTOP PS2 PS1 PS0 TSC

• Timer Stop (TSTOP)– Stops the timer counter– Recommended1 = Timer stopped

0 = Timer active

• Timer Reset (TRST)– Resets timer counter AND prescaler– Automatically cleared after counter reset

1 = Reset counter and prescaler

0 = No effect

NOTE: Setting both TSTOP and TRST stops the counter $0000


PS2 PS1 PS0 TIM Clock Source

0 0 0 Internal Bus Clock ÷ 1







1 1 1 PTE3/TCLK

NOTE: TCLK pulses must be longer than two system clock

pulses or will be ignored

Timer Prescale Select Bits (PS0-2)


Timer Counter Register

Timer Counter Register (TCNTH, TCNTL)• 16 bit, read only, free running counter• Reading high byte latches low byte until read

WRITE:

READ: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

RESET: 0 0 0 0 0 0 0 0

TCNTH

WRITE:

READ: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

RESET: 0 0 0 0 0 0 0 0

TCNTL

WRITE:

READ:

RESET: 1 1 1 1 1 1 1 1

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TMODH

WRITE:

READ:

RESET: 1 1 1 1 1 1 1 1

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TMODL

Timer Modulo Register (TMODH, TMODL)• Contents compare against TCNTH, TCHTL to determine reset time• Writing to TMODH disables TOF and overflow interrupts, until write to TMODL

Timer Modulo Register


Timer Resolution and Range

Timer resolution is inversely proportional to system clock and prescaler value

Resolution (sec) = 1 ÷ (Bus Clock ÷ prescaler)

Timer range depends on value in TMODH and TMODL

Range = 0 .. Resolution x TMOD value

Max Range = 0 .. Resolution x 65,535

Example:

• Calculate resolution and range given 4 MHz bus clock, prescaler value of 4

(010), and TMOD = $00FF

Resolution = 1 ÷ ( 4 MHz ÷ 4 ) = 1 ÷ 1 MHz = 1µs

Range = 1µs x $00FF = 1µs x 255 = 255 µs


Timer Channel Block Diagram

16-bit Comparator

CHANNEL XPTxLogic

IntLogic

CHxIE

PTx/TCHx

MSxA

TCHxH : TCHxL

16-bit Latch

ELSxB

X

ELSxA

CHxF

DMASx

TOVx

CHxMAX

From TOF

Data

Bus


Compare/Capture Unit16-bit Free Running Counter

16-bit Input Capture Latch

Status Flag is set upon capture

Interrupt request to CPU08

LatchEdge Select& DetectICx

CHxF

CHxIE

Rising EdgesFalling EdgesAny Edge

Optional Local Interrupt Mask(enabled through software)

• Provides a mechanism to capture the time at which an external event occurs

TCNTH:TCNTHL

TCHxH:TCHxL

Input Capture Function


Input Capture Example - Measured Pulse Width -

T1

T2

1. Configure timer channel for input capture, rising edge

2. Capture time T1

3. Capture time T2

4. Period = T2 - T1


Compare/Capture Unit16-Bit Free-Running Counter

16-Bit Compare

16-Bit Output Compare Register (programmed by software)

Pin ControlLogic

Interrupt request to CPU08

OCx

CHxFStatus Flag is set

upon compare match

CHxIE

Optional Local Interrupt Mask(enabled through software)

• Provides a mechanism to output a signal at a specific time

Set PinClear PinToggle PinAction taken upon

match of compareregister with counter

TCNTH:TCNTHL

TCHxH:TCHxL

Output Compare Function

Possible uses:

• Generating waveforms or pulses

• Elapsed time indicator (to external circuitry)

• Triggering external events


Output Compare Example- Pulse Generation -

1. Set compare value to T1

2. Configure timer channel for output compare, set output

3. Set compare value to T2

4. Configure timer channel for output compare, clear output

5. Generated pulse width = T2 - T1

T1

T2


Interrupt latency and execution time may limit minimum pulse width possible

using interrupt on overflow method

To maximize resolution and avoid unsynchronized writes:

• Enable the output compare interrupt function when new pulse width value

required

• Write new value to output compare register within output compare

interrupt routine

Output Compare Synchronization Method


Timer Overflow Action

Timer Channel Status and Control Registers (TSCx)• Toggle on Overflow (TOVx)

– Controls behavior Output Compare and PWM only– Has no effect when channel configured as input capture– Normal used in generating PWMs

1 = Toggle Channel output on Timer Overflow

0 = Do nothing on Timer Overflow

WRITE: 0

READ: CHxF

RESET: 0 0 0 0 0 0 0 0x = Channel number 0, 1, 2, etc.

CHxIE MSxB MSxA ELSxB ELSxA TOVx CHxMAXTSCx


Channel Timer Registers

Timer Channel registers (TCHx)

• Input Capture– Timer register value latched upon input capture

• Output Compare– Value to compare timer against

WRITE:

READ:

RESET: INDETERMINATE AFTER RESET

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TCHxH

WRITE:

READ:

RESET: INDETERMINATE AFTER RESETx = Channel number 0, 1, 2, etc.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCHxL


Mode, Edge, and Level Selection

X0 00 Output Preset Pin under port control; initial output lvl high

X1 00 Output Preset Pin under port control; initial output lvl low

00 01 Input Capture Capture on Rising Edge Only

00 10 Input Capture Capture on Falling Edge Only

00 11 Input Capture Capture on ANY (rising or falling) Edge

01 01 Output Compare Toggle output line on Output Compare

01 10 Or Clear output line to 0 on output compare

01 11 PWM Set output line to 1 on output compare

1X 01 Buffered Output Toggle output on compare

1X 10 Compare Or Clear output on compare

1X 10 Buffered PWM Set output on compare

MSxB:MSxA ELSxB:ELSxA Mode Configuration

Note 1: MSxB has priority over MSxA (When MSxB is set, MSxA is don't care)Note 2: Unbuffered PWMs are set up while in Output Compare Mode

WRITE: 0

READ: CHxF




Channel Interrupt & Status

Timer Channel Status and Control Registers (TSCx)

• Channel x Interrupt Enable (CHxE)– Enables TIM CPU interrupts and TIM DMA service requests on channel x.

1 = Channel x CPU interrupt requests and DMA service requests enabled

0 = Channel x CPU interrupt requests and DMA service requests disabled

• Channel Status Flag (CHxF)– Input Capture

• Set when active edge occurs– Output Compare

• Set when the value in TIM counter registers matches value in TIM channel register– Cleared by reading status register then writing logic one to CHxF

1 = Input capture or output compare on channel x

0 = No event capture or output compare on channel x

WRITE: 0

READ: CHxF




TIM Exercise Calculate the register values to configure:

• Timer for 8µs resolution from a 4 MHz Bus clock• Timer channel 1 to capture rising edge of a signal• Timer channel 2 to toggle it’s output between states every 100 ms

Given:• MCU has just been reset

* Timer exercise

TSC EQU $0020TMODH EQU $0024TMODL EQU $0025TSC1 EQU $0029TSC2 EQU $002CTCH2H EQU $002DTCH2L EQU $002E

* Configure Timer for 8µs resolution, using 4 MHz system clock MOV #_30_,TSC ; Reset timer, Configure clock prescaler MOV #_30_,TMODH ;MSB for modulo register MOV #_D4_,TMODL ;LSB for modulo register

* Configure Timer channel 1 to capture rising edge of pulse MOV #_04_,TSC1 ;Input capture, rising edge only, no interrupts

* Configure Timer channel 2 to toggle output MOV #_30_,TCH2H ;Set compare value MSB MOV #_D4_,TCH2L ;Set compare value LSB MOV #_14_,TSC2 ;Output compare, toggle output, no interrupts

BCLR 5,TSC ;Start timer, reset bit automatically clear


Mea

sure

Per

iod

of

a S

qu

are

Wav

e E

xerc

ise

Wri

te a

rou

tine

that

mea

sure

s th

e pe

riod

of

a sq

uare

wav

e on

TC

H1.

The

rou

tine

uses

the

Inpu

t C

aptu

re f

unct

ion

to d

eter

min

e th

e di

ffer

ence

in ti

me

from

one

ris

ing

edge

to th

e ne

xt. U

se a

so

ftw

are

polli

ng, n

on-i

nter

rupt

-dri

ven,

rou

tine.

Ass

ume

Syst

em c

lock

= 8

MH

z.

S

uggest

ed p

rogra

m s

teps:

Add

ress

of

Tim

e (1

6 bi

t val

ue)

Add

ress

of

Dif

fere

nce

(16

bit v

alue

) A

ddre

sses

for

: Tim

er S

tatu

s/C

ontr

ol R

egis

ter

Tim

er C

h. 1

Sta

tus/

Con

trol

Reg

iste

r

T

imer

Ch.

1 H

igh

Reg

iste

r

T

imer

Ch.

1 L

ow R

egis

ter

Tim

er C

ount

er R

egis

ter

Hig

h

T

imer

Cou

nter

Reg

iste

r L

ow

Write

your

pro

gra

m h

ere

:

TIME EQU $50

DIFF EQU $52

TSC EQU $20

TSC1 EQU $29

TCH1H EQU $2A

TCH1L EQU $2B

TCNTH EQU $22

TCNTL EQU $23

Get

tim

e of

nex

t ris

ing

edge

of

squa

re w

ave

& c

alcu

late

di

ffer

ence

bet

wee

n fi

rst a

nd n

ext t

imes

:

1

0. W

ait h

ere

if C

H1F

fla

g is

not

set

, els

e go

to 1

1.

11. L

oad

TC

H1L

cou

nt in

to a

ccum

ulat

or.

12. S

ubtr

act

TIM

EL

fro

m a

ccum

ulat

or.

13. S

tore

dif

fere

nce

to D

IFF

L R

AM

loca

tion

.

14

. Loa

d T

CH

1H c

ount

into

acc

umul

ator

.

15

. Sub

trac

t wit

h bo

rrow

TIM

EH

fro

m a

ccum

ulat

or.

16. S

tore

dif

fere

nce

to D

IFF

H R

AM

loca

tion

.

17

. Don

e, s

tay

here

.H

C08

-InC

apE

xer

Con

figu

re T

imer

for

8uS

res

olut

ion,

usi

ng 8

MH

z cl

ock

1. R

eset

Tim

er a

nd C

onfi

gure

clo

ck P

resc

aler

In

itia

lize

TIM

CH

1 fo

r in

put c

aptu

re f

unct

ion:

2. L

oad

TC

R w

ith

"cap

ture

ris

ing

edge

" v

alue

. C

lear

TIM

CH

1 fl

ag (

CH

1F),

Sta

rt T

imer

;

3. R

ead

Tim

er C

hann

el 1

Sta

tus

Reg

iste

r.

4. W

rite

a lo

gic

"zer

o" t

o C

H1F

.

5.

Sta

rt ti

mer

, res

et b

it a

utom

atic

ally

cle

ars.

Get

tim

e of

fir

st r

isin

g ed

ge o

f sq

uare

wav

e &

cle

ar C

H1F

:

6. W

ait h

ere

if C

H1F

fla

g is

not

set

, els

e go

to 7

.

Als

o, f

irst

ste

p to

cle

ar C

H1F

fla

g

7.

Loa

d T

CH

1H c

ount

into

H:X

Reg

iste

r.

8. S

tore

H:X

to T

IME

RA

M lo

cati

on.

9. S

econ

d st

ep to

cle

ar C

H1F

fla

g(W

rite

"0"

to C

H1F

)


Su

gges

ted

prog

ram

ste

ps:

Add

ress

es f

or: T

imer

Sta

tus/

Con

trol

Reg

iste

r

T

imer

Ch.

2 S

tatu

s/C

ontr

ol R

egis

ter

Tim

er C

h. 2

Hig

h R

egis

ter

Tim

er C

h. 2

Low

Reg

iste

r

T

imer

Cou

nter

Reg

iste

r H

igh

Tim

er C

ount

er R

egis

ter

Low

1 K

Hz

Sq

uar

e W

ave

Exe

rcis

eW

rite

a r

outin

e th

at g

ener

ates

a 1

KH

z sq

uare

wav

e on

the

TC

H2

pin.

Ass

ume

the

inte

rnal

pr

oces

sor

cloc

k =

4 M

Hz.

Use

a s

oftw

are

polli

ng, n

on-i

nter

rupt

dri

ven,

rou

tine.

D =

Del

ay f

rom

one

TC

MP

cloc

k ed

ge to

the

next

= 5

00 u

Sec

F (

timer

clo

ck F

requ

ency

) =

4 M

Hz

÷ 4

= 1

MH

z

Tot

al #

of

timer

clo

cks

= F

x D

= (

1 x

10 E

6) x

(50

0 x

10 E

-6)

= 5

00

1

3. A

dd w

ith

carr

y T

CH

2H to

acc

umul

ator

.

14.

Sto

re a

ccum

ulat

or to

TC

H2H

.

15.

Get

sav

ed d

elay

for

TC

H2L

.

16.

Sto

re a

ccum

ulat

or to

TC

H2L

.

17.

Wri

te a

logi

c "0

" to

CH

2F, 2

nd s

tep

to c

lear

fla

g.

1

8. G

oto

step

8.

HC

08-O

utC

ompE

xer

Wri

te y

our

prog

ram

her

e:

TSC EQU $20

TSC2 EQU $2C

TCH2H EQU $2D

TCH2L EQU $2E

TCNTH EQU $22

TCNTL EQU $23

Con

figu

re T

imer

for

8uS

res

olut

ion,

usi

ng 8

MH

z cl

ock

1.

Res

et T

imer

and

Con

figu

re c

lock

Pre

scal

er

Init

iali

ze T

IM C

H2

to to

ggle

out

put

ever

y 1m

S

2. S

et M

SB

com

pare

val

ue.

3. S

et L

SB

com

pare

val

ue.

4. L

oad

TS

C2

wit

h "T

oggl

e ou

tput

on

com

pare

" va

lue.

Cle

ar C

H2F

fla

g(2

step

s re

quir

ed):

5. R

ead

TS

C2.

6.

Wri

te a

logi

c "0

" to

CH

2F.

7. S

tart

Tim

er

Whe

n C

H2F

=1

add

500

usec

. del

ay &

set

for

nex

t out

put:

8.

Wai

t for

CH

2F to

go

set,

also

1st

. ste

p to

cle

ar f

lag

9. L

oad

Acc

umul

ator

wit

h lo

w h

alf

of 5

00 u

sec

dela

y.

1

0. A

dd T

CH

2L v

alue

to a

ccum

ulat

or.

1

1. S

ave

accu

mul

ator

.

12.

Loa

d ac

cum

ulat

or w

ith

hi h

alf

of 5

00 u

sec

dela

y.


Unbuffered PWM Signal

Any channel can generate an unbuffered PWM

• Uses output compare

• Toggling output based on timer overflow

PWM period set by:

• Modulo count value

• Clock prescaler output

Pulse width duration set by:

• Output compare register value– Timer channel configured to force output pin to

complement of pulse width level


PWM Signal Generation

T1 = PWM Period = Timer overflow point

• Calculate prescaler value and TMOD = T1

T2 = Pulse width = Output compare value

Example: Want 50% duty cycle PWM with period of 100 µs from a 4 MHz system

clock.

Select prescaler of 4, Resolution = 1 ÷ (4 MHz ÷ 4) = 1µs

TMOD = T1 ÷ Resolution = 100µs ÷ 1µs = 100

TCHxH:TCHxL = T2 = Duty cycle x TMOD = 50% x 100 = 50

A = Output compare, clear output occurs B = Timer overflow, toggle output occurs

T2

T1

A B A B A

TIME


PWM Resolution

Period

• 8-bit PWMs– Variable in 256 increments of system clock

• 16-bit PWMs– Variable in 65536 increments of system clock

Pulse width is variable up to N increments of system clock

N = System clock counts for Period– Pulse width = N/4 = 25% duty cycle– Pulse width = N/2 = 50% duty cycle– Pulse width = 3N/4 = 75% duty cycle


Unbuffered PWM Initialization

1) Stop and reset timer

2) Select timer counter modulo value and timer clock prescaler to provide

required PWM period

3) Load output compare register with pulse width value

4) Configure timer channel for output compare operation

5) Select the timer counter toggle on overflow function

6) Configure timer channel to force output pin to complement of pulse

width level

• Toggle on output compare should not be used

7) Enable the timer


Create an eight-bit unbuffered PWM with the following characteristics:• Frequency of approx 32 KHz• Duty cycle of 75%• Initial Pulse Width begins in logic 1 state

Assume:• 8 MHz system clock• Use timer channel 0• HC08 has just been reset

Steps Required:Stop and reset timer

• Set TSTOP and TRST in TSC register

Configure prescaler and modulo register for 32 KHz• Note PS2:0 in TSC register = 000 (divide by 1) on timer reset• Set TMODH:TMODL = $00FF (8 MHz / 256 32 KHz)

Configure timer status and control register for channel 0 (TSC0)• Set MS0A = 1 (Output Compare)• Set ELS0B:ELS0A = 10 (Clear output line on output compare)• Set TOV0 = 1 (Enable timer counter toggle on overflow) • Clear CH0E (Disable output compare interrupt)

Load output compare register for pulse width of 192 counts• Set TCH0H = $00, TCH0L = $C0 (192 / 256 = 75%)

Enable the timer• Clear TSTOP in the TSC register

Unbuffered PWM “Example 1”

Frequency ~ 32Khz (8Mhz/256)

Pulse Width Duration= 75% Duty Cycle192256


Limitation for Unbuffered PWM

Previous methods for changing pulse widths work in most cases

• Except when change in pulse width is large

Example:

Could not change from a 99% duty cycle to a 1% duty cycle


Buffered PWMChannel Block Diagram

16-bit Comparator

CHANNEL YPTxLogic

IntLogic

CHyE

PTy/TCHy

MSyA

TCHyH : TCHyL

16-bit Latch

ELSyB

X

ELSyA

CHyF

DMASy

TOVy

CHyMAX

MSxB X

From TOF

Data

Bus

16-bit Comparator

CHANNEL XPTxLogic

IntLogic

CHxE

PTx/TCHx

MSxA

TCHxH : TCHxL

16-bit Latch

ELSxB

X

ELSxA

CHxF

DMASx

TOVx

CHxMAX


What is Buffered PWM?

Uses two output compare registers to control a single output

• Overcomes synchronization and pulse width limitations of unbuffered PWMs

• Channels 0 and 1 and/or channels 2 and 3 may be linked

Selected by setting MS0B and/or MS2B bit

• Linked timer channel (ch 1 and/or 3) output becomes general purpose I/O – Under control of DDR and data register– Regardless of TSC1 and/or TSC3 settings

HC08 Buffered PWM Operation

Configure either channel 0 or 2 as for unbuffered PWM

• Except MSxB bit is set in TSCx register

Initial pulse width must be loaded into channel 0 or 2’s output compare register

Subsequent pulse width values are written to inactive linked channel at any time

• Writing to compare register of inactive channel enables that channel

• Output control changes after next counter overflow – Auto synchronization


Buffered PWM “ Example 1 “

Create an eight-bit buffered PWM with following characteristics:

• Frequency of approximately

Assume:

• System clock is approx 8 Mhz

• Use timer channels 0 and 1

• HC08 has just been reset

Frequency ~ 32Khz (8Mhz/256)Pulse Width Duration = 254 counts


Stop and reset the timer

• Set TSTOP and TRST in TSC register

Configure prescaler and TMOD register for 32 KHz

• Note PS2:0 in TSC register = 000 (divide by 1) on timer reset

• Set TMODH:TMODL = $00FF (8 MHz / 256 32 KHz)

Configure timer status and control register for channel 0 (TSC0)

• Set MS0B:MS0A = 11 (Buffered PWM, Output Compare)

• Set ELS0B:ELS0A = 10 (Clear output line on output compare)

• Set TOV0 = 1 (Enable timer counter toggle on overflow)

• Clear CH0E (Disable output compare interrupt)

Load output compare register 0 for pulse width of 254 counts

• Set TCH0H = $00, TCH0L = $FE (254 / 256 = 99%)

Enable the timer

• Clear TSTOP in TSC register

Buffered PWM “ Example 1 Solution “

Frequency = 32KhzPulse Width = 254


Pulse Width ModulationBuffered/Unbuffered

Unbuffered PWMs

• Advantages– Consistent, non-serviced PWM waveform– Programmable period and duty cycle

• Disadvantage– Must synchronize changes to duty cycle

Buffered PWMs

• Advantages– Unsynchronized changes to duty cycle, auto sync

• Disadvantage– Requires two timer channels– Must keep track of inactive channel


TIM Exercise - Buffered PWM -Code configures a Timer channel as a buffered 75% duty cycle PWM.Assume:

• Timer register already configured for 125 ns resolution• TMOD register has not been initialized (default $FFFF)• Pick your own PWM frequency/period

Given: * Timer exercise - Part 2

TSC EQU $0020TMODH EQU $0024TMODL EQU $0025TSC0 EQU $0026TCH0H EQU $0027TCH0L EQU $0028TSC1 EQU $0029TCH1H EQU $002ATCH1L EQU $002B* Timer exercise - Part 2

BSET 5,TSC ;Stop timer BSET 4,TSC ;Reset timer

* Could pick any period you want, lets choose max in 8-bit PWM, yields 32 KHz MOV #$00,TMODH ;MSB for modulo register MOV #$FF,TMODL ;LSB for modulo register

*Want 75% duty cycle = 3/4 * period = 3/4 * 256 = 192 MOV #$00,TCH0H ;Set compare value MSB

MOV #$C0,TCH0L ;Set compare value LSB

* Configure Timer channel 0 as buffered PWM MOV #$2A,TSC0 ;Buffered PWM, Clear on compare, Enable ;toggle on timer overflow

BCLR 5,TSC ;Start timer, reset bit automatically clear


Additional Timer Questions

a) What is the fastest frequency that can be achieved for a 5-bit PWM?

b) What is the fastest frequency that can be achieved for a 12-bit PWM?

c) What happens when an output compare value is greater than the value

in the modulus registers?

d) What happens if the output compare register is the same as the

modulus register

e) With ELSxB:ELSxA = 00 (discrete I/O mode), will the timer still generate

interrupts if enabled?

f) How do you force an output compare or PWM to begin in a logic zero or

logic one state?



ANSWERS

a) Bus Clock/32 ~ 8Mhz/32 ~ 250 KHz

b) Bus Clock/4096 ~ 8Mhz/4096 ~ 2 KHz

c) The output compare will never occur if the Output Compare register is greater

than the modulus register

d) The counter overflow toggle will take precedence (if enabled) over an output

compare if they occur at the same time

e) Yes. You must disable the channel interrupts or stop the timer to disable timer

interrupts


f) To force a channel output to a logic zero:

• Set ELSxB:ELSxA = 10

• Ensure (MSxB:)MSxA are set to any state other than (0)0

• Clear the appropriateReset the timer (TRST = 1)

To force a channel output to a logic one:

• Set ELSxB:ELSxA = 11

• Ensure (MSxB:)MSxA are set to any state other than (0)0

• Clear the appropriateReset the timer (TRST = 1)

Note: You cannot use I/O port data register and DDR to preset

state of an output pin prior to enabling timer channel


ANSWERS


100% Duty Cycle Selection

Timer Channel Status and Control Registers (TSC0 - TSC3)• Channel Max - 100% PWM duty cycle (CHxMAX)

– Forces duty cycle to 100%– Takes effect in cycle after being set or cleared

1 = Enable 100 % duty cycle0 = Disabled

WRITE: 0

READ: CHxF


CHxE MSxB MSxA ELSxB ELSxA TOVx CHxMAXTSCx


Additional Information- DMA Servicing -

Timer DMA Select Register (TDMA)

• DMA Channel Selects ( DMAS3 - DMAS0)– Selects either CPU or DMA interrupts for that channel

1 = DMA handles channel x interrupts0 = CPU handles channel x interrupts

NOTE:

Channel interrupts are still enabled/disabled by CHxE bit in TSCx register

WRITE:

READ: 0 0 0 0

RESET: 0 0 0 0 0 0 0 0

DMA3S DMA2S DMA1S DMA0STDMA


Additional Information- Low Power Modes -

WAIT

• TIM remains active

• TIM Registers are not accessible by the CPU

• Enabled TIM interrupts can wake processor

• DMA can service the TIM without exiting wait mode

• If TIM functions are not required during wait mode, stop TIM before

executing WAIT instruction

STOP

• TIM becomes inactive

• Register contents not affected

• TIM operation resumes when the MCU exits stop mode after and external

interrupt


Register Summary

TSC TOF TOIE TSTOP TRST 0 PS2 PS1 PS0

TDMA 0 0 0 0 DMAS3 DMAS2 DMAS1 DMAS0

TCNTH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

TCNTL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TMODH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

TMODL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TCS0 CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MX

TCH0H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

TCH0L BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TCSn CHnF CHnIE 0 MSnA ELSnB ELSnA TOVn CHnMX

TCHnH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

TCHnL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

•••

•••


Mea

sure

Per

iod

of

a S

qu

are

Wav

e S

olu

tion

Wri

te a

rou

tine

that

mea

sure

s th

e pe

riod

of

a sq

uare

wav

e on

TC

H1.

The

rou

tine

uses

the

Inpu

t C

aptu

re f

unct

ion

to d

eter

min

e th

e di

ffer

ence

in ti

me

from

one

ris

ing

edge

to th

e ne

xt. U

se a

so

ftw

are

polli

ng, n

on-i

nter

rupt

-dri

ven,

rou

tine.

Ass

ume

Syst

em c

lock

= 8

MH

z.

Su

gges

ted

prog

ram

ste

ps:

Add

ress

of

Tim

e (1

6 bi

t val

ue)

Add

ress

of

Dif

fere

nce

(16

bit v

alue

) A

ddre

sses

for

: Tim

er S

tatu

s/C

ontr

ol R

egis

ter

Tim

er C

h. 1

Sta

tus/

Con

trol

Reg

iste

r

T

imer

Ch.

1 H

igh

Reg

iste

r

T

imer

Ch.

1 L

ow R

egis

ter

Tim

er C

ount

er R

egis

ter

Hig

h

T

imer

Cou

nter

Reg

iste

r L

ow

Wri

te y

our

prog

ram

her

e:

TIME EQU $50

DIFF EQU $52

TSC EQU $20

TSC1 EQU $29

TCH1H EQU $2A

TCH1L EQU $2B

TCNTH EQU $22

TCNTL EQU $23

Get

tim

e of

nex

t ris

ing

edge

of

squa

re w

ave

& c

alcu

late

di

ffer

ence

bet

wee

n fi

rst a

nd n

ext t

imes

:

1

0. W

ait h

ere

if C

H1F

fla

g is

not

set

, els

e go

to 1

1.

11. L

oad

TC

H1L

cou

nt in

to a

ccum

ulat

or.

12. S

ubtr

act

TIM

EL

fro

m a

ccum

ulat

or.

13. S

tore

dif

fere

nce

to D

IFF

L R

AM

loca

tion

.

14

. Loa

d T

CH

1H c

ount

into

acc

umul

ator

.

15

. Sub

trac

t wit

h bo

rrow

TIM

EH

fro

m a

ccum

ulat

or.

16. S

tore

dif

fere

nce

to D

IFF

H R

AM

loca

tion

.

17

. Don

e, s

tay

here

.H

C08

-InC

apS

ol

Con

figu

re T

imer

for

8uS

res

olut

ion,

usi

ng 8

MH

z cl

ock

1. R

eset

Tim

er a

nd C

onfi

gure

clo

ck P

resc

aler

In

itia

lize

TIM

CH

1 fo

r in

put c

aptu

re f

unct

ion:

2. L

oad

TC

R w

ith

"cap

ture

ris

ing

edge

" v

alue

. C

lear

TIM

CH

1 fl

ag (

CH

1F),

Sta

rt T

imer

;

3. R

ead

Tim

er C

hann

el 1

Sta

tus

Reg

iste

r.

4. W

rite

a lo

gic

"zer

o" t

o C

H1F

.

5.

Sta

rt ti

mer

, res

et b

it a

utom

atic

ally

cle

ars.

Get

tim

e of

fir

st r

isin

g ed

ge o

f sq

uare

wav

e &

cle

ar C

H1F

:

6. W

ait h

ere

if C

H1F

fla

g is

not

set

, els

e go

to 7

.

Als

o, f

irst

ste

p to

cle

ar C

H1F

fla

g

7.

Loa

d T

CH

1H c

ount

into

H:X

Reg

iste

r.

8. S

tore

H:X

to T

IME

RA

M lo

cati

on.

9. S

econ

d st

ep to

cle

ar C

H1F

fla

g(W

rite

"0"

to C

H1F

)

MOV #$36,TSC

MOV #$04,TSC1

LDA TSC1

BCLR #7,TSC1

BCLR #5,TSC

WAIT1 BRCLR #7,TSC1,WAIT1

LDHX TCH1H

STHX TIME

BCLR #7,TSC1

WAIT2 BRCLR #7,TSC1,WAIT2

LDA TCH1L

SUB TIME+1

STA DIFF+1

LDA TCH1H

SBC TIME

STA DIFF

DONE BRA DONE


Su

gges

ted

prog

ram

ste

ps:

Add

ress

es f

or: T

imer

Sta

tus/

Con

trol

Reg

iste

r

T

imer

Ch.

2 S

tatu

s/C

ontr

ol R

egis

ter

Tim

er C

h. 2

Hig

h R

egis

ter

Tim

er C

h. 2

Low

Reg

iste

r

T

imer

Cou

nter

Reg

iste

r H

igh

Tim

er C

ount

er R

egis

ter

Low

1 K

Hz

Sq

uar

e W

ave

Exe

rcis

eW

rite

a r

outin

e th

at g

ener

ates

a 1

KH

z sq

uare

wav

e on

the

TC

H2

pin.

Ass

ume

the

inte

rnal

pr

oces

sor

cloc

k =

4 M

Hz.

Use

a s

oftw

are

polli

ng, n

on-i

nter

rupt

dri

ven,

rou

tine.

D =

Del

ay f

rom

one

TC

MP

cloc

k ed

ge to

the

next

= 5

00 u

Sec

F (

timer

clo

ck F

requ

ency

) =

4 M

Hz

÷ 4

= 1

MH

z

Tot

al #

of

timer

clo

cks

= F

x D

= (

1 x

10 E

6) x

(50

0 x

10 E

-6)

= 5

00

1

3. A

dd w

ith

carr

y T

CH

2H to

acc

umul

ator

.

14.

Sto

re a

ccum

ulat

or to

TC

H2H

.

15.

Get

sav

ed d

elay

for

TC

H2L

.

16.

Sto

re a

ccum

ulat

or to

TC

H2L

.

17.

Wri

te a

logi

c "0

" to

CH

2F, 2

nd s

tep

to c

lear

fla

g.

1

8. G

oto

step

8.

HC

08-O

utC

ompS

ol

Wri

te y

our

prog

ram

her

e:

TSC EQU $20

TSC2 EQU $2C

TCH2H EQU $2D

TCH2L EQU $2E

TCNTH EQU $22

TCNTL EQU $23

Con

figu

re T

imer

for

8uS

res

olut

ion,

usi

ng 8

MH

z cl

ock

1.

Res

et T

imer

and

Con

figu

re c

lock

Pre

scal

er

Init

iali

ze T

IM C

H2

to to

ggle

out

put

ever

y 1m

S

2. S

et M

SB

com

pare

val

ue.

3. S

et L

SB

com

pare

val

ue.

4. L

oad

TS

C2

wit

h "T

oggl

e ou

tput

on

com

pare

" va

lue.

Cle

ar C

H2F

fla

g(2

step

s re

quir

ed):

5. R

ead

TS

C2.

6.

Wri

te a

logi

c "0

" to

CH

2F.

7. S

tart

Tim

er

Whe

n C

H2F

=1

add

500

usec

. del

ay &

set

for

nex

t out

put:

8.

Wai

t for

CH

2F to

go

set,

also

1st

. ste

p to

cle

ar f

lag

9. L

oad

Acc

umul

ator

wit

h lo

w h

alf

of 5

00 u

sec

dela

y.

1

0. A

dd T

CH

2L v

alue

to a

ccum

ulat

or.

1

1. S

ave

accu

mul

ator

.

12.

Loa

d ac

cum

ulat

or w

ith

hi h

alf

of 5

00 u

sec

dela

y.

MOV #$36,TSC

MOV #$F4,TCH2H

MOV #$01,TCH2L

MOV #$14,TSC2

BCLR #7,TSC2

BCLR #5,TSC

WAIT BRCLR #7,TSC2,WAIT

LDA #$F4

ADD TCH2L

TAX

LDA #1

ADC TCH2H

STA TCH2H

STX TCH2L

BCLR #7,TSC2

BRA WAIT


Timer Block Diagram

PRESCALER

PRESCALER SELECT

TCLK

INTERNAL

16-BIT COMPARATOR

PS2 PS1 PS0

16-BIT COMPARATOR

16-BIT LATCH

TCH0H:TCH0L

MS0A

ELS0B ELS0A PTE4

TOF

TOIE

INTER-

16-BIT COMPARATOR

16-BIT LATCH

TCH1H:TCH1L

16-BIT COMPARATOR

16-BIT LATCH

TCH2H:TCH2L

16-BIT COMPARATOR

16-BIT LATCH

TCH3H:TCH3L

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

TMODH:TMODL

TRST

TSTOP

TOV0

CH0IE

DMA0S

CH0F

ELS1B ELS1ATOV1

CH1IE

DMA1S

CH1MAX

CH1F

ELS2B ELS2ATOV2

CH2IE

DMA2S

CH2MAX

CH2F

ELS3B ELS3ATOV3

CH3IE

DMA3S

CH3MAX

CH3F

CH0MAX

MS0B

MS2B

16-BIT COUNTER

BUS CLOCK

MS1A

MS2A

MS3A

PTE3/TCLK

PTE4/TCH0

PTE5/TCH1

PTE6/TCH2

LOGIC

RUPTLOGIC

INTER-RUPTLOGIC

PTE5LOGIC

INTER-RUPTLOGIC

PTE6LOGIC

INTER-RUPTLOGIC

PTE7LOGIC

INTER-RUPTLOGIC

PTE7/TCH3

INTERNALBUS

TIM V2.1 9 - 12

Documents

Timer Interface Module MTT48 9 - 1 TIMER INTERFACE MODULE (TIM)