Time Varying Signals Chemistry 838

November 9, 2004 - 1 - Version 2004.2

Time Varying Signals

Chemistry 838

Thomas V. Atkinson, Ph.D. Senior Academic Specialist Department of Chemistry Michigan State University East Lansing, MI 48824

Table of Contents TABLE OF CONTENTS ............................................................................................................. 1

TABLE OF TABLES.................................................................................................................... 3

TABLE OF FIGURES.................................................................................................................. 4

1. OSCILLOSCOPE.................................................................................................................... 6 1.1. CRT...................................................................................................................................... 6 1.2. OSCILLOSCOPE SCHEMAT ..................................................................................................... 6 1.3. PROJECTION OF TWO TIME VARYING SIGNALS ....................................................................... 7 1.4. TIME SHARING THE BEAM..................................................................................................... 8 1.5. LISSAJOUS PATTERNS - VARYING PHASE ANGLE.................................................................. 9 1.6. LISSAJOUS PATTERNS - PHASE ANGLE MEASUREMENT ...................................................... 10 1.7. LISSAJOUS FIGURES - DIFFERENT FREQUENCIES ................................................................. 11

2. OSCILLOSCOPE (Y VERSUS TIME EXAMPLES)........................................................ 12 2.1. ASYNCHRONOUS SWEEP, WITH AND WITHOUT BLANKING................................................. 12 2.2. SYNCHRONIZED SWEEP....................................................................................................... 13 2.3. TRIGGERED SWEEP, SIMPLE SIGNAL ................................................................................... 14 2.4. TRIGGERED SWEEP, COMPLEX SIGNAL ............................................................................... 15 2.5. TRIGGERED SWEEP, COMPLEX SIGNAL ............................................................................... 16

3. RASTER DEVICES (TV, MONITOR) ON THE CRT ..................................................... 16 3.1. TIMING EXAMPLES.............................................................................................................. 16

3.1.1. Black and White .......................................................................................................... 17 3.1.2. Black and White (Multiple Frames Example) ............................................................. 18 3.1.3. Gray Scale ................................................................................................................... 19 3.1.4. Gray Scale (Multiple Frames Example)...................................................................... 20 3.1.5. Interlaced .................................................................................................................... 21

3.2. RASTER IMAGES.................................................................................................................. 22 3.2.1. Black and White .......................................................................................................... 22

Chemistry 838 Time Varying Signals Table of Contents


3.2.2. Gray Scale ................................................................................................................... 23 3.2.3. Interlaced .................................................................................................................... 24

4. CRT MODES SUMMARY ................................................................................................... 25

5. SWITCHES ............................................................................................................................. 26 5.1. IDEAL AND REAL ................................................................................................................. 26 5.2. MECHANICAL....................................................................................................................... 27 5.3. SOLID STATE ....................................................................................................................... 29 5.4. APPLICATIONS – MULTIVIBRATORS .................................................................................... 30

Monostable Applications........................................................................................................ 33 5.5. APPLICATIONS – ANALOG MULTIPLEXER ........................................................................... 34

6. MEASUREMENT OF TIME AND FREQUENCY ............................................................ 34 6.1. DEVICE ................................................................................................................................ 34 6.2. SIGNALS............................................................................................................................... 35 6.3. DERIVATION ........................................................................................................................ 35 6.4. REQUIREMENTS ................................................................................................................... 37 6.5. TIME BASE........................................................................................................................... 37

7. COMPUTER INTERFACE HARDWARE ........................................................................ 39 7.1. UNIPOLAR DAC.................................................................................................................. 40

7.1.1. Unipolar DAC Example (n = 4).................................................................................. 41 7.1.2. DAC Example (n = 4 with Error in Bit 2)................................................................... 42 7.1.3. DAC (Bipolar) ............................................................................................................. 44

7.2. SUCCESSIVE APPROXIMATION ADC ................................................................................... 46 7.2.1. Successive Approximation ADC Example (4 Bit Linear Search)................................ 46 7.2.2. Successive Approximation ADC Example (8 Bit Binary Search) ............................... 47 7.2.3. ADC Example 2 (8 Bit Binary Search)........................................................................ 48

7.3. DUAL SLOPE ADC .............................................................................................................. 50 7.4. FLASH ADC (2 BIT) ............................................................................................................ 52

8. MEASUREMENT AND CONTROL SYSTEMS – GENERAL ....................................... 53

9. ACQUISITION SYSTEMS (INPUT) - ANALOG ............................................................. 55 9.1. EFFECT OF RESOLUTION...................................................................................................... 55 9.2. ACQUISITION TIMING SCHEMES........................................................................................... 56 9.3. SIMPLE ADC....................................................................................................................... 57 9.4. OPERATOR TRIGGER ........................................................................................................... 59 9.5. SOFTWARE TRIGGER ........................................................................................................... 59 9.6. SIMPLE ADC WITH HARDWARE TRIGGER........................................................................... 61 9.7. PROGRAMMABLE CLOCK .................................................................................................... 62 9.8. PROGRAM ACCESS TO THE ADC AND A PROGRAMMABLE CLOCK ...................................... 63 9.9. DIRECT COUPLED CLOCK AND TRIGGER............................................................................. 65 9.10. SAMPLE/HOLD .................................................................................................................. 67 9.11. MULTIPLEXED INPUTS....................................................................................................... 68 9.12. LOCAL BUFFER, HARDWARE TRIGGER.............................................................................. 70

Chemistry 838 Time Varying Signals Table of Tables


9.13. MULTIPLE ADCS .............................................................................................................. 72 9.14. CIRCULAR BUFFERS .......................................................................................................... 73 9.15. ACQUISITION SYSTEMS - DIGITAL..................................................................................... 75

10. CONTROL OF THE EXPERIMENT, OUTPUT............................................................. 76 10.1. ANALOG............................................................................................................................ 76 10.2. DIGITAL ............................................................................................................................ 77

11. COMPUTERIZED MEASUREMENT OF TIME AND FREQUENCY ....................... 78

12. FIGURES OF MERIT FOR ACQUISITION SYSTEM COMPONENTS.................... 80 12.1. DAC ................................................................................................................................. 80 12.2. ADC ................................................................................................................................. 80 12.3. MULTIPLEXER................................................................................................................... 80 12.4. SAMPLE AND HOLD........................................................................................................... 81 12.5. COUNTER .......................................................................................................................... 81

13. INSTRUMENT SYSTEMS................................................................................................. 82

14. COMMUNICATION (A BRIEF INTRODUCTION)...................................................... 84 14.1. TWO PARTICIPANTS .......................................................................................................... 84 14.2. MANY PARTICIPANTS........................................................................................................ 85

15. TIME VARYING SIGNAL DETAILS.............................................................................. 88 15.1. VARYING DUTY CYCLE .................................................................................................... 88 15.2. SIGNAL DETAILS................................................................................................................ 89 15.3. SIGNAL DETAILS - ANOTHER PART OF THE SIGNAL............................................................ 90 15.4. ACQUISITION STRATEGIES – SCENARIO 1 .......................................................................... 91 15.5. ACQUISITION STRATEGIES – SCENARIO 2 .......................................................................... 91 15.6. ACQUISITION STRATEGIES – SCENARIO 3 .......................................................................... 92 15.7. ACQUISITION STRATEGIES – BOXCAR................................................................................ 93 15.8. ACQUISITION STRATEGIES – RECONSTRUCTING SIGNAL FROM VARIABLE WINDOWS ....... 93

16. REVISION HISTORY ..................................................................................................... 94

Table of Tables TABLE 1 - NOMINAL SWITCH CHARACTERISTICS .........................................................................................................26 TABLE 2 - DAC CIRCUIT PARAMETERS........................................................................................................................41 TABLE 3 - DAC CIRCUIT PARAMETERS (II)..................................................................................................................41 TABLE 4 - UNIPOLAR DAC EXAMPLE - TABLE OF STATES ...........................................................................................41 TABLE 5 - DAC WITH ERROR - CIRCUIT PARAMETERS.................................................................................................42 TABLE 6 - DAC WITH ERROR - CIRCUIT PARAMETERS (II)...........................................................................................42 TABLE 7 - DAC WITH ERROR – TABLE OF STATES .......................................................................................................43 TABLE 8 - BIPOLAR DAC EXAMPLE - CIRCUIT PARAMETERS ......................................................................................44 TABLE 9 - BIPOLAR DAC EXAMPLE - CIRCUIT PARAMETERS (II) ................................................................................44 TABLE 10 - BIPOLAR DAC EXAMPLE - TABLE OF STATES............................................................................................45 TABLE 11 - 4-BIT SUCCESSIVE APPROXIMATION ADC ................................................................................................46 TABLE 12 - DUAL SLOPE ADC - SWITCH CONTROL .....................................................................................................50 TABLE 13 - FLASH ADC - TABLE OF STATES ...............................................................................................................52

Chemistry 838 Time Varying Signals Table of Figures


TABLE 14 – FREQUENCY/PERIOD/TIME/COUNT METER - INTERNAL CONNECTIONS ....................................................79 TABLE 15 - NUMBER OF LINKS IN A FULLY CONNECTED NET ......................................................................................87

Table of Figures FIGURE 1 - IDEAL SWITCH ............................................................................................................................................26 FIGURE 2 - REAL SWITCH - 1ST ORDER MODEL ...........................................................................................................26 FIGURE 3 - GENERIC SWITCH WITH ELECTRONIC CONTROL .........................................................................................26 FIGURE 4 - MECHANICAL SWITCH ................................................................................................................................27 FIGURE 5 - BOUNCE EXAMPLE .....................................................................................................................................28 FIGURE 6 – MONOSTABLE MULTIVIBRATOR CONFIGURATION .....................................................................................30 FIGURE 7 - ASTABLE MULTIVIBRATOR CONFIGURATION .............................................................................................30 FIGURE 8 - MONOSTABLE MULTIVIBRATOR TIMING ....................................................................................................31 FIGURE 9 - ASTABLE MULTIVIBRATOR TIMING............................................................................................................32 FIGURE 10 - MONOSTABLE MULTIVIBRATOR (1 SHOT) SYMBOL..................................................................................33 FIGURE 11 – 1 SHOT - PULSE SHAPING .........................................................................................................................33 FIGURE 12 – 1 SHOT - PULSE STRETCHING ...................................................................................................................33 FIGURE 13 – 1 SHOT - PULSE SHORTENING ..................................................................................................................33 FIGURE 14 - COUPLED MONOSTABLES .........................................................................................................................33 FIGURE 15 - COUPLED 1 SHOTS - TIMING .....................................................................................................................33 FIGURE 16 - ANALOG MULTIPLEXER............................................................................................................................34 FIGURE 17 - FREQUENCY/PERIOD MEASUREMENT .......................................................................................................35 FIGURE 18 - FREQUENCY/PERIOD MEASUREMENT TIMING ..........................................................................................35 FIGURE 19 - CRYSTAL STABILIZED TIME BASE ............................................................................................................38 FIGURE 20 - GENERALIZED INTERFACE ........................................................................................................................39 FIGURE 21 - UNIPOLAR DAC .......................................................................................................................................40 FIGURE 22 – UNIPOLAR DAC EXAMPLE - TRANSFER FUNCTION..................................................................................42 FIGURE 23 - DAC WITH ERROR - TRANSFER FUNCTION ...............................................................................................43 FIGURE 24 - BIPOLAR DAC CONFIGURATION...............................................................................................................44 FIGURE 25 - BIPOLAR DAC TRANSFER FUNCTION .......................................................................................................45 FIGURE 26 – SUCCESSIVE APPROXIMATION ADC ........................................................................................................46 FIGURE 27 - 4-BIT ADC LINEAR SEARCH ....................................................................................................................47 FIGURE 28 - DUAL SLOPE ADC....................................................................................................................................50 FIGURE 29 - DUAL SLOPE ADC - OPERATION ..............................................................................................................51 FIGURE 30 - GENERALIZED EXPERIMENT .....................................................................................................................53 FIGURE 31 - ACQUISITION WINDOW.............................................................................................................................54 FIGURE 32 - RESOLUTION - 3 BITS................................................................................................................................55 FIGURE 33 - RESOLUTION - 4 BITS................................................................................................................................55 FIGURE 34 - RESOLUTION - 6 BITS................................................................................................................................56 FIGURE 35 - EQUAL ACQUISITION INTERVALS .............................................................................................................56 FIGURE 36 - VARIED ACQUISITION INTERVALS ............................................................................................................56 FIGURE 37 EXPONENTIAL ACQUISITION INTERVALS ....................................................................................................56 FIGURE 38 - MULTIPLE SIGNALS ..................................................................................................................................57 FIGURE 39 - MULTIPLEXED ADC .................................................................................................................................57 FIGURE 40 - SIMPLE ADC ............................................................................................................................................57 FIGURE 41 - SIMPLE ADC - TIMING ISSUES..................................................................................................................58 FIGURE 42 - SOFTWARE TRIGGER TIMING....................................................................................................................61 FIGURE 43 - SIMPLE ADC WITH HARDWARE TRIGGER.................................................................................................61 FIGURE 44 - PROGRAMMABLE CLOCK..........................................................................................................................62 FIGURE 45 – ADC, REAL TIME CLOCK, AND HARDWARE TRIGGER .............................................................................64 FIGURE 46 - ACQUISITION SYSTEM WITH DIRECT COUPLED CLOCK AND TRIGGER......................................................66 FIGURE 47 - SAMPLE AND HOLD ..................................................................................................................................67 FIGURE 48 - SAMPLE AND HOLD – TIME COURSE.........................................................................................................67 FIGURE 49 - SAMPLE AND HOLD AND ADC..................................................................................................................68 FIGURE 50 - ADC, SAMPLE/HOLD, AND MULTIPLEXER ...............................................................................................69

Chemistry 838 Time Varying Signals Table of Figures


FIGURE 51 - ACQUISITION SYSTEM WITH LOCAL BUFFER ............................................................................................71 FIGURE 52 - MULTIPLE ADC........................................................................................................................................73 FIGURE 53 - CIRCULAR BUFFER ...................................................................................................................................73 FIGURE 54 - PRE, MID, POST TRIGGERS........................................................................................................................73 FIGURE 55 - USING A LINEAR BUFFER AS A CIRCULAR BUFFER ...................................................................................75 FIGURE 56 - DIGITAL INPUT .........................................................................................................................................75 FIGURE 57 - DIGITAL INPUT II ......................................................................................................................................76 FIGURE 58 - SIMPLE DAC ............................................................................................................................................76 FIGURE 59 - DIGITAL OUTPUT......................................................................................................................................77 FIGURE 60 - EXTERNAL FREQUENCY/PERIOD/TIME/COUNT METER.............................................................................78 FIGURE 61 - INTERNAL FREQUENCY/PERIOD/TIME/COUNT METER..............................................................................79 FIGURE 62 - SIMPLE COMPUTERIZED ACQUISITION SYSTEM ........................................................................................82 FIGURE 63 - INTELLIGENT INSTRUMENT SYSTEM .........................................................................................................82 FIGURE 64 - DISTRIBUTED INSTRUMENT SYSTEM.........................................................................................................83 FIGURE 65 - A VERY DISTRIBUTED INSTRUMENT SYSTEM...........................................................................................83 FIGURE 66 - ONE TO ONE COMMUNICATION ................................................................................................................84 FIGURE 67 - PHYSICAL CONNECTIONS..........................................................................................................................84 FIGURE 68 – ONE-TO-MANY COMMUNICATION ...........................................................................................................85 FIGURE 69 - MULTICAST ..............................................................................................................................................85 FIGURE 70 - BROADCAST .............................................................................................................................................85 FIGURE 71 - COMMUNICATION TOPOLOGIES ................................................................................................................86 FIGURE 72 - HIERARCHY OF STARS ..............................................................................................................................87 FIGURE 73 - MIXED TOPOLOGIES .................................................................................................................................87 FIGURE 74 - HIGH DUTY CYCLE SIGNAL......................................................................................................................88 FIGURE 75 - LOW DUTY CYCLE SIGNAL.......................................................................................................................88 FIGURE 76 - LOWER DUTY CYCLE SIGNAL...................................................................................................................89 FIGURE 77 - LIMIT X-RANGE .......................................................................................................................................89 FIGURE 78 - LIMIT X-RANGE .......................................................................................................................................90 FIGURE 79 - LIMIT X AND Y RANGE.............................................................................................................................90

Chemistry 838 Time Varying Signals Oscilloscope


1. Oscilloscope The figures in this section are from Section 3-4 and following in "Making the Right Connection"

1.1. CRT

1.2. Oscilloscope Schemat



1.3. Projection of two time varying signals



1.4. Time Sharing the Beam



1.5. Lissajous Patterns - Varying Phase Angle



1.6. Lissajous Patterns - Phase Angle Measurement

sin Θ = c/b



1.7. Lissajous Figures - Different Frequencies

Horizontal to Vertical Frequencies a.) 1:1 b.) 2:1 c.) 1:5 d.) 10:1 e.) 5:3

Chemistry 838 Time Varying Signals Oscilloscope (y versus Time Examples)


2. Oscilloscope (y versus Time Examples) 2.1. Asynchronous Sweep, With and Without Blanking



2.2. Synchronized Sweep



2.3. Triggered Sweep, Simple Signal



2.4. Triggered Sweep, Complex Signal

Chemistry 838 Time Varying Signals Raster Devices (TV, Monitor) on the CRT


2.5. Triggered Sweep, Complex Signal

3. Raster Devices (TV, Monitor) on the CRT 3.1. Timing Examples



3.1.1. Black and White

-15

-5

5

15

0 100 200 300 400 500 600

Ver

tical

-15

-5

5

15

0 100 200 300 400 500 600

Hor

izon

tal

-2

3

8

0 100 200 300 400 500 600

Time

Bea

m



3.1.2. Black and White (Multiple Frames Example)

-15

-5

5

15

0 200 400 600 800 1000

Ver

tical

-15

-5

5

15

0 200 400 600 800 1000

Hor

izon

tal

-2

3

8

0 200 400 600 800 1000

Time

Bea

m



3.1.3. Gray Scale

-15

-5

5

15

0 100 200 300 400 500 600

Ver

tical

-15

-5

5

15

0 100 200 300 400 500 600

Hor

izon

tal

-2

3

8

0 100 200 300 400 500 600

Time

Bea

m



3.1.4. Gray Scale (Multiple Frames Example)

-15

-5

5

15

0 200 400 600 800 1000 1200

Ver

tical

-15

-5

5

15

0 200 400 600 800 1000 1200

Hor

izon

tal

-2

3

8

0 200 400 600 800 1000 1200

Time

Bea

m



3.1.5. Interlaced

-15

-5

5

15

0 200 400 600 800 1000 1200

Ver

tical

-15

-5

5

15

0 200 400 600 800 1000 1200

Hor

izon

tal

-2

3

8

0 200 400 600 800 1000 1200

Time

Bea

m



3.2. Raster Images

3.2.1. Black and White

1 2 3 4 5 6 7 8Pixel

1

2

3

4

5

6

7

8

Hor

izon

tal L

ine

Raster (8 x 8) DisplayBlack and White

Horizontal flyback

Verticalflyback

Raster8x8.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University



3.2.2. Gray Scale

1 2 3 4 5 6 7 8Pixel

1

2

3

4

5

6

7

8

Hor

izon

tal L

ine

Raster (8 x 8) DisplayGray Scale

Horizontal flyback

Verticalflyback

Raster8x8gray.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University



3.2.3. Interlaced

1 2 3 4 5 6 7 8Pixel

1

2

3

4

5

6

7

8

Hor

izon

tal L

ine

Raster (8 x 8) DisplayInterlaced

Gray Scale

Horizontal flyback

Verticalflyback

Raster8x8grayinterlaced.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University

Chemistry 838 Time Varying Signals CRT Modes Summary


4. CRT Modes Summary

Type Horizontal Drive Vertical Drive Beam Drive

X-Y plot remote signal source remote signal source on

Time base Oscope (Simplest) local sweep generator (free running) remote signal source on

Time base Oscope (Simple) local sweep generator (free running) remote signal source Blanked on flyback

Time base Oscope Typical) local sweep generator (Triggered) remote signal source Blanked on flyback, when armed

Raster (TV, Monitor) local sweep generator local sweep generator remote source (Beam Intensity contains the visual information for a given point (pixel) in the image being displayed.)

The longer the persistence, the lower the refresh rate needed to keep an image visible. The longer the persistence, the slow the motion (i.e. the changes from one frame to the next, can be.

Chemistry 838 Time Varying Signals Switches


5. Switches 5.1. Ideal and Real

GenericSwitch_01.cdr 11-Oct-2004

Symbol

VS

iS

Open

Closed Figure 1 - Ideal Switch

RealSwitch_01.cdr 11-Oct-2004

VS

RSOpen

RSClosed

CS

iS

Figure 2 - Real Switch - 1st Order Model

Table 1 shows nominal values for several of the figures of merit of switches. Any real switch also has a maximum value of VS. If a switch is subjected to voltages greater than the limit, the switch will arc and even catastrophically destruct. Another figure of merit is the maximum amount of current that can be put through the switch. Switches vary from a maximum current capacity of milliamps to many amps.

Table 1 - Nominal Switch Characteristics

Switch Type RSClosed RSOpen Time to Switch

Ideal 0 ∞ 0

Mechanical <0.1Ω >100MΩ milliseconds

Solid State <200Ω >1011Ω microseconds

Figure 3 shows two symbols for switches that can be switched between the open and closed states by electronic rather than manual means. Such devices are used often in modern instrumentation.

GenericSwitch_02.cdr 11-Oct-2004

Switchein

ein

eSC

eout

eout

eSC

SwitchControl

Figure 3 - Generic Switch with Electronic Control



5.2. Mechanical

Figure 4 - Mechanical Switch



B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

B

C

A

Mechanical Single Pole Double Throw SwitchTransition from one position to the other

t1 t2 t3 t4

t5 t6 t7 t8

t9 t10 t11 t12

t13 t14 t15 t16

Rigidt t Breakt t Transition1 2

3 8

®®

9 16 t t Bounce®

Bounce.cdr 30-SEP-2000 T V Atkinson Department of Chemistry Michigan State University

Figure 5 - Bounce Example



5.3. Solid State SolidStateSwitch.cdr 30-SEP-2000 T V Atkinson Department of Chemistry Michigan State University

Solid State Switch

5V R = 1K

R = 1KTHRESHDISC

Vout

Vout

SwitchDriverSwitch

2.5V

0V

open

closed

Switch

t1 t2

ton toff

t4

t3



5.4. Applications – Multivibrators Monostable.cdr 30-SEP-2000

V

RTHRESH

TRIG

DISC

Integrated Circuit

OUT

eref1eC1

C eref0

eC0

to Close

to Open

Open

Close

SwitchControl

SwitchDriver

Monostable Configuration Figure 6 – Monostable Multivibrator Configuration

Astablea.cdr 14-Oct-2004

V

R1

R2

THRESH

TRIG

DISC

Integrated Circuit

OUT

eref1eC1

C

eref0

eC0

to Close

to Open

Open

Close

SwitchControl

SwitchDriver

Figure 7 - Astable Multivibrator Configuration



VC

0

TRIGeref1

eC1

eref0

eC0

Open

Close

Switch(OUT)

1

2

3

4

5

Monostabletime.cdr 30-SEP-2000

Assume C is discharged at t=0

Limitations: a.) Long = RC 1.) Leakage of C 2.) Noise on thresholds b.) Short = RC 1.) Speed of comparators 2.) Speed of switch 3.) Speed of discharge 4.) Stray capacitance

t

t

6

Figure 8 - Monostable Multivibrator Timing



Open

Close

Switch(OUT)

eC1

eC0

TRIGeref1

VCeref1

0

eref0

1

2 6

34

5

7

Astabletime.cdr 30-SEP-2000

Figure 9 - Astable Multivibrator Timing



Monostable Applications Monostable_01.cdr 8-Oct-2003

R

tr

Q1S

_Q

C Figure 10 - Monostable Multivibrator (1

Shot) Symbol

Monostable_02.cdr 8-Oct-2003

trthreshold

Q Figure 11 – 1 Shot - Pulse Shaping


tr

Q Figure 12 – 1 Shot - Pulse Stretching


tr

Q Figure 13 – 1 Shot - Pulse Shortening


RA

tr

Q1S

A

IN

B

_Q

CA RB

tr

Q1S

_Q

CB

Figure 14 - Coupled Monostables


IN

QA

QB

tdelay

QA

Figure 15 - Coupled 1 Shots - Timing

Figure 14 illustrates one of many ways to couple more than one monostable together. Figure 15 shows the resultant timing for the configuration. Notice that every input pulse on In results in a pulse being generated on QB that will have the leading edge delayed by tdelay after the leading edge of the input pulse. Notice also that the signal on In are not periodic nor are the pulses of the

Chemistry 838 Time Varying Signals Measurement of Time and Frequency


same width. The delay, tdelay, and the width of the pulses on QA and QB are functions of RA and CA alone. The width of the pulse is a function of RB and CB alone.

Collections of monostables may be constructed that produce complicated timing sequences.

5.5. Applications – Analog Multiplexer

eout

e3

e2

e1

e0

b2b3

SwitchControl

b1 b0

Exam02_1.cdr

Rf

R1

R2

R3

R0s0

s1

s2

s3

Figure 16 - Analog Multiplexer

Let bi = 0 if switch Si is open.

Let bi = 1 if switch Si is closed.

If 3210f RRRRR ==== , then ∑=

−=+++−=3

0iii33221100out ebebebebebe .

If only one switch, i.e. Sk, is allowed to be closed at a time then the transfer function for Figure 16 becomes the following.

kout ee −= where k can be 0, 1, 2, 3.

Thus, this circuit selects, based on a binary number, b3b2b1b0, one of a set of signals and presents the inverse of that signal at the output of the circuit. Notice that only one of the bits, bi, will be one at a time.

6. Measurement of Time and Frequency 6.1. Device The circuit shown in Figure 17 can be used to measure time and frequency.



FreqMeter_01.cdr 7-Oct-2003

egi

egc

ego

estart estop

GateControl

Gate Counter

Figure 17 - Frequency/Period Measurement

The Gate Control in Figure 17 is a circuit whose output, egc, will change state from Closed to Open upon detecting an edge (rising in the example) on estart. The output of the circuit will change from Open to Closed on the next edge of the appropriate type (rising in this example) on estop. The output of the gate is presented to the counter. Thus, the counter will count edges (rising in this example) of the signal, egi, coming from the gate when the gate is Open.

6.2. Signals An important case is that with the two inputs to the Gate Control tied together, i.e. driven by the same signal, egcin. Figure 18 illustrates the behavior of the device when presented the two periodic signals egi and egcin.

FreqMeter_02.cdr 7-Oct-2003

egi

pgi

0

1

0

1ego

pgi

tstart tstop

0

1e =e =gcin start estop

∆t

egc Closed

Open

Figure 18 - Frequency/Period Measurement Timing

6.3. Derivation The following two relations are true in general.



periodfrequency 1

=

unittimeriodsNumberofPefrequency =

In the case of the Frequency/Period Measurement device as described here, the following will be true. In fact, the basis of all of the measurements accomplished with this device is the measurement of ∆t.

gcstartstop pttt =−=∆

If the frequencies of the two input signals are integer multiples of each other, the following is true. Such a relationship of the two signals will be assumed for the derivation. The error in the measurement of ∆t due to this assumption is at most one period of egi.

gcgiCounts ppn =

These can be arranged as follows.

gcgi

Counts

ffn 1

=

gcCountsgi fnf =

giCountsgc pnp =

gc

giCounts f

fn =

gi

gcCounts p

pn =

These results are the basis for the five measurement devices outlined in the table below.



Equation Device Conditions

gcCountsgi fnf = Frequency Meter fgc is known

giCountsgc pnp = Period Meter fgc is known

Countsgc

gi nff

= Frequency Ratio Meter Neither fgc nor fgi is known

Countsgi

gc npp

= Period Ratio Meter Neither fgc nor fgi is known

giCountsstartstop pntt =− Elapsed Time Meter fgc is known

Of course, egi and egcin are not always integral multiples of each other. Analysis of the possibilities will show that the error in the measurement of ∆t is one period of egi. This translates into the error in the 5 relationships in the table being at most 1 count when the two signals are not integral multiples.

6.4. Requirements The following constrains are required when applying the above to measurements.

1. The Gate control signal is always the slower, i.e. fgi > fgc. Otherwise, the number of counts accumulated will only be 0 or 1.

2. If one of the two signals is known, you can measure the other. If neither is known, you can only determine the ratio of the two unknown frequencies or the two unknown periods.

3. There is always an error in the measurement of ±1 count. Therefore, the number of counts should be as large as possible, i.e. fgi >> fgc to minimize the error of the measurement.

4. Both egi and egcin are periodic, except in the case of elapsed time measurement when only egi is periodic.

5. The accuracy and precision of the measurement is solely dependent on the accuracy and precision of the known frequency or period.

6.5. Time Base When measuring frequency or period, a stable, precise, accurate time base is needed as the standard or known signal. Figure 19 illustrates such a time base. The heart of the time base is an oscillator that is stabilized by a piezo electric crystal. Precisions and accuracies of parts per million and better can be achieved. In extreme cases, the temperature of the crystal will have to be stabilized. An appropriate output is chosen and connected to the Gate Input or the Gate Control.



10 MHz Osc.PiezoElectricCrystal

10 MHz (100 nanosecond)

1 MHz (1 microsecond)

100 KHz (10 microsecond)

10 KHz (100 microsecond)

1 KHz (1 millisecond)

100 Hz (10 millisecond)

10 Hz (10 millisecond)

1 Hz (1 second)

0.01667 (1 minute) Hz

0.0002778 (1 hour) Hz

0.00001547 (1 day) Hz

0.0000016534 (1 week) Hz

/10

/10

/10

/10

/10

/10

/10

/10

/6

/10

/6

/6

/4

/7

TimeBase.cdr 10-Oct-2004

Figure 19 - Crystal Stabilized Time Base

Digital clocks and watches are based on this technique with the states of the slower stages displayed on the face of the device. Typically, these digital time pieces will display months. This, of course, requires more logic to appropriately keep track of the 28, 29, 30, 31 day months and leap years. More flexible time bases will be discussed in the Programmable Clock Section.

Chemistry 838 Time Varying Signals Computer Interface Hardware


7. Computer Interface Hardware Interface0.cdr 19-Oct-2004

ADC

Busy

D ,...,D0 n-1

Convert

DAC

D ,...,D0 n-1

Latch

Control

In Out

World Computer

Latch

Control

InOut

ein

eout

D

Load Data

D

Data Ready

Figure 20 - Generalized Interface

The above is the generalized of interface between the computer and the outside world. All interfaces to the external world are variations of the four modes illustrated.



7.1. Unipolar DAC

eout

ein

b2b3

SwitchControl

b1 b0

DAC.cdr

Rf

R1

R2

R3

R0s0

s1

s2

s3

Figure 21 - Unipolar DAC

Define the following binary variables.

bi = 0 if switch Si is open bi = 1 if switch Si is closed

Then the following is true

∑−

=

−=1

0

n

i i

ifinout R

bRee

If the following is true,

iiRR2

=

then

in

ii

finout b

RR

ee 21

0∑−

=

−=

Notice that eout is an analog quantity, R

Re f

in− is an analog quantity, and in

iib 2

1

0∑−

=

is a binary

number.

The DAC outputs a voltage that ranges from 0 to (2n-1)* emax. The following defines emax. nf

in RR

ee 2max −=



or

n

fin e

RRe −−= 2max

Thus, as the input of the DAC goes from 0 to 2n-1, eout goes from 0 to max212 en

n − in 2n steps.

7.1.1. Unipolar DAC Example (n = 4)

Table 2 - DAC Circuit Parameters

Parameter Value

Rf/R 0.0625

ein -1 volt

Table 3 - DAC Circuit Parameters (II)

Parameter i 2i

R0 0 1

R1 1 2

R2 2 4

R3 3 8

Table 4 - Unipolar DAC Example - Table of States

Decimal b0 b1 b2 b3 Binary Multiplier Decimal Output

0 0 0 0 0 0 0 0.0000

1 1 0 0 0 1 1 0.0625

2 0 1 0 0 2 2 0.1250

3 1 1 0 0 3 3 0.1875

4 0 0 1 0 4 4 0.2500

5 1 0 1 0 5 5 0.3125

6 0 1 1 0 6 6 0.3750

7 1 1 1 0 7 7 0.4375

8 0 0 0 1 8 8 0.5000

9 1 0 0 1 9 9 0.5625

10 0 1 0 1 10 10 0.6250

11 1 1 0 1 11 11 0.6875

12 0 0 1 1 12 12 0.7500

13 1 0 1 1 13 13 0.8125

14 0 1 1 1 14 14 0.8750

15 1 1 1 1 15 15 0.9375



4 Bit DAC Output

0.00.10.20.30.40.50.60.70.80.91.0

0 5 10 15

Binary Input Value

Out

put V

olta

ge (-

RF*

Ein*

(Sum

(1/R

i))

Actual OutputIdeal Output

Figure 22 – Unipolar DAC Example - Transfer Function

7.1.2. DAC Example (n = 4 with Error in Bit 2)

Table 5 - DAC with Error - Circuit Parameters

Parameter Value

Rf/R 0.0625

ein 1 volt

Table 6 - DAC with Error - Circuit Parameters (II)

Parameter i 2i

R0 0 1

R1 1 2

R2 1.584963 3

R3 3 8



Table 7 - DAC with Error – Table of States


0 0 0 0 0 0 0 0.0000

1 1 0 0 0 1 1 0.0625

2 0 1 0 0 2 2 0.1250

3 1 1 0 0 3 3 0.1875

4 0 0 1 0 4 4 0.1875

5 1 0 1 0 5 5 0.2500

6 0 1 1 0 6 6 0.3125

7 1 1 1 0 7 7 0.3750

8 0 0 0 1 8 8 0.5000

9 1 0 0 1 9 9 0.5625

10 0 1 0 1 10 10 0.6250

11 1 1 0 1 11 11 0.6875

12 0 0 1 1 12 12 0.6875

13 1 0 1 1 13 13 0.7500

14 0 1 1 1 14 14 0.8125

15 1 1 1 1 15 15 0.8750

4 Bit DAC Output with Error in Bit 2

0.00.10.20.30.40.50.60.70.80.91.0

0 5 10 15

Binary Input Value

Out

put V

olta

ge (-

RF*

Ein*

(Sum

(1/R

i))

Actual OutputIdeal

Figure 23 - DAC with Error - Transfer Function



7.1.3. DAC (Bipolar)

eout

ein

b2b3

SwitchControl

b1 b0

DAC1.cdr

Rf

R1

R2

R3

R0s0

s1

s2

s3

RoffsetVoffset

Figure 24 - Bipolar DAC Configuration

∑−

=

−−=1

0

)(n

i offset

foffset

i

ifinout R

RV

RbRee

Again, assuming the following.

RR ii

−= 2 then

offset

foffset

in

ii

finout R

RVb

RR

ee −−= ∑−

=

)2(1

0

Table 8 - Bipolar DAC Example - Circuit Parameters

Parameter Value

Rf/R 0.0625

ein -1 volt

offset

foffset R

RV 0.5 volt

Table 9 - Bipolar DAC Example - Circuit Parameters (II)

Parameter i 2i

R0 0 1

R1 1 2

R2 2 4

R3 3 8



Table 10 - Bipolar DAC Example - Table of States


0 0 0 0 0 0 0 -0.5000

1 1 0 0 0 1 1 -0.4375

2 0 1 0 0 2 2 -0.3750

3 1 1 0 0 3 3 -0.3125

4 0 0 1 0 4 4 -0.2500

5 1 0 1 0 5 5 -0.1875

6 0 1 1 0 6 6 -0.1250

7 1 1 1 0 7 7 -0.0625

8 0 0 0 1 8 8 0.0000

9 1 0 0 1 9 9 0.0625

10 0 1 0 1 10 10 0.1250

11 1 1 0 1 11 11 0.1875

12 0 0 1 1 12 12 0.2500

13 1 0 1 1 13 13 0.3125

14 0 1 1 1 14 14 0.3750

15 1 1 1 1 15 15 0.4375

4 Bit DAC Output

-0.5-0.4-0.3-0.2-0.10.00.10.20.30.40.5

0 5 10 15

Binary Input Value

Out

put V

olta

ge (-

RF*

Ein*

(Sum

(1/R

i))

Actual OutputIdeal Output

Figure 25 - Bipolar DAC Transfer Function



7.2. Successive Approximation ADC

ADC0.cdr 25-Oct-2000

Number Generator/Controller

n-Bit Register

Busy

ConverteIn

ea e < e ?a b

eb

eDAC

Answer(n-Bit)

DAC

Switch Controls

Figure 26 – Successive Approximation ADC

7.2.1. Successive Approximation ADC Example (4 Bit Linear Search) In this case a staircase is generated by incrementing a counter at a set rate until the generated voltage just exceeds the unknown voltage. Figure 27 is an example of how a 4 Bit ADC would operate. The bipolar 4-bit DAC from above is used to implement the 4-bit ADC.

1. Number Generator sets the counter to zero 2. Assert Convert to start process, raise Busy. 3. Number Generator adds 1 to the counter up at zero 4. If ea<eb, continue and go to Step 3, i. e. next count 5. If ea>eb, Done. Stop process, lower Busy. 6. Answer is the current contents of the n-bit Register.

Table 11 - 4-Bit Successive Approximation ADC

Signal Actual Voltage Steps required to get to answer

Measured Voltage

Unknown 1 0.26 13 0.3125

Unknown 2 -0.42 2 -0.3750



4 Bit DAC Output

-0.5-0.4-0.3-0.2-0.10.00.10.20.30.40.5

0 5 10 15

DAC Input Value (Step)

DA

C O

utpu

t (vo

lts)

DAC OutputUnknown 1Unknown 2

Figure 27 - 4-Bit ADC Linear Search

7.2.2. Successive Approximation ADC Example (8 Bit Binary Search)

• Start with MSB • Turn on bn.. Is eDAC > eunk?

Yes – turn off bn No – Leave bn turned on

• Turn on bn-1. Is eDAC > eunk? Yes – turn off bn-1 No – Leave bn-1 turned on

• Continue through n = 0

Parameter Value

Increment 0.00390625

Unknown 0.31

number of bits 8



Step 0 1 2 3 4 5 6 7 8

Bit Position 7 6 5 4 3 2 1 0

Delta 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 0.00390625

Step 0 1 2 3 4 5 6 7 8

Trial Value 0 0.5 0.25 0.375 0.3125 0.28125 0.296875 0.3046875 0.30859375

Sum 0 0 0.25 0.25 0.25 0.28125 0.296875 0.3046875 0.30859375

Bit Value 1 0 1 1 0 0 0 0

Step1StepStep DeltaSumvalue trial += −

Binary Search ADC

00.10.20.30.40.50.60.70.80.9

1

0 1 2 3 4 5 6 7 8

Step

Volta

ge Trial ValuesSumUnknown Voltage

7.2.3. ADC Example 2 (8 Bit Binary Search)

Parameter Value

Increment 0.00390625

Unknown 0.66

number of bits 8



Step 0 1 2 3 4 5 6 7 8

Bit Position 7 6 5 4 3 2 1 0

Delta 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 0.00390625

Step 0 1 2 3 4 5 6 7 8

Trial Value 0 0.5 0.75 0.625 0.6875 0.65625 0.671875 0.6640625 0.66015625

Sum 0 0.5 0.5 0.625 0.625 0.65625 0.65625 0.65625 0.65625

Bit Value 0 1 0 1 0 1 1 1

Binary Search ADC

00.10.20.30.40.50.60.70.8

0 1 2 3 4 5 6 7 8

Step

Volta

ge Trial ValuesSumUnknown Voltage



7.3. Dual Slope ADC

eintegrator

eunknown

eknown

Control

ADCDualSlope.cdr

ecomparator

C

R1

R0s0

s1 sc

Figure 28 - Dual Slope ADC

Table 12 - Dual Slope ADC - Switch Control

Switch t0 tintegrate tdischarge (ta, tb, tc)

sc closed open open

s0 open closed open

s1 open open closed

( ) integrate0

unknownintegrateintegrator t

CRete −=

( ) discharge1

knownintegrateintegrator t

CRete −=

( ) discharge1

knownintegrate

0

unknownintegrateintegrator t

CRe t

CRete −=−=

10 RR =

dischargeknown

integrateunknown t

RCe t

RCe

−=−

dischargeknownintegrateunknown te te =

integrate

dischargeknownunknown t

te e =



eintegrator

Time

0

0

ADCDualSlope2.cdr

tintegratet0 tc

tc

tb

ta

tb

ta

Time

ecomparator

0

1

Time

ecomparator

0

1

Time

ecomparator

0

1

Equal Slopes

Figure 29 - Dual Slope ADC - Operation



7.4. Flash ADC (2 Bit)

eunknown

ADCFlash.cdr

e0

b0

b1e1

e2

OVERFLOW

____________UNDERFLOW

R

R

R

R

Table 13 - Flash ADC - Table of States

UNDERFLOW OVEROW e0 e1 e2 b0 b1

eref < eunknown 1 1 1 1 1 1 1

¾ eref < eunknown < eref 1 0 1 1 1 1 1

½ eref < eunknown < ¾ eref 1 0 1 1 0 1 0

¼ eref < eunknown < ½ eref 1 0 1 0 0 0 1

0 < eunknown < ¼ eref 1 0 0 0 0 0 0

eunknown < 0 0 0 0 0 0 0 0

Chemistry 838 Time Varying Signals Measurement and Control Systems – General


8. Measurement and Control Systems – General

mf2,1

cf1,2

mf1,3

mf1,2

mf1,1

mf3,2

mf3,1cf1,1cf2,1

Con

trol

Mea

sure

men

t

Physical System

Inputtransducer

Outputtransducer

Interface

MeasuremenControlt.cdr 1-Nov-2004

Computer Data Store

cf2,2 cf1,3

Scientist/Engineer

mf3,3 mf1,4

Figure 30 - Generalized Experiment

An underlying goal of science and engineering is the understanding of physical systems. An important aspect of the search for this understanding is making observations of the physical system under study. Sometimes various aspects, e. g. temperature, pressure, of the system are controlled as the measurements are being made. Figure 30 is a generic picture of the modern experiment with both measurement and control. These observations are then used to discover the principles of behavior of the system.

The measurement side of the experiment starts with a set of input transducers, mfj,1 that are placed “in” the system being studied. Each transducer converts a system parameter, pj, of interest, into a new quantity that is more amenable to measurement. Each transducer has a transfer function that gives the value of the output quantity as a function of the input quantity as seen below. The transducer transforms the information from one data domain to another.

))(t(pf)(ty ijj,1mij =

For some parameters additional transformations are made by other domain converters, mfj,k. Thus, complete data stream yields a value that is the set of nested transfer functions, which in general is the following.

)))(t(pf(f(f)(ty ijj,1m1-kj,mkj,mij ••••••=

Chemistry 838 Time Varying Signals Measurement and Control Systems – General


where k = 1 to k, and n is the number of domain converters for this measurement stream.

The following is an example for the first measurement stream of Figure 30, which has three conversions before reaching the interfaces.

))))(t(pf(f(f)(ty i11,1m1,2m1,3mi1 =

The interface performs the final domain conversion converts the quantity being measured into digital form, if this has not already happened, and gates the results into the computer to be stored or analyzed in real time. This section focuses on various hardware systems used as interfaces acquiring the quantities and recording the values for later analysis. Typically, sets of observations, i. e. measurements of the values of various parameters of the system, are made by the experimenter as the state of the system changes. Thus, the process results in a set of observations that can be represented as follows.

y1(t1), y2(t1), …, yq(t1)

y1(t2), y2(t2), …, yq(t2)

…

y1(tn), y2(tn), …, yq(tn)

In the above representation, measurements of the values, yi, of q parameters of the system are made at n different times. Time is always a dependent variable in experimentation since the measurements have to be made in real time. The times, ti, of the observations may often be correlated with some other parameter. As an example, if the observation is the intensity of the light coming out of a monochromator and the wavelength is being scanned over time, the time values can be related to the values of the wavelength. The result is a spectrum.

StandardWindow.cdr 20-JUL-1997

ymin

tmin tmax(x )min ( )xmax

ymax

∆y

∆t(∆x)

Figure 31 - Acquisition Window

Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog


An experiment can be thought of a series of measurements of one or more dependent variables with time as the independent variable. An acquisition window, i. e. Figure 31, describes how the data is acquired for a given dependent variable. In essence, the measurement process is the discovery of the set of grid points of the acquisition window that are the closest to the signal or parameter being measured. Of course, what actually happens is that the point nearest the physical parameter for at tmin is determined and then that for the next time increment, etc. sequentially in time across the window.

The goal is to optimize the window so that the signal being acquired fills the window giving the maximum resolution possible. The window is defined by the choices of the parameters tmin, tmax, ∆t, ymin, ymax, and ∆y. The choices are constrained by the needs of the experiment and the abilities of the acquisition system. Figure 31 shows a constant ∆t, which is the most common strategy. Figure 35 contains an example of an acquisition using equal acquisition intervals. Figure 37 and Figure 36 suggest other, nonlinear strategies that may be desirable. The ultimate goal is to gather the most information possible about the signal of interest. More data points are desired for the portion of a signal that is changing more rapidly.

The implied quantized nature of the measurements in this discussion is slanted toward the use of Analog to Digital Converters to make the measurements. However, the use of analog oscilloscope, analog recorders, and manual recording to acquire a set of data is analogous. In those cases the ∆t and ∆y are the horizontal and vertical resolutions of the analog device. The best results occur for these devices when the signal being measured fills the oscilloscope display, the width of the recorder, etc. That is, the best results are when the signal fills the acquisition window.

Another important consideration is the specification of tmin. Typically, the acquisition a signal is to begin at a particular time. Identifying that the time, i.e. the trigger event, has occurred must cause the acquisition to begin.

9. Acquisition Systems (Input) - Analog 9.1. Effect of Resolution

000

001

010

011

100

101

110

111

1000

0.000

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

0 5 10 15 20 25Time

Am

plitu

de(D

ecim

al)

0

1

2

3

4

5

6

7

80 5 10 15 20 25

Am

plitu

de(B

inar

y)

AnalogDigitized

Figure 32 - Resolution - 3 Bits

0000

0010

0100

0110

1000

1010

1100

1110

10000

0.000

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

0 5 10 15 20 25Time

Am

plitu

de(A

nalo

g)

0

2

4

6

8

10

12

14

160 5 10 15 20 25

Am

plitu

de(B

inar

y)

AnalogDigitized




000000

001000

010000

011000

100000

101000

110000

111000

1000000

0.000

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

0 5 10 15 20 25Time

Am

plitu

de(A

nalo

g)

0

8

16

24

32

40

48

56

640 5 10 15 20 25

Am

plitu

de(B

inar

y)

AnalogDigitized


9.2. Acquisition Timing Schemes

-2

0

2

4

6

8

10

12

0 5 10 15 20 25 30

Time

Am

plitu

de

SignalTimebase

Figure 35 - Equal Acquisition Intervals

-2

0

2

4

6

8

10

12

0 10 20 30 40 50 60 70 80

Time

Am

plitu

de

SignalTimebase

Figure 36 - Varied Acquisition Intervals

-2

0

2

4

6

8

10

0 20 40 60 80 100 120 140

Time

Am

plitu

de

SignalTimebase

Figure 37 Exponential Acquisition Intervals

Figure 38 illustrates a frequent need to acquire more than one signal at a time. A common approach is to use a multiplexed ADC which results the timing shown in Figure 39.



-2

-1

0

1

2

3

4

5

6

7

8

9

10

0 5 10 15 20 25 30

Time

Am

plitu

deSignal 1TimebaseSignal 2

Figure 38 - Multiple Signals

MultiplexADC.cdr 20-JUL-1997

yk

zk yk+1 yk+2

zk+1

tk tk+1 tk+2

zk+2

∆tacq

∆tData

y(t)

z(t)

Figure 39 - Multiplexed ADC

9.3. Simple ADC This and the following sections will examine a number of approaches to implementing a computer interfaced acquisition system that will allow the acquisition of a set of points which represent the amplitude of one or more analog signals as a function of time.

ADC1.cdr 7-Oct-1995

In

ADC

CSRConvert

Busy

d , ..., dn-1 0

eIn

Dat

a

World Computer

Inte

rface

to I/

O B

us

Figure 40 - Simple ADC

This simple system requires a program executing on the computer to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system.

1. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion.

2. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step.

3. Read the CSR and observe the value of the Busy bit.



4. If the Busy bit is 1, go to Step 3. If the Busy bit is 0, the conversion is finished, proceed to the next step.

5. Read the Data Register to get the converted point.

6. Store the point

7. Do the bookkeeping to see if more data points are to be taken, and where the next data point is to be stored.

8. If more points are required, go to Step 1. If done, stop.

Two problems exist with this approach. First, how does the system know when to start the acquisition process, i.e. what is the trigger event and how does the program know when it has occurred? Second, what is the time base for the set of data points, i.e. what are the values of xi associated with each data point, yi, acquired?

Acquision_01.cdr 20-Oct-2004

Busy

Convert

Program Step1

Step2

Step3

Step4

Step3

Step4

Step3

Step4

Step3

Step4

Step1

Step2

Step3

Step4

Step5

Step6

Step7

Step8

Step1

Step2

Step3

Step4

Step1

Step2

Step3

Step4

Step3

Step4

Step3

Step4

Step5

Step6

Step7

Step8

Busy

Convert

Program

ta tb tb tb tb

ta tb tb tb ta tb

ta tb

∆tacq1

∆tacq2

∆t1∆t1

∆t1∆t1

Figure 41 - Simple ADC - Timing Issues

Figure 41 shows two possible scenarios for the acquisition of two points with the system described here. The time base is controlled by the conversion time of the ADC and the time required by the program to execute the indicated steps. The times, ∆t1, represent the delay required for the ADC to respond to the command to convert and raise the Busy flag. The times labeled ta are the times during the execution of Step 1 at which the 1 is actually written out to the



ADC. The times labeled tb are the times during the execution of Step 3 at which the value of the Busy flag is actually latched into the interface. The time between any two data points, ∆tacq, will be the sum of the following times.

Time required to perform Steps 1. (Get the ADC to start the conversion.)

The conversion time of the ADC

Time required to perform Steps 3-4. (Sense the fact that the Busy flag has gone down.)

Time required to perform Steps 5-8. (Deal with the current point and do the attendant bookkeeping.)

First, these times will vary from computer system to computer system since the instruction timings differ from computer model to model. Second, the number of times Steps 3-4 will be executed may differ from data point to data point. Since the ADC is not synchronized with the computer, the Busy flag might go down before or after the time, tb, when the value is actually captured by the nearest Step 3 in time. If the falling edge of the Busy flag comes after the time tb, then the program makes an extra trip through the loop consisting of Step 3 and Step 4. This leads to the difference in acquisition times, ∆tacq, seen in Figure 41.

Another problematic issue is choosing a nominal acquisition interval, the time between data points. As written the time between points is what ever the instruction timing dictates plus the uncertainty due to varying number of execution of Steps 3 and 4. Other choices can be achieved by introducing time killing instructions between Step 7 and Step 8, but this is cumbersome and imprecise.

Finally, at the end of Step 9, the program stops with the results of the acquisition stored in the memory of the computer. Either the memory would then have to be manually examined and the values manually recorded externally, or a program written that would read the acquired data and store it in a file on a disk, or print the values out on a printer or plot the values on a plotter. Fortunately, modern operating systems provide programming that would do much of this work for you. This problem of what to do with the data once acquired will not be addressed in this document.

9.4. Operator Trigger The simplest way to trigger an acquisition sequence is for the operator to wait to start the program until the desired point in time. This will work if the signal being acquired is very slow and the start time need not be very precise. The reaction time of the operator, the time needed for the program to start, plus any initialization steps in the program, (There are none in the above example.) will contribute to the uncertainty of the time of the first data point.

9.5. Software Trigger A second way to control the start of the acquisition is to have the software look for a trigger event on the signal being acquired. As an example, the following simple mechanism looks for a trigger event consisting of the first occurrence after launching the program of the signal making a transition through a threshold in the positive direction. Assume that a storage location called Threshold has been defined in the program and has been preloaded with the value of the threshold.

[Wait until the signal goes below the threshold before arming the trigger mechanism.]



1. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion and raise the Busy flag.





6. Compare the new value with Threshold?

7. If the new value is greater than the value in Threshold, go to Step 1. If the new value is less than the value in Threshold, the trigger mechanism is now armed, proceed to the next step.

[Signal is now below the threshold. Get a new value and look for the next transition through the threshold.]






13. Is the new value greater than or equal to the value stored in Threshold?

14. If no, go to Step 8. If yes, the trigger event has occurred, proceed with the acquisition of the dataset.

This approach assumes, as with the triggering of an analog oscilloscope, that there is a slope and threshold that would define an unambiguous trigger event and that this trigger event would not occur until after the program has started. Figure 42 illustrates the timing of such an approach. The software is continually acquiring data points with an acquisition interval, ∆tacq. The software trigger is armed after the transition through the value stored in Threshold, which is detected with the data point acquired at time t1. The trigger event occurs at time t2. However, the fact that the trigger event has occurred is not detected until the data point is acquired at time t3.



Acquision_02.cdr 20-Oct-2004t1 t2 t3

y

∆tacq

Time

ThresholdData Point

Signal

Figure 42 - Software Trigger Timing

This approach could work for relatively slow signals.

9.6. Simple ADC with Hardware Trigger Another way to address the problem of when to begin the acquisition is to implement a hardware trigger mechanism as indicated in Figure 43. The trigger senses when the input signal, etrigger, crosses the threshold, ethreshold in the direction specified by the Slope, eSlope.


In

ADC

CSRConvert

Busy

d , ..., dn-1 0

eIn

Dat

a

World Computer

Inte

rface

to I/

O B

us

CSR

Inte

rface

to I/

O B

us

In

Trigger

Trigger

Arm

etrigger

ethreshold

eslope

Figure 43 - Simple ADC with Hardware Trigger

Again, a program is required to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system.

1. Write a 1 into the Arm bit in the Trigger CSR.

2. Read the Trigger CSR and observe the value of the Trigger bit.

3. If the Trigger bit is 0, go to Step 2. If the Trigger bit is 1, a trigger event has occurred, proceed to the next step.



4. Write a 1 into the Convert bit of the ADC CSR, which will cause the ADC to begin a conversion and raise the Busy flag.


6. Read the ADC CSR and observe the value of the Busy bit.


8. Read the ADC Data Register to get the converted point.

9. Store the point

10. Do the bookkeeping to see if more data points are to be taken and where the next data point is to be stored.


[As written this program would take one data point per trigger. If the trigger is to signal that a set of points are to be acquired, the branch at this point would be to Step 4 instead.]

This system addresses the problem of when to begin the process, i.e. an external trigger event will start the process. However, there will be some uncertainty in the timing of when the process begins. As with the Busy flag problem of the previous example, the number of instructions in the program that are executed between the time of the trigger event and when the program has sensed that the trigger event has occurred can vary from one run to the next.

This approach does not address the time base challenge described above.

9.7. Programmable Clock

10 MHz Osc.

Mul

tiple

xer (

Switc

h)

Sele

cted

Fre

quen

cy

10 MHz

1 MHz

100 KHz

1 KHz

1 KHz

100 Hz

10 Hz

1 Hz

/10

/10

/10

/10

/10

/10

/10

Freq Reg CSR

I/O Bus Interface

Not Shown: Control signals for strobing information into registers.

Enab

le C

ount

Gate

7

6

5

4

3

2

1

0A0A1A2

CSR

Counter (n-bits)

Enab

le O

veflo

w

Latc

hed

Clo

ck O

ut

Cle

arLa

tche

dC

lock

Out

Clock OutGate

Preload Reg(n-bits)

Counter Reg(n-bits)

ProgClk1.cdr 1-Nov-2004

FlipFlop

SetQ

Clear

Figure 44 - Programmable Clock



The programmable (or real time) clock shown in Figure 44 is a binary counter with preload and an associated time base that is interfaced to the computer. The programmable clock is capable of keeping time independent of the other operations of the computer, thus the name real time. The clock is constructed so that a number is preloaded into the counter and then incremented by each pulse from the basic time base until the counter overflows. The overflow provides an edge that marks the end of a fixed increment of time. The edge causes the logic of the programmable clock system to reload the preload value into the counter and clear the overflow flag. In addition, the Overflow or Clock Out edge is latched in order to hold the value until the software is capable of sensing the end of the time interval. Once the program has sensed the occurrence of the end of the time interval, the software strobes the Clear Latched Clock Out to clear the flag for the next time interval. This process will repeat until stopped by the software and generates a series of pulses at equal intervals of time. Thus, a counter with n stages is operating as a variable modulus counter with a choice of bases between 2 and 2n. To achieve a time interval of m, the preload value is 2n – m.

As an example, if the counter were 16 bits, the base frequency was chosen to be 1 KHz, and the preload value is 216 – 475 = 65536 – 475 = 65061, then the clock would overflow every 475 milliseconds.

The time marks can be sensed by the software or other subsystems of the computer. The Programmable Clock can provide very accurate, very precise, and very stable time bases.

9.8. Program Access to the ADC and a Programmable Clock As in the system shown in Figure 45, the Programmable Clock can be added to the acquisition system to provide more accurate and predictable timing.



ADC2.cdr 1-Nov-2004

Not Shown: Control signals required to strobe signals onto and off of the I/O Bus.

In

ADCConvert

Busy

d , ..., dn-1 0

eIn

Dat

a R

egC

SR

Inte

rface

to I/

O B

us

World Computer

CSR

Inte

rface

to I/

O B

us

In

Trigger

Trigger

Arm

etrigger

ethreshold

eslope

Prog. Clock

Base Freq Select

Preload Reg

Counter

Enable Count

Latched Clock Out

Clear Latched Clock Out

Clock Out

Dat

a R

egD

ata

Reg

Dat

a R

eg

Enable Overflow CSR

Inte

rface

to I/

O B

us

Figure 45 – ADC, Real Time Clock, and Hardware Trigger

The following steps would be required of the program to acquire n points separated by equal increments of time.

[Set up the Programmable Clock and the Trigger.]

1. Write the choice of the basic time base into the Programmable Clock Base Freq Select register.

2. Write the number corresponding to the number of intervals of the basic time base between data points into the Programmable Clock Preload Reg.

3. Write a 1 into the Enable Overflow bit in the Programmable Clock CSR to allow the overflow to be output when it occurs.


[Wait for the Trigger Event to occur. Then start the clock.]

5. Read the Trigger CSR and observe the value of the Trigger bit.

6. If the Trigger bit is 0, go to Step 5. If the Trigger bit is 1, a trigger event has occurred, proceed.

7. Write a 1 into the Enable Counter bit in the Programmable Clock CSR to open the gate and start the counting.



[Wait for a clock tick, i.e. the end of a (beginning of next) time interval.]

8. Read the Programmable Clock CSR and observe the value of the Latched Clock Out bit.

9. If the Latched Clock Out bit is 0, go to Step 8. If the Latched Clock Out bit is 1, a time interval has occurred, proceed to the next step.

10. Write a 1 into the Clear Latched Clock Out bit in the Programmable Clock CSR to clear the latch and, thus, prepare for the end of the current interval.

[Acquire a data point.]

11. Write a 1 into the Convert bit of the ADC CSR, which will cause the ADC to begin a conversion.





16. Store the point

17. Do the bookkeeping to see if more data points are to be taken, and where the next data point is to be stored.

18. If more points are required, go to Step 8. If done, Stop.

[As this program is written, the trigger event signals that a set of n data points are to be acquired.]

This system addresses the two problems above, i.e. the time base and triggering. By choosing the appropriate basic time base and preload value for the Programmable Clock, a wide range of time intervals can be selected. However, there is still a problem with the timing. The clock overflows that mark the end of the time intervals are sensed by the the software “spinning on a bit.” Since the Programmable Clock and the Computer are separate asynchronous machines, the reading of the overflow flag may not occur immediately. If the overflow flag goes up right after the program has read the overflow flag, then the event will not be noticed until a few instruction times later when the program loop comes back around and senses the flag again. This uncertainty decreases the precision of the time base.

9.9. Direct Coupled Clock and Trigger In order to increase the precision of the timing, the Programmable Clock and the trigger can be directly connected to the ADC as indicated in Figure 46.





In

ADC

Convert

Busy

d , ..., dn-1 0

eIn

Dat

a R

egC

SR

Inte

rface

to I/

O B

us

World Computer

CSR

Inte

rface

to I/

O B

us

In

Trigger

Trigger

Arm

etrigger

ethreshold

eslope

Prog. Clock

Base Freq Select

Preload Reg

Counter

Enable Count

Latched Clock Out


Clock Out

Dat

a R

egD

ata

Reg

Dat

a R

eg

Enable Overflow CSR

Inte

rface

to I/

O B

us

Figure 46 - Acquisition System with Direct Coupled Clock and Trigger

The following steps would be required of the program to acquire n points separated by equal increments of time.

[Set up the Programmable Clock and the Trigger.]



3. Write the number of intervals of the basic time base between data points into the Programmable Clock Preload Reg.


[The trigger event will start both the ADC and the Programmable Clock.]

[Acquire a data point.]






8. Store the point

9. Do the bookkeeping to see if more data points are to be taken, and where the next point is to be stored.

10. If more points are required, go to Step 5. If done, Stop.

This system will have more precise triggering and timing, since the vagaries of the program execution are now removed from the timing.

9.10. Sample/Hold Most ADCs require that the voltage being measured be constant over the interval of time during which the conversion takes place. The Sample and Hold (an analog latch) depicted in Error! Reference source not found. and Error! Reference source not found. captures the value of the signal being measured at the beginning of the conversion interval and holds that value until the conversion is done.

SampleHold.cdr 5-Nov-2002

Figure 47 - Sample and Hold

Trig

ger e

vent

occ

urs

S/H

Set

tles

A to

D C

onve

rsio

n Be

gins

A to

D C

onve

rsio

n en

ds

Data Point is stored

Arm

the

trigg

er

Next point can begin

Signal

Output of Sample and Hold

ADC6.cdr 17-Apr-2000

tADCtS to H

tH to S

Figure 48 - Sample and Hold – Time Course




Sample/Hold

(0 = sample, 1 = hold)

Out

Control

In In

ADC

Convert

Busy

d , ..., dn-1 0

eIn

Dat

aC

SR


World Computer

Inte

rface

to I/

O B

us

Figure 49 - Sample and Hold and ADC

The following sequence of operations would be performed by the program controlling the system to acquire a set of data points.

1. Write a 0 into the Sample bit of the CSR, which will cause the Sample/Hold to follow the input signal.

2. If necessary, kill time until the Sample/Hold has settled into the Hold state.

3. Write a 1 into the Control bit of the Sample/Hold CSR, which will cause the Sample/Hold to hold the current value of the input signal.





8. Store the point

9. Do the bookkeeping to see if more data points are to be taken, and where the next data appoint is to be stored.


As described this system has the same two problems of sensing a trigger event and having a known, stable, accurate time base. A real system would address these issues, most likely by combining these elements with others discussed in this section.

9.11. Multiplexed Inputs Typically, more than one signal is to be measured at a time. While individual ADC could be implemented for each signal, the relatively high expense of the ADCs usually precludes such an approach. A more common approach is to include an analog multiplexer in the system as illustrated in Figure 50. This example also includes a Sample and Hold.



Sample/Hold

(0 = sample, 1 = hold)

Out

Control

In In

ADC

CSR

Mul

tiple

xer

Convert

Busy

d , ..., dn-1 0

a0a1a2

e1

e3

e5

e7

e0

e2

e4

e6

Dat

a

World Computer

Inte

rface

to I/

O B

us

Not Shown: Control signals required to strobe signals onto and off of the I/O Bus. Figure 50 - ADC, Sample/Hold, and Multiplexer

The following sequence of operations would be performed by the program controlling the system to acquire a set of data points from two source signals. Assume that the signal x(t) is connected to input e0 and the signal z(t) is connected to input e1. Also, an integer is stored in a location labeled Time Delay prior to execution of the program. A pair of points one from x(t) and one from z(t) are to be taken as close in time as possible. The time between such pairs of points will be the amount of time it takes the program to count down from the integer stored in Time Delay to 0 plus the program overhead of the count down and various bookkeeping. Figure 39 shows an example time course for this acquisition.

[Get the next x(ti).] 1. Write the binary number 0 into the a2, a1, and a0 bits of the Multiplexer CSR, which

will cause e0 to be presented to the input of the Sample/Hold.


3. At the time the conversion is to begin, write a 1 into the Sample bit of the Sample/Hold CSR, which will cause the Sample/Hold to hold the current value of the input signal.








9. Store the point, x(ti).

[Get the next z(ti).] 10. Write the binary number 1 into the a2, a1, and a0 bits of the Multiplexer CSR, which

will cause e1 to be presented to the input of the Sample/Hold.








18. Store the point, z(ti).

19. Do the bookkeeping to see if more data points are to be taken, and where the next data points are to be stored.

20. If no more points are required, stop. Otherwise, proceed with the next step.

[Kill some time before the next pair of points is to be acquired] 21. Get the contents of the location Time Delay.

22. Subtract 1.

23. If the result is 0, go to Step 1. If the result is > 0, go to Step 21.

Again as described, this system has the same problem of sensing a trigger event. In addition having a more deterministic, stable, accurate time base would probably be desirable. A real system would address these issues, most likely by combining the elements of Figure 50 with others discussed in this section.

9.12. Local Buffer, Hardware Trigger Often even more functionality is moved from the program into the acquisition system in order to increase the performance of the acquisition process. Typically, the logic of all of the operation can be simplified and implemented in hardware leading to increased performance. Figure 51 illustrates one such system.




In

ADCConvert

Busy

Trigger

d , ..., dn-1 0

eIn

In

Trigger

etrigger

ethreshold

eslope

Local Buffer for Data

World Computer

Inte

rface

to I/

O B

us

Sample/Hold

Out

Sample

In

Prog. Clock

Base Freq Select

Preload Reg

Counter

Enable Count

Latched Clock Out


Clock Out

Dat

a R

egD

ata

Reg

Dat

a R

eg

Enable Overflow CSR

Inte

rface

to I/

O B

us

Figure 51 - Acquisition System with Local Buffer

The program that will run on the computer to operate this system is below.

[Set up the Programmable Clock and the Controller.]


2. Write the value for up counting into the bit named UP in the Programmable Clock CSR


4. Write the number of intervals of the basic time base between data points into the Programmable Clock Preload Reg.

5. Write the number of data points to be acquired into the Controller.

6. Write the address of the desired multiplexer input into the Controller.

7. Write a 1 into the Start bit of the Controller CSR. This will start the process. Controller will raise the Controller Busy flag.

[Wait for the data set to be acquired.]

8. Read the Controller CSR and observe the value of the Busy bit.

9. If the Busy bit is 1, go to Step 8. If the Busy bit is 0, the acquisition is finished, proceed to the next step.

10. Transfer the dataset from the local buffer to computer memory.



11. Stop.

The Controller must perform the following steps upon receiving the start command.

1. Raise the Controller Busy flag.

2. Write the binary number of the input signal to be acquired into the a2, a1, and a0 bits of the Multiplexer, which will cause the desired signal to be presented to the input of the Sample/Hold.



5. Write a 1 into the Convert bit of the ADC, which will cause the ADC to begin a conversion.

6. Read the value of the ADC Busy bit.


8. Write a 0 into the Sample bit of the CSR, which will cause the Sample/Hold to follow the input signal while other tasks are going on.


10. Store the point in the local buffer.

11. Do the bookkeeping to see if more data points are to be taken, and where the next is to be stored.

12. If more points are required, go to Step 3. If done, lower Controller Busy flag.

9.13. Multiple ADCs The offset, ∆tacq in Figure 38, between the time a point from one signal is acquired and the time a point from a second signal is acquired can be eliminated with the use of multiple ADCs as depicted in Figure 52. Notice that Convert inputs of all of the ADCs are driven by the same clock signal. The computer program sets up the programmable clock before the acquisition begins. Once the acquisition begins, the program monitors the Busy flags. When the conversions are finished, the program reads the output data of the ADC and stores the data for later analysis.




World Computer

to Real Time Clock

In

ADC

CS

R

ConvertBusy

d , ..., dn-1 0

e1

Dat

a

In

ADC

CSRConvert

Busy

d , ..., dn-1 0

e2

Dat

a

In

ADC

CSRConvert

Busy

d , ..., dn-1 0

e0

Dat

a


Inte

rface

to I/

O B

usIn

terfa

ce to

I/O

Bus

Inte

rface

to I/

O B

us

Figure 52 - Multiple ADC

9.14. Circular Buffers

0

1

23

4567

89

1415

1617 18 19

2021

22

2313

12Next Data Pointis stored here

10

11

Figure 53 - Circular Buffer

Acquision_02.cdr 20-Oct-2004

tpretstart tmid tpost

y

Time Figure 54 - Pre, Mid, Post Triggers

A circular buffer can be used in the acquisition of data. Figure 53 illustrates such a circular buffer; in this case there are 24 locations each of which can contain one data point. The pointer



labeled Next Data Point Is Stored Here points to the location where the next item will be stored. In Figure 53 the next item will be stored in location 12. Once an item is stored in the current location, the pointer is incremented to point to the next location in the clockwise direction. The process can continue without end. Of course, values will be overwritten as the pointer completes a revolution. The pointer always points to the oldest item in the buffer. After the first complete revolution has occurred, a circular buffer with n locations will always contain the last n items stored, e.g. 24 in this case.

In the case of data acquisition, the process is started before the window of time during which the features of interest occur. Data points are acquired and the stored in the circular buffer. The acquisition continues until some point in time, e.g. when some trigger event occurs. At that point, the process will be continued for m additional data points where m can be 0 or any number desired. At that time the circular buffer will contain the last n points acquired.

Figure 54 illustrates one such case. The process begins at tstart. Data points are acquired at equal increments in time and stored in the circular buffer. Three possible trigger events are defined, i.e. tpre, tmid, and tpost. In this case the trigger event at tpre could be derived from features on the signal being acquired. The other two trigger events would have to be derived from external sources.

There are three variations possible here. First, the “pre-trigger” is used. The pre-trigger indicates to the controller of the process that 24 more points are to be acquired. The second approach uses the “mid-trigger” which, in this case, indicates that 12 more points are to be acquired. The third approach uses the “post-trigger” which indicates that no more data points are to be acquired. As described here, all three approaches would result in the same 24 points being acquired.

The choice of which type trigger to use will depend on which features are available on the signal of interest if “internal triggering” is to be used or what external signals can be used to generate the appropriate trigger events. Notice that the pre-trigger is the type that has been used in this document for the analog oscilloscope and the acquisitions systems prior to this particular section.

Other variations are possible. For one, if pre-triggering is being used and the controller was set to take 30 more data points after the trigger event occurs, the final 24 data points would correspond to a dataset that begins after a delay of 6 acquisition intervals after the trigger event.

Storage locations are always linear arrays of locations, not circular. Figure 55 illustrates how a linear buffer can be used as a circular buffer. The buffer in this example consists of 24 storage locations that have been allocated for this use and begin at the location labeled Buff. The controlling logic (either in software or hardware) keeps tract of where the next data point is to be stored. When a data point is stored into location Buff+23, the pointer is reset to point to Buff, rather than being incremented to point to Buff+24. An example of a hardware implementation would have a modulo-n counter, the output of which would be used as the address of the next location relative to the beginning of the buffer. The n-th point would cause the counter to roll over. Figure 55 shows the state of the buffer before the acquisition begins and at 4 times during the acquisition.



CircularBuffer0.cdr 26-Oct-2004

Next

Element

Next

Element

Next

Element

Next

Element

a1

a2

a3

a4

a5

a6

a7

a8

a17

a9

a18

a10

a19

a11

a20

a12

a21

a13

a22

a14

a23

a15

a24

a16

a113

a114

a115

a116

a117

a118

a119

a120

a121

a122

a123

a100

a101

a102

a103

a104

a105

a106

a107

a108

a109

a110

a111

a112

a1

a2

a3

a4

a5

a17

a18

a19

a20

a21

a22

a23

a24

a25

a26

a27

a28

a29

a30

a31

a8

a9

a10

a11

a12

a13

a14

a15

a16

BuffBuff + 1Buff + 2Buff + 3Buff + 4Buff + 5Buff + 6Buff + 7Buff + 8Buff + 9Buff + 10Buff + 11Buff + 12Buff + 13Buff + 14Buff + 15Buff + 16Buff + 17Buff + 18Buff + 19Buff + 20Buff + 21Buff + 22Buff + 23

BufferContainsElements

none a - a1 5 a - a1 24 a - a8 31 a - a100 123

t24

AfterAcquisition

timet31t5 t123

Next

Element

Beforethe

start

Figure 55 - Using a Linear Buffer as a Circular Buffer

9.15. Acquisition Systems - Digital Figure 56 illustrates an 8 bit Digital Input system. If the experimental apparatus, i. e. the various domain converters and transducers, produce a series of digital values, the system of this section could be used to acquire the data.

DigitalIn_00.cdr 27-Oct-2004

Control

Latch

01

34567

Dat

a

World Computer

Inte

rface

to I/

O B

us

CSR

Figure 56 - Digital Input

As before a program is required to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system.

Chemistry 838 Time Varying Signals Control of the Experiment, Output


1. Write a 0 into the Control bit of the CSR, which will cause the Latch to follow the input signals.

2. Write a 1 into the Control bit of the CSR, which will cause the Latch to hold the current values of the input signals.

3. Read the Data Register to get the new set of bits.

4. Store the store the set of bits.

5. Do the bookkeeping to see if more data points are to be taken, and where the next data appoint is to be stored.


As with the simple ADC, this approach ignores the issues of when to start acquiring the data and how to control the intervals of time between successive acquisitions of sets of binary bits. Figure 57 illustrates a slight variant where the external system signals that a new point is ready by strobing the Data Ready signal. In such a case, the program would have to monitor the Data Ready bit and get the new point when it has been latched into the interface.

DigitalIn_01.cdr 27-Oct-2004

Control

Latch

01

34567

Dat

a

World ComputerIn

terfa

ce to

I/O

Bus

CSR

Figure 57 - Digital Input II

These issues with triggering and acquisition interval could be addressed by adding triggers, programmable clocks, local buffers, and such to the system in ways analogous to the analog acquisitions cases discussed above.

10. Control of the Experiment, Output 10.1. Analog

DAC_10.cdr 27-Oct-2004

Out

DACd , ..., dn-1 0

eout Dat

a

World Computer

Inte

rface

to I/

O B

us

Figure 58 - Simple DAC

Chemistry 838 Time Varying Signals Control of the Experiment, Output


Figure 58 illustrates an analog output system. In this case, the program writes the next value to be converted and output into the Data Register at the proper moment. The value becomes available as soon as the DAC does the conversion.

More careful control of when the points are output can be achieved by including a programmable clock with the system. Another variant consists of adding a local buffer which can be preloaded with a set of values to be output. This approach removes the computer from the output once the local buffer has been loaded. These techniques would be very similar to those discussed in the analog acquisition section.

Such analog output systems can be used to output very complex functions, i.e. be a function generator.

10.2. Digital

DigitalOut_00.cdr 27-Oct-2004

Control

Latch

01

34567

Dat

a

World Computer

Inte

rface

to I/

O B

us

CSR

Figure 59 - Digital Output

Figure 59 illustrates a digital output system. The Data Ready signal strobes the data into the latch to hold it for the external system. The Data Ready signal also serves as a flag to signal the external system that a new value has been output.

Chemistry 838 Time Varying Signals Computerized Measurement of Time and Frequency


11. Computerized Measurement of Time and Frequency An important interface for modern instrumentation is the computer based facility for measuring frequency, period, frequency ratio, period ratio, elapsed time, and simple counts. Figure 60 and Figure 61 illustrates two approaches for providing this functionality. Figure 60 illustrates having the computer interfaced to an external meter. Figure 61 illustrates the case where the functionality of the meter is built into the interface.

This is really an example of multiple instances of simple digital inputs.

Controller

Not Shown: Control signals for strobing information into registers. Switches and logic for routing , , and to , , and .

Unknown Signal ATime Base Internal Start, Internal Stop Gate Input Start StopUnknown Signal B,

TimeBase

UnknownSignal

A

UnknownSignal

B

Outside World

Computer

Internal Stop

CounterTimer2.cdr 1-Nov-2004

Internal Start

ProgrammableClock

B

A Counter (n-bits)Gate

Gate Control

Start

Gate Input

Stop

I/O Bus Interface

Figure 60 - External Frequency/Period/Time/Count Meter

In both cases, logic will be included within the meter to affect the appropriate connections as described in Table 14 for the selected function. The usual constraints on the signals found in these kinds of measurements apply here as well. For instance, the frequency of the signal connected to the Gate Input must be much greater than the frequency of the signal connected to Start and Stop. The time base can simply be a crystal stabilized oscillator and divider chain or a more elaborate programmable clock.

Chemistry 838 Time Varying Signals Computerized Measurement of Time and Frequency


Table 14 – Frequency/Period/Time/Count Meter - Internal Connections

Signal Connected to Function

Gate Input Start Stop

Frequency Measurement Unknown Signal A Time Base Time Base

Period Measurement Time Base Unknown Signal A Unknown Signal A

Time (External Start/Stop) Time Base Unknown Signal A Unknown Signal B

Time (Internal Start/Stop) Time Base Internal Start Internal Stop

Frequency Ratio Unknown Signal A Unknown Signal B Unknown Signal B

Period Ratio Unknown Signal A Unknown Signal B Unknown Signal B

Count Unknown Signal A Internal Start Internal Stop

Controller

Not Shown: Control signals for strobing information into registers. Switches and logic for routing , , and to , , and .

Unknown Signal ATime Base Internal Start, Internal Stop Gate Input Start StopUnknown Signal B,

TimeBase

UnknownSignal

A

UnknownSignal

B

Outside World

Computer

Internal Stop

CounterTimer1.cdr 1-Nov-2004

Internal Start

ProgrammableClock

B

A Counter (n-bits)Gate

Gate Control

Start

Gate Input

Stop

I/O Bus Interface

Figure 61 - Internal Frequency/Period/Time/Count Meter

Chemistry 838 Time Varying Signals Figures of Merit for Acquisition System Components


12. Figures of Merit for Acquisition System Components 12.1. DAC

• Resolution (number of bits)

• Output range (vmin to vmax)

• Output current limit

• What happens if the output is shorted?

• Time to convert a number

• Linearity

• Cost

• Power Consumption

• Heat dissipation

12.2. ADC • Resolution (number of bits)

• Input range (vmin to vmax) for conversion

• Input range (vmin to vmax) for safety of the ADC device

• Time to convert a number

• Linearity

• Cost

• What happens if the inputs are overloaded?



12.3. Multiplexer • Number of inputs

• Input range (vmin to vmax) assume the same for each input

• Time to switch from one input to another

• Cost




Chemistry 838 Time Varying Signals Figures of Merit for Acquisition System Components


12.4. Sample and Hold • Input range (vmin to vmax)

• Time to go from sample to hold

• Time to go from hold to sample

• Droop rate

• Cost




12.5. Counter • Resolution (number of bits)

• Maximum count rate

• Cost



Chemistry 838 Time Varying Signals Instrument Systems


13. Instrument Systems

Instrument_01.cdr 2-Nov-2004

Control Bus

Address Bus

Data Bus

CPU

Memory

ControlPanel

Registers

Arithmetic Logical Unit

CommandDecoder

I/O Controller#1

Registers

Display/Controls

I/O Controller#2

Registers

AnalogIn

AnalogOut

DigitalOut

DigitalIn

FreqMeter

Acquisition SystemController

Figure 62 - Simple Computerized Acquisition System

Instrument_02.cdr 2-Nov-2004

Control Bus

Address Bus

Data Bus

CPU

Communication Channel

Memory

ControlPanel

Registers

Arithmetic Logical Unit

CommandDecoder

I/O Controller#1

Registers

Display/Controls

I/O Controller#2

CommunicationI/O Controller

Registers

AnalogIn

AnalogOut

DigitalOut

DigitalIn

FreqMeter

Acquisition SystemController

Figure 63 - Intelligent Instrument System

Chemistry 838 Time Varying Signals Instrument Systems


Communication Channel (Bus)

Communication Channel (Daisy Chain)

Communication Channel (Star)

MainComputer

IntelligentInstrument








Figure 64 - Distributed Instrument System

MarsLander.cdr 7-Nov-2000

Lander

Orbiter

Mars

GroundStation

Earth

Rover

Figure 65 - A Very Distributed Instrument System

Chemistry 838 Time Varying Signals Communication (A Brief Introduction)


14. Communication (A Brief Introduction) 14.1. Two Participants The previous section about instrument systems touches on the role communication plays in modern experimentation. As mentioned in the discussion of computer architecture, the typical computer consists of many subsystems and subsections which have to pass information among themselves and external entities. Coupled with these mechanical venues, is the human to human communication. Thus, the topic of communication is and has always been of great importance and interest.

This section takes a very abbreviated look at the physical arena of electronic, electrical communication. Many aspects of the terminology, taxonomy, and technology of the communication parts of modern computing and networking are rooted in the evolution of the telegraphy and telephony industry that has occurred over the last century and a half. The discussion begins with communication between two participants. Figure 66 illustrates the variations of one-to-one communication.

Half Duplex - Alternating Talking

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Figure 66 - One to One Communication


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Figure 67 addresses the specific issue of connecting two electronic devices together for communication, an issue that the modern researcher often encounters when deploying and maintaining distributed computing and instrumentation. Basically, the transmitter of one node must be connected to the receiver of the second node and visa-a-versa. As illustrated in Figure 67, there are typically two types of devices of a given categories, e.g. computers, switches, hubs. All of a given type typically has the same assignment of transmit and receive signals to the physical pins on the connector to which the communication cable is to be attached. For example, transmit is pin 1 for the type 1 devices in Figure 67. Thus, to connect two devices of the same type, e. g. two computers or two switches, one must use a crossover cable (called a null modem in the case of serial connections or uplink in the case of switches and hubs). However, to connect two devices of different types together, one must use a straight through cable. Many modern switches are capable of detecting which kind of connection is needed and automatically reconfiguring the port in question.



14.2. Many Participants Usually there are many more than two participants connected to a communication facility. One mode of operation in such cases is for there to be one talker and any number of listeners as depicted in Figure 68. One node can talk to a subset of the population as shown in Figure 69. Or, the information can be sent to all participants as in Figure 70.

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Figure 68 – One-to-Many Communication


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Notice that the discussion so far seems to assume that there is a communication channel between the talker and each of the listeners. As the number of participants grows, this becomes more difficult to achieve. Figure 71 illustrates a few variations of communication systems connecting 6 participants. Except for the case of the communication bus, shared link, or party line depicted in Figure 71g, all communication systems are a combination of one-to-one communication channels connecting two participants. Figure 71a illustrates the case where there is a dedicated link between each pair of participants.

Except in the case of the bus, the communication between two nodes may involve more than the two communicating participants. In such cases, the information must pass through intermediate nodes to get to the destination. As an example, assume the topology of Figure 71b. If node F wishes to communicate with node E, all information must first pass to node A, which then must forward the information to the destination. More hops are involved in other cases.

In these cases of less than full connectivity, the interior nodes may be dedicated to forwarding information and not be full fledged nodes as those on the fringes of the topology. These interior forwarding nodes may be hubs, switches, routers, or gateways.



The topology of Figure 71g does not need the forwarding nodes, but the communication channel is shared and one conversation has to wait until the current one is finished.


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From a communication point of view, the topology of Figure 71a is the most desirable in that there is a dedicated communication link to all other parties. Thus, communication between any two nodes can take place with no interference from any other conversations. In all other cases, there are conflicts that may impede any given conversation between two nodes. However, there are two facts that keep any real network from striving toward the goal of full connectivity. First, a human being and most machines are limited in the number of conversations in which they can participate simultaneously. Second, the number of links required to fully connect a group of nodes grows very rapidly with the number of nodes. Equation 1 shows the relationship between the number of links, k, and the number of nodes, n, to be connected in a fully connected topology.

!2)!2(

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Table 15 tabulates some values from this equation.



Table 15 - Number of Links in a Fully Connected Net

Number of Nodes

Number of Links

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Number of Links

2 1 10 45

3 3 20 190

4 6 28 378

5 10 50 1225

6 15 100 4950

7 21 200 19900

8 28 500 124750

9 36 10000 49995000

10 45 100000 5E+09

As an example, consider the city of Lansing, MI which has about 400000 inhabitants with, say as a guess, 100000 households. A completely connected telephone network for this community would require 5x109 phone lines between each home and every other house. But even worse, each home would have to have 5x109 telephone instruments. Absurd!

Figure 72 illustrates a more complicated topology than those of Figure 71 and involves 28 full nodes, 6 forwarding only nodes (i.e. hubs, Hi) and 33 links. This set of nodes would require 378 links to completely connect the 28 full nodes, already an unwieldy number. Real systems can be much more complicated even if they are not fully connected. For example, consider the global phone network or the global Internet each with millions of nodes. At the other extreme are small local area networks involving only a small number of nodes. Any network will be a compromise between the number of links and the desire for connectivity, and will be extensions of the concepts included in Figure 71, Figure 72, and Figure 73.

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Figure 73 - Mixed Topologies

Chemistry 838 Time Varying Signals Time Varying Signal Details


15. Time Varying Signal Details 15.1. Varying Duty Cycle

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15.2. Signal Details

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Figure 79 - Limit X and Y Range

15.3. Signal Details - Another part of the Signal

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15.6. Acquisition Strategies – Scenario 3


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15.7. Acquisition Strategies – Boxcar

Acquisition Window 1 Acquisition Window 2

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Chemistry 838 Time Varying Signals REVISION HISTORY


16. REVISION HISTORY Revision History for Time Varying Signals

Version Date Authors Description 1997 21-Jul-1997 T V Atkinson This document is the transcription of my lecture

notes as distilled over 3 decades of CEM 838. This is the first edition of the material in this form. Contained the Oscilloscope material.

2000 8-Nov-2000 T V Atkinson Added data acquisition systems

2001 31-Oct-2001 T V Atkinson Added instrument systems section and more acquisition systems.

2002 4-Nov-2002 T V Atkinson Expanded DAC and ADC section.

2003 9-Oct-2003 T V Atkinson Added Data Analysis. Expanded switch section.

2004 12-Oct-2004 T V Atkinson Added ideal/real switch section.

2004.1 4-Nov-2004 T V Atkinson Reformatted and added commentary to the computer interfacing hardware section. Major reorganization and changes to the Acquisition and Instrument Systems Sections. Moved the data analysis section to a separate document.

2004.2 9-Nov-2004 T V Atkinson Added the communication section.

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Time Varying Signals Chemistry 838