Time-multiplexing of signal using highly integrated

Time-multiplexing of signal using highly integrated digital delay:

an FPGA implementation

V. Bocci, G. Chiodi, F. Iacoangeli, R. Nobrega, D.Pinci,W. Rinaldi. INFN Sezione di Roma

Abstract–We have designed and implemented on a Xilinx

SpartanIIE FPGA a highly integrated time-multiplexing device by means of using multiple fixed delays. Signals coming from MWPCs (Multi Wire Proportional Chambers) Front End readout circuitry can be multiplexed in time using selected delay values. Up to 5 channels can be merged into one using delays in increments of 150ns. As a consequence, usage of one multi-hit channel to measure timing of 5 channels is possible. Inside the FPGA a 36 to 8 multiplexing is performed, resulting in a reduction, of more than a factor of four, of the number of multi-hit TDC channels needed.

I. INTRODUCTION In high energy physics experiments, numerous detector

channels can provide signals in a narrow time window of tens of nanoseconds. It is often necessary to measure the absolute timing of each channel with a good resolution. With time-multiplexing it is possible to put several inputs into one channel of a multi-hit TDC to make measurements of their individual absolute time, all in one go.[1]

Figure 1: Time-multiplexing to TDC

The basis of time-multiplexing is to apply different delay values to individual channels and to finally recombine the signals in one channel of a multi-hit TDC. In our application the amount of each delay step necessary is of the order of 150 ns: to combine 5 channels the first of them is sent out without delay while the others are delayed by T ,2T, 3T, 4T where T in our implementation can vary in the 140-160 ns range.

Figure 2: The basis of time-multiplexing A brute force approach, using cables as delay elements is

simply not feasible: to achieve a 600 ns delay time, a 120 m long cable, even disregarding attenuation effects, is clearly not an option. This dictates that an active delay line is needed.

There are on the market several active digital delay circuits, but the integration of such devices is not suitable to this purpose. Even the most miniaturized commercially available digital delay chips contain a maximum of 3 lines, only with TTL signaling; even if offered packages can be very small, they can not reach the density of a single chip solution. On the other hand, commercial products can guarantee high precision in delay amounts but what matters most in our application is stability over time of the delay obtained, rather than its absolute value which can be in any case measured a posteriori.

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II. TIME-MULTIPLEXING Large scale integration of active delay units is feasible using

either ASICs or FPGAs; the flexibility of multi standard IO pins available on FPGAs as well as their reprogrammability, opposed to the development one-off costs and lead time of an ASIC make FPGA the best option.

In order to optimize production costs and integration level we have chosen to implement time-multiplexing on a FPGA Xilinx SpartanIIE XCV300 [2]. This device, with a streamlined architecture based on the proven VirtexII-E platform, delivers 6,912 logic cells, 1536 complex logic blocks and 329 I/Os of which a maximum of 240 can be used as differential pairs.

Moreover it is possible to choose among 19 available I/O standards: this also helps increase system integration.

Time-multiplexing is implemented in delay steps of about 150ns.

One multiplexer FPGA can recombine 36 LVDS input channels, each delayed by 150 ns, 300 ns, 450 ns or 600ns, into 8 TTL outputs. Some groups of channels are made up of five input lines, some of four: groups of four have a multiplexing window of 450 ns as maximum delay and groups of five by 600 ns. This modularity helps maximize FPGA occupancy while increasing delay steps.

A modular approach has been the obvious choice in order to maximize device usage while keeping a fixed multiplexing ratio, necessary for board implementation and to adhere to specifications.[1]

As well as delaying signals by fixed amounts, multiplexers possess some testing and control functionalities

An i2c slave interface has been implemented on the device: by means of such a block, internal registers within the FPGA allow enabling or disabling channels input to the Multiplexer. Setting in the appropriate fashion i2c registers it is possible to mask out each input, enabling only desired channels. Besides, generation of test sequences, for example to check cable connections, is also possible using trains of selectable duration made up of a desired number of pulses sent to the chosen range of input channels.

A. IMPLEMENTATION Xilinx ISE 4.2 has been used as EDA tool in order to design

validate and implement the Time Multiplexer. It comes as a complete FPGA solution with design entry, validation, synthesis, physical implementation and device configuration tools.

In order to produce delay lines of variable length in the FPGA device, the main guideline has been to use the FPGA internal Configurable Logic Blocks (CLBs) as I/O buffer stages, so that input signals accumulate delay in propagating across each logic cell. Replicating numerous short delay paths through many CLBs, a delay line is obtained.

Figure 3: Scheme of CLBs connections

A 36 by 8 multiplexer is not just one block, but as a result of

concurrent usage of several basic modules. Using a floorplanning tool, a basic delay macrocell has been

designed by hand and optimized for maximum delay and minimum area. Such delay lines have been achieved following a unusual approach, using the signal paths with the worst delay, which can be very awkward for an EDA tool, which usually tries to achieve the shortest propagation delay time.

By-Hand place and route has also allowed using the same CLB twice: in this way sometimes the same delay can be obtained using half as many configurable logic blocks.

Eight basic delay macrocells are grouped in a square block with a simulated delay of about 20 ns. The 20 ns component is instantiated in a structural verilog file, resulting in a macro block.

Figure 4: Delay block made up of 8 macrocells used as

basic delay element The only outcome of the process is the creation of a basic

delay block which amounts to the time window between one channel to multiplex and the following.

In order to obtain a 36-to-8 channel multiplexing, on a

SpartanIIE XCV300 four 4 to 1 and four 5 to 1 multiplexing blocks are featured.

To enhance usability of the device an I2C slave block has been implemented on the same FPGA, allow access to a serial interface which makes possible a selection or masking out of

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every single channel. Using the choice of different IO standards offered by the Xilinx device, versions with different I/O buffers of the same design can be programmed, in our case we use LVDS or LVTTL IO pins.

B. PLACEMENT AND ROUTING Routing the FPGA is a difficult task, in spite of the

simplicity of the design, because of the substantial number of cells and connections entailed; extra care had to be taken in order to keep memory used by the routing process below the 2 GB limit set by the OS.

In order to do so, larger blocks previously laid out by hand had to be used as building blocks of the design, thus decreasing the chance of errors generated by the Xilinx fitter. In other words a double result was achieved: decreasing the memory in use by the OS and the chance of errors caused by automatic placement.

Figure 5: Routed FPGA

III. SIMULATION The time multiplexer design has been entirely simulated and

validated using “Modelsim SE/EE Plus 5.4e" at gate level, employing a flattened verilog file synthesized by the Xilinx synthesis tool within ISE.

We have chosen best case in device delay, in order to obtain the worst case for the utilization foreseen. The Figure 6 shows the functional blocks of the time multiplexer simulated and its test bench.

An explanation of functionalities of the blocks: Strobe: generates a periodic pulse, 5ns long, every 600ns.

The resulting signal is the reference input signals are built on. Random Pulse: using as a reference the strobe coming from

the module with the same name, this block creates five periodic signals with the same shape as their inputs. Each output is

delayed by a different random duration of time, obtained from a Gaussian distribution.

Figure 7: Simulation Testbench. Multiplexer36x8: this block contains the basic 36-to-8

multiplexer obtained with Xilinx ISE. The five outputs from random pulse are then fed into the multiplexer inputs so that each multiplexing sub-block (the 5-to-1 and 4-to-1), implemented in the FPGA receives a different test signal.

I2C Master: It simulates the functionalities of a control system executing every test routine. Its main duty is to enable or mask out input channels using its i2cmaster block. It generates a flag, called Mask_on, which signals to the test bench the completion of access to registers, disabling the clock generator and enabling a strobe generator. This facilitates simulation and speeds up testing the logic.

40Mhz Clock: this is a 40MHz clock signal input to the FPGA, used mainly in the i2c block.

Histogram Generator: in the histogram generator delay values of test pulses are accumulated. Actually, one module per input signal has been used, and this block can be thought as the collection of all basic histogram generators, one per each multiplexer output and one for the five outputs of random pulse, taken as a reference. Each module is provided with a vector of 500 integers which corresponds to the 500ns following generation of a strobe pulse, taken as the start signal. When a pulse reaches the input, a delay from the reference is calculated, and the corresponding register is incremented. At the same time another function is reading sequentially the contents of the histogram vector registers, 1 ns later, and it puts

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the values obtained on the 32 output bits, generating a plot of the histogram.

Generated histograms of output signals show a Gaussian

distribution of their input delays, each centered around the expected delay time of each input line.

Using the framework, it has been evaluated how the delay interval of output channels varies in time.

VI. MEASUREMENTS The Key feature of a time-multiplexer is jitter, which affects

accuracy and stability of delay. Jitter should be kept to a minumum in order to avoid variations in the delay time.

Jitter measurements have been performed on output channels, using generated periodic pulse signals with duration of 50 ns and period equal to 200 µs. the resulting samples are shown below in histograms.

The measured response of tested devices is in good agreement with simulations, delays are consistent and channels show an RMS jitter lower than 500 ps, hence it is safe to conclude that after careful evaluation the device showed a very low contribution to timing misalignments.

Figure 8: 16 hours measurement at room temperature.

Measurements of delay stability over SpartanIIE's

temperature and supply voltage operating conditions (Figures 8, 9,10) show with a changing delay a modest jitter. However the device will operate in a much less unfavourable temperature and voltage working range (as shown in Figure 9), as it will be installed in a laboratory apparatus with regulated power supplies.

Figure 10: Supply voltage 1.72v (-4.5%), at room

temperature.

Figure 11: Supply voltage 1.88v (+4.2%), at room

temperature.

Figure 12: measurement at T = 47.2 °C. V. MULTIPLEXING-BOARD AND TEST STATION

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Four SpartanIIE Xilinx FPGA are hosted on a 6U VME

module, the Multiplexer Board [3], shown in the figure below. It is a standard VME 6u module constructed with a 6-layer PCB.

Each board is capable of time-multiplexing 144 LVDS signal inputs into 32 ECL outputs by means of a daughter board which carries out a translation between TTL and MECL electrical levels.

Figure 13: VME Multiplexer board

The multiplexer-board is used in a cosmic rays test station

for MWPCs (Multi Wire Proportional Chambers), the chambers which will be used in most of the LHCb Muon subdetector. It is an apparatus able to receive signals from 6 MWPCs, each generating a maximum of 96 output channels.

Using four multiplexer-boards, as many as 576 channels output from the chambers under test can be read out employing a single CAEN V767 128-channel multi-hit TDC module. Then, via a National Instruments VME/PCI MXI2 adapter, signals are sent to a desktop PC running the data acquisition program[4].

Figure 14: Scheme of read-out system of test station.

ACKNOWLEDGMENT

We are grateful to Labe Staff: Silvano Di Marco, Antonio Rossi and Daniele Ruggieri for their precious work and technical assistance during the test and assembling stages in the laboratories.

REFERENCES [1] F.Iacoangeli, V.Bocci (Advisor),G.Martellotti (Advisor) ” Studio

del sistema di test e controllo delle camere per i muoni dell’esperimento LHCb”,M.S.C. thesis , Rome – university “La Sapienza” (2003)

[2] Xilinx,“SpartanIIE 1.8V FPGA Family Complete Data Sheet”, http://direct.xilinx.com/bvdocs/publications/ds077.pdf

[3] V.Bocci et al. “Multiplexed Channel Readout in a Cosmic Rays Test Station”, Proceeding of 11th Workshop on Electronics for LHC and future Experiments , LECC 2005, Heidelberg, Germany

[4] V. Bocci, et al “Performance Evaluation of the Control System for the LHCb Muon Detector”, Proceeding of 11th Workshop on Electronics for LHC and future Experiments , LECC 2005, Heidelberg, Germany

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Time-multiplexing of signal using highly integrated