This file contains a block diagram and some functional notes on the L2Beta 9U card design.

Results of discussions among Philippe Cros, Drew Baden, and Bob Hirosky are merged into the design.

Base design uses an Altera 20K200 FPGA and PLX 9054 PCI interfaceThe choice of the Altera will expedite our firmware development cycle.The choice of the PLX chip will give our design greater flexibility, because the PLX supports both 3.3V and 5V PCI buses. Use of a commercial PCI interface will also reduce our firmware complexity.

Details of the mechanical design are show in talks by Philippe Cros.

PLX ADDON

P1

P2

ALTERA 20K200360 (of 272)

pins used

TTL2

PECL

VME Block

Config/S

py B

lock

MB

Arb

. Blo

ck

LB

us B

lock

FIF

O B

lock

Scaler

Block

FIFO

(18bits x4k)x8

MB

AD

/DA

Blo

ck

AD dirDA enables

Overview of FPGA Blocks

MBAD

MBDA

MBDA

MB_PECL

MB TTL

62

15

32

36

TS

I M

Bus

B

lock

23

14

163

15

These blocks have tightly coupled functions

P3

Add-onbus

DQ[31:0]

62 signals

BP_CLKIRQ*SYSRST*ADR[6:2]BE[3:0]*SELECT*WR*RD*PT_NUM[1:0]PTBE[3:0]*PTATN*PTBURST*PTADR*PTWRPTRDY*WRFULLWRFIFO*RDEMPTYRDFIFO*

Add-on bus block

Fixed by AMCC SPECS

VME block

P1 GAP*

GA[4:0]*6 signals

P2SCL_INT/Worker_intL2 Answer Ready

9 signals

VBD_DONEVBD_Start_Request/VBD_STARTJ2_Test_Out(0)/Worker1_IntJ2_Test_Out(1)/Worker2_IntWorker3_IntWorker4_IntWorker5_Int

ClockReset

36 signals

EPROM[5]JTAG[5]?Logic Analyzer[16]Switches[4]LED DISPLAY[4]?

Config./SPY block

JTAG/EPROM/DIAGNOSTIC I/O, etc

MOD_DONE[15]EV_LOADED[3]START_LOADDONE_OUTMB_RESETAP_FIFO_EMPTY

55 signals ECL SALERS[32]

TSI MBus+scalar block

“MISC” out: EV_LOADED[3:0], START_LOAD, DONE_OUT, MB_RESET, AP_FIFO_EMPTY

VME block (signals on P1&P2)

P1GA[5:0]*6 signals

P2SCL_INT/Worker_intL2 Answer Ready

9 signals

VBD_DONEVBD_Start_Request/VBD_STARTJ2_Test_Out(0)/Worker1_IntJ2_Test_Out(1)/Worker2_IntWorker3_IntWorker4_IntWorker5_Int

MbusArbitration

MB_WR*

14 signals

DDONE*

Open collector MBUS arbitration lines require output buffers and separate input pins

DSTROBE*

BOSSREQ*

BOSSBROUT*

BOSSGRIN*

BOSS* TTL2

PECL

P3

MBUS AD/DA + FIFO block

OE PIO_OUT

OE PIO_IN

AD_DIR

AD[32]

WCLK, WEN

RCLK,REN,OE

EF,FF

FIFO (18bits x4k)x8

DA[128]

FPGA188 Pinsused

P3

MB DMA AD[10]

BROADCAST DATA IN

FIFO WEN set (PIO OEs deasserted) by address decodeFIFO WCLK = WEN + DSTROBE(New address sets FIFO_IN bits to flag BOE)

PIO DATA IN (TARGET MODE)

OE_PIO_IN set (OE_PIO_OUT, FIFO_OE deasserted AD_DIR=0) by address decodeData/Address latched in FPGA at DSTROBE, DDONE pulsed

PIO DATA OUT (TARGET MODE)

OE_PIO_OUT set (OE_PIO_IN, FIFO_OE deasserted, AD_DIR=0) by address decodeAddress latched in FPGA on DSTROBE/RWDATA fetched, placed on MBUS, DDONE pulsed

PIO DATA OUT (MASTER MODE)

Boss RequestedOE_PIO_OUT set (OE_PIO_IN, FIFO_OE deasserted, AD_DIR=1)AD/DATA placed on MBUS, WR set, DSTROBE pulsedDDONE received, OE_PIO_OUT deasserted, AD_DIR=0

PIO DATA IN (MASTER MODE)

Boss RequestedOE_PIO_IN set (OE_PIO_OUT, FIFO_OE deasserted, AD_DIR=1)ADDR placed on MBUS, WR set, DSTROBE setDDONE received, Data Latched in FPGA, OE_PIO_IN&DSTROBE deasserted,AD_DIR=0

DEFAULT settings:AD_DIR = 0 (input mode)

PIO_OE_IN=PIO_OE_OUT=FIFO_OE=0

Arbitration of shared inputs from Mbus to FPGA

Comments:

•Explicit CDF compatibility is not implemented in this draft•The FIFO outputs share the same FPGA I/O pins as PIO, FIFO readout is simplified, because it’s done in 128 bit words•Spare bits in the FIFO’s are used to tag beginning and possibly end of a data source, this can simplify DMA firmware •Utility features include LA hookups to FPGA, LEDS, and switches

16 free I/O pins are still available in this configuration, additional pins could easily be made available by:Adding external logic to MBUS Arbitration (~5)Reducing FIFO special bits (~2)Reducing LA/LED/Switch bits (~10)POSSIBLE FREE PINS w/ minimal impact on design ~ 33

Uses for additional I/O pins (and pins needed for each function):Provide compatibility w/ a custom designed 64-bit interface (~12-16 pins)

Provide compatibility w/ a 64-bit PCI local bus (~40 pins) (Possible at expense of LA pins at time of upgrade – Firmware redefinition)

Provide compatibility w/ CDFJ2 signals (~37 pins)Address FIFO (~10 pins plus support logic)(Maybe possible at expense of LA pins, LEDS, switches AND 64 bit upgrade option)

More LA hookups, bells, whistles, etc…

Additional Comments:

More pins may be freed up by using 32 bits to ECL drives as LA bits. A front panel redefine these line to be LA lines, instead of scalar lines for diagnostic testing. This would leave us with more than 40 free I/O pins in the design proposed here.