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THIN FILM DEPOSITION – Chapter 9Introduction
P
P WellN Well
PNP+ P+ N+ N+
• Many films, made of many different materials are deposited during a standard CMOS process.• Requirements or desirable traits for deposition:1. Desired composition, low contaminates, good electrical and mechanical properties.2. Uniform thickness across wafer, and wafer-to-wafer.3. Good step coverage (“conformal coverage”).4. Good filling of spaces.5. Planarized films .
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
€
Aspect ratio=AR =hw
• Note the aspect ratios and the need for new materials.• Note also the number of metal layers requiring more deposition steps.
Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018
Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm
MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm
Min Metal 1 Pitch (nm) 214 152 108 76 54 42
Wiring Levels - Logic 10 11 12 12 14 14
Metal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0
Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20
STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4
Metal Resistivity (µohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
Interlevel Dielectric Constant 3.9 3.7 3.7 <2.7 <2.4 <2.1 <1.9 <1.7 <1.7
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Metal line
a
Contact hole
b
wh
wh
Thin Film Deposition
• Quality – composition, defect density, mechanical and electrical properties
• Uniformity – affect performance (mechanical , electrical)
Thinning leads to R
Voids: Trap chemicals lead to cracks (dielectric) large contact resistance and sheet resistance (metallization)
AR (aspect ratio) = h/w with feature size in ICs.
Examples
Poor step coverage with increasing AR
Thinning causes metal resistance to increase, generates heat and lead to failure
Chemical Vapor Deposition
Flat on the susceptor
Cold wall reactor
Methods of Deposition:
Chemical Vapor Deposition (CVD):APCD, LPCVD, HDPCVD Physical Vapor Deposition (PVD: evaporation, sputtering)
Atmospheric Pressure : APCVD
Cold wall reactors (walls not heated - only the susceptor)
Low pressure: LPCVD – batch processing.
Hot wall reactor
Atmospheric Pressure Chemical Vapor Deposition
Transport by forced convection
By diffusion through boundary layer
Diffusion through the B. L
Desorption of by products
Transport of byproducts by forced convection @ the surface (4):
decomposition, reaction, surface migration attachment etc.(3) May be desorption which depends on a sticking coefficient (4)
Growth rate for Si deposition N=5•1022cm-3
Mole fraction of the incorporating species in the gas phase.
Partial pressure
Total concentration in the gas phase
CT = 1 * 1019 cm-35 * 1022
V = 0.14 m/min
PG @ 1 torr
Ptotal = 1 atm = 760 torr
adsorption
transport
reaction
Steady state
Steps in deposition
As in Deal-Grove model for oxidation
Growth Kinetics
Determined by the Smaller of ks or hGTwo limiting cases
1) Surface reaction ks << hG
Control: fast transport
slow reaction
YkN
Cv S
T=
2) Mass transfer or gas phase diffusion hG << ks
YhN
Cv G
T=
Fast reaction and slow transport.
Temperature uniformity more important than the gas flow wafers vertically poly-Si
Put wafers flat to ensure flow uniformity @ the Si surface.
EpitaxyAPCVD
SiO2
(111) Si shows slower v – fewer attachment sites than in (100) Si
Ea 1.6 eV for all Si sources H desorption from the Si surface.
With H2 as a gas carrier
Light mass
heavy
Limited by transport
Both are linear with time (t)
SiH4 the fastest growth
kS limited deposition is VERY temp sensitive.hG limited deposition is VERY geometry (boundary layer) sensitive
Boundary Layer – Diffusion to the Surface
Gas moves with the constant velocity U.
Boundary layer (caused by friction ) increases along the susceptor, mass transfer coefficient hG decreases, gas depletion caused by consumption of the reacting species (concentrations decrease)Growth rate decreases along the chamber
• Use tilted susceptor
• Use T gradient 5-25°C
• Gas injectors along the tube
• Use moving belt
Deposition of alloys DIFFICULT – various reactions, kinetics (species, precursors)
Use PVD rather than CVD
B.L.
viscosity
gas density
Doping in CVD for EPITAXY
Intentional and Unintentional
Si source + Dopant (AsH3, PH3, or B2H6)
Autodoping: 1 - 4
outdiffusion
autodopingThe growth is
faster than the diffusion
Dtvt >>
The dopant sources at the surface go through:
• dissociation of hydride gas
• lattice site incorporation
• burying of dopants by other atoms in the film
Simulation very inaccurate : chamber design etc.
In deposition , the doping,
€
C ∝ Pi for low growth rates
C ∝Pi
v for high growth rates
800-1000°C
outdiffusion
autodoping
T&time of CVD
Calculate all distributions (=contributions) to get C(x,t)
Low Pressure Chemical Vapor Deposition
Operate at the surface reaction limited regime lower deposition temperatures
Larger diffusion @ lower P s
GG
Dh
δ=
YN
c
hk
hkv T
Gs
Gs
+=
hG increases ~ 100 X for 760 torr 1 torr
Surface reaction controls the growth
LPCVD reactors use
• Vertical wafer stacking
• P = 0.25 – 2.0 torr
• T = 300 – 900 °C ( + 1 °C) temperature gradient increase 5 – 25% to compensate reactants depletion distributed feeding.
• Less autodoping (at lower P)
• Fewer particulates.
Possible disadvantages:
• Deposition rates may be too low, Film quality decreases
• Shadowing (less gas-phase collisions) due to directional diffusion to the surface deterioration of the step coverage and filling.
transport less important
low pressure
DG1/Ptotal
Plasma Enhanced Chemical Vapor Deposition(PECVD) Used when :
• Low T required (dielectrics on Al, metals) but CVD at decreased T gives increased porosity, poor step coverage.
• Good quality films – energy supplied by plasma increases film density, composition, step coverage for metal decreases but WATCH for damage and by product incorporation.Outgassing , peeling ,
cracking stress.
P 50 mtorr - 5 torr
Plasma: ionized excited molecules, neutrals, fragments, ex. free radicals very reactive reactions @ the Si surface enhanced increase deposition rates
• High Density Plasma CVD dense layers ( SiO2) at low T (150 °C) and low P ( 1- 10 m torr); T increases to 400°C by bombardment
• Separate RF (gives substrate biasing bombardment) from plasma generation (Electron Cynclotron resonance ECR and Inductively coupled Plasma ICP)
• Controlled bombardment (angular -> sputtering) preferential sputtering of sloped surface improved planarization and filling
200- 350 °C
13.56 MHz
Ions, electrons, neutrals = bombardment
High Density Plasma (HDP) CVD
gas inlet
plasma
magnetic coil
RFbias supply
(13.56 MHz)
wafer
gas outlet,pump
Microwavesupply
(2.45 GHz)
• Remote high density plasma with independent RF substrate bias.• Allows simultaneous deposition and sputtering for better planarization and void-free films (later). • Mostly used for SiO2 deposition in backend processes.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Physical Vapor Deposition (PVD) – no chemical reactions (except for reactive sputtering)
Evaporation
Advantages:
• Little damage
• Pure layers (high vacuum)
Disadvantages:
• Not for low vapor pressure metals
•No in-situ cleaning
• Poor step coverage
Very low pressure (P < 10 –5 torr) - long mean free path.
• purer – no filaments, only surface of the source melted
• X-rays generated trapped charges in the gate oxides anneal it !
Evaporation
k2cos
rN
vopRev θ
Ω= ki2
coscosrN
vopRev θθ
π=
Ideal cosine emission
Wafer holders to increase uniformity of deposition
Projected area
Knudsen –cell like behavior
The largest flux for the perpendicular direction
Affected by a crucible (melt,) l
r and cos θk v
Practical cases
Use spherical holders & rotate them in a planetary configuration
Deposition rates:
nonuniform deposition
lower because of cosθi emission
source here is || to the wafer
Emitted fluxes from crucibles
Evaporation
Partial Pressure (Pe) of the source (target)
e
2
1
s2
evap PT
mA1083.5R ⎟
⎠
⎞⎜⎝
⎛×= −
Needed for reasonable v 0.1 - 1m/min
No alloys – partial pressure differences
Use separate sources and e-beam
incident
reactedc F
FS =
Step Coverage Poor :
• Long mean free path (arrival angle not wide = small scattering) and low T (low energy of ad-atoms)
• Sticking coefficient high (@ T) no desorption and readsorption poor step coverage
• Heating can increase Sc but may change film properties (composition, structure)Rarely used in IC fabrication
Sticking coefficient
1-10 mtorr
Deposition
Sputter Deposition
Higher pressures 1 –100 mtorr ( < 10-5 torr in evaporation) -> contaminations!
Use ultra clean gasses and ultra clean targets
Alloys (TiW, TiN etc)
• good step coverage
• controlled properties
DC Sputtering (for metal)
Conductive
Al, W, Ti
Ar inert gas at low pressure.
No free radicals formed by Ar (ex. O, H ,F as was for PECVD)
Major Technique in Microelectronics for:
DC Sputtering
Low concentrations of electrons -> few collisions -> large voltage here0.1 –10
mm
Ar ions (+) strike the target and sputter ions electrons do not have high energy yet dark glow anode sheath.
e-
I+
e- collide with Ar atoms excitation=glow
(Crookes dark space)
positive potential (form next to each surface = anode)
I+ and e- strike the surface:µe larger (smaller mass than for ions) more electrons than ionsE field due to charge imbalance Vp (10 V develops) to decrease e- accumulation
+ potential
secondary electrons!They sustain the plasma
ions
The source of material to be deposited
Conductive !
low e--conc.
Very small sputtering at the anode can be used for bias sputtering and ionized sputtering
Ions get neutralized by e- and diffuse to the wafer surface
Sputtering
10-20 eV
secondary electrons
electrons sustain the plasma - ionization of the gas Bombardment by
I+ , e- charges and neutrals
adsorption
migration
desorption (small)
Cathode
DC Sputtering
heating
can be used in hot sputterreflow
Reactive SputterDeposition = add gas:. N2 Ti N. O2 Ti O2
Can be incorporated in the film
CONDUCTOR
WAFERS
SPUTTERING YIELD
Effect of mass (gas) & Energy TiW
steady state sputtering
Effect of mass (target)
implantation
Target
Target atom
gas
much smaller differences in sputtering yields then in partial pressures of components (target) in evaporation
+
Neutral
RF Sputter DepositionDielect
ric
Instead of DC: 13.6 MHz RF coupled capacitively to plasma
several 100V
wafers
DC sputter cannot be used for dielectrics
secondary e-
plasma extinguished (VZ ) in 1-10µs
More on the walls charge built-up
potential VP
potential
@ the target ( area)
-
= NON-CONDUCTINGOscillating (with RF) e- ionization yield
pressure
+ magnet e- trajectory Magnetron Sputter Deposition have better ionization yields
deposition rates (10-100X)better film quality (Ar needed)use in DC & RF ( heating of the target since I+ )
large A1 area
A2
A2A1
e- charge on electrode (e- are fast so they keep up with RF)
e- d
tenths of volts
faster, smaller
can be used
V1/V2=(A2/A1)m
m=1-2
For A1=A2 Ions would bombard the target and the deposited layer
BIAS SPUTTERING - Small (-) Bias @ the Wafer Chuck50 – 300V on wafers 700 – 2000V on target
For :
• precleaning = sputter etch
• better planarity step coverage
• properties (stress, compos.)
Not used much particulates from flaking
Use High Density Plasma CVD instead or
Collimated Sputtering and Ionized Sputtering
small Wider arrival
in
extended sources = not point sources evap;in point sources
Collimate the beam by using holes to direct the ions to the wafers : that
Ionized Sputter Deposition or HDP Sputtering
DC target bias
RF substrate bias
Inductivelycoupled RF
antenna
Al →
Al+ + e-
Al target
• In some systems the depositing atoms themselves are ionized. An RF coil around the plasma induces collisions in the plasma creating the ions (50-85% ionized).
• This provides a narrow distribution of arrival angles which may be useful when filling or coating the bottom of deep contact hole.
a) b)
Highly directional fluxBetter solution than a collimator (holes)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
VARIOUS DEPOSITION TECHNIQUES
3326AsH,PH,BH
give better step coverage than sputtering
0.5 – 2 torr 80 – 200 torr
Barrier
plugs
400 – 7000C
VLSI !
• mass transfer regime
• T oxide evaporation
• Cl- cleaning (HCL etc)
& better doping control
• Selectivity with Cl, poor for SiHCL
porous BPSG 4-8% B, P)
reflow for planarization, steam, N2 ! Al – TIBA or
DMAH Al-H C - better Cu or Al-Cu
sputtered on CVD Al diffusion @ 400 0C
= salicide
Low T: -Si instead of poly_Si
Conditions: density of SiO2, step coverage, contaminations (C, H, N) all that determines T, pressure and gas used.
TEOS
LPCVD (conformal, 650-800°C)
Polysilicon@ low T amorphous Si
columnar structure
As & P deposition rate of poly – Si use doping after poly deposition
B Vpoly - Si
As, P segregate @ the grain boundaries ( B does
not ! )
625 °C
Models and Simulation
Ar +
Direct flux,neutrals
Al
Resputtered flux
Desorbed(emitted)
flux
Redeposited fluxes
Al
Al
Surface diffusion flux
AlAl+ Direct flux, ions
€
Fneti =Fdirect(neutrals)
i + Fdirect(ions)i + Fredep
i + Fdiff .ini
−Femittedi −Fsputtered
i −Fdiff .outi
• Within the past decade, a number of simulation tools have been developed for topography simulation. • Generalized picture of fluxes involved in deposition. (No gas phase boundary layer is included, so this picture doesn't fully model APCVD.)• Essentially the same picture will be used for etching simulation (in Chapter 10).
(14)
• To simulate these processes, we need mathematical descriptions of the various fluxes. • Modeling specific systems involves figuring out which of these fluxes needs to be included.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
• Finally, ions striking the surface can sometime enhance the deposition rate (by supplying the energy to drive chemical reactions for example), so that
€
Fion−inducedi =K i ∗Fions
i (22)
LPCVD Deposition Systems
€
Fdirect(neutrals)i Yes
Fdirect( ions)i No
Fdiff (net)i =Fdiff ( in )
i −Fdiff (out)i No
Femittedi Yes
Fredep(emitted)i Yes
Fsputteredi No
Fredep(sputtered)i No
Fion−inducedi No
Furnace - with resistance heaters
Standup wafers
Direct flux,neutrals
Desorbed(emitted)
flux
Redeposited fluxes • In these systems there are no ions involved and hence no sputtering. Surface diffusion also is usually not important.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
PECVD Deposition SystemsRF power input
Electrode
WafersPlasma
Gas outlet, pump
Heater
Gas inlet( SiH4, O2)
Direct flux,neutrals
Desorbed(emitted)
flux
Redeposited fluxes
+ Direct flux, ions
€
Fdirect(neutrals)i Yes
Fdirect( ions)i No
Fdiff (net)i =Fdiff ( in )
i −Fdiff (out)i No
Femittedi Yes
Fredep(emitted)i Yes
Fsputteredi No
Fredep(sputtered)i No
Fion−inducedi Yes
• In these systems an ion flux can enhance the deposition rate by changing the surface reactions. Sputtering is usually not significant because the ion energy is low, nor is direct deposition of ions significant.
€
rate=ScKdFd( ) + K iFi( )
N• Thus (25)
where Kd and KI are relative rate constants for the neutral and ion-enhanced components respectively.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Ionized PVD Deposition Systems
+Direct flux,
neutrals
Resputtered flux Desorbed(emitted)
flux
Redeposited fluxes
Direct flux, ions+
DC target bias
RF substrate bias
Al → Al+ + -e
Al target
€
Fdirect(neutrals)i Yes
Fdirect( ions)i Yes
Fdiff (net)i =Fdiff ( in )
i −Fdiff (out)i No
Femittedi Yes
Fredep(emitted)i Yes
Fsputteredi Yes
Fredep(sputtered)i Yes
Fion−inducedi Yes
• These systems are complex to model because both ions and neutrals play a role.• They are often used for metal deposition so that Ar+ ions in addition to Al+ or Ti+ ions may be present.• Thus almost all the possible terms are included
€
rate=ScFd( ) + Fi − K spYFi( ) + K rdFrd( )
Nwhere Fd includes the direct and redeposited (emitted) neutral fluxes, Fi includes the direct and ion-induced fluxes associated with the ions, and Frd models redeposition due to sputtering.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
High Density Plasma CVD Deposition Systems
gas inlet
plasma
magnetic coil
RFbias supply(13.56 MHz)
wafer
gas outlet,pump
Microwavesupply
(2.45 GHz)
Resputtered flux
Redeposited fluxes
Direct flux, ions+
+
• Very similar to IPVD (except neutral direct flux not as important):
€
rate =KiFi( ) − KspYFi( ) + KrdFrd( )
N(29)
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Models in SPEEDIE
LPCVD:
PECVD:
Standard PVD:
High T PVD:
Ionized PVD:
HDP CVD:
€
rate= ScFddensity
€
Fd = Fdirect(neutrals)i + Fredep(emit)
i( )
€
rate=ScKdFd( ) + K iFi( )
density
€
Fi =Fions( )
€
rate= ScFddensity
€
rate=ScFd + Ds
kTγsΩ∂
2K
∂s2
density
€
rate=ScFd( ) + Fi − K spYFi( ) + K rdFrd( )
density
€
rate=ScK iFi( )− K spYFi( ) + K rdFrd( )
densitySILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Calibration of Models - Example: SPEEDIE
Overhang test structure allows calibration of different components
o Neutral Precursor • Ions θ SiOx•
••o(1)
(2)(4)
(3) θ θ
(1) CVD component(2) - Ion induced deposition(3) - Sputtering with angle dependent sputter yield(4) Redeposition(5) Backscattered deposition
(5)
- Poly Si overhangSiO2
•
θ
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
DIRECT DEPOSITION
SURFACE DIFFUSION
DEPOSITION PRECURSORS
POLY-Si OVERHANG
SILICON SUBSTRATE
OXIDE
16 µm
1-4 µm
RE-EMISSION
OVERHANG TEST STRUCTURE
INDIRECT DEPOSITION
BY OBSERVING DEPOSITION PROFILES IN THE CAVITY CONCLUSIONS CAN BE DRAWN ABOUT THE DEPOSITION MECHANISMS
* TAPERING OF THICKNESS ON TOP SURFACE
* INFLUENCE OF CAVITY HIGHT ON DEPOSITION ON THE UNDERSIDE
J.P. McVittie, J.C. Rey, L.Y. Cheng, and K.C. Saraswat, "LPCVD Profile Simulation Using a Re-Emmission Model", IEDM Tech. Digest, 917-919 (1990).
L-Y. Cheng, J. P. McVittie and K. C. Saraswat, " Role of Sticking Coefficient on the Deposition Profiles of CVD Oxide, "Appl. Phys. Lett., 58(19), 2147-2149 (1991).
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
PECVD LPCVD
J.P. McVittie, “Test Structure and Modeling Studies of Deposition and Etch Mechanisms”, Talk TC1-WeM6, AVS mtg in Orlando, Florida, 1993
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Parameter Values for Specific Systemsn
(exponent in cosinearrival angledistribution)
SC
(stickingcoefficient)
Sputter deposition-standard ~ 1 - 4 ~1-ionized orcollimated
8 - 80 ~1
Evaporation 3 - 80 ~1
LPCVD silicon dioxide- silane 1 0.2 - 0.4-TEOS 1 0.05 - 0.1
LPCVD tungsten 1 0.01 or lessLPCVD polysilicon 1 0.001 or less
• PVD systems - more vertical arrival angle distribution (low pressure line of sight or field driven ions). n > 1 typically.• CVD systems provide isotropic arrival angle distributions (higher pressure, gas phase collisions, mostly neutral molecules). n ≈ 1 typically.• PVD systems usually provide Sc of 1. Little surface chemistry involved. Atoms arrive and stick.• CVD systems involve surface chemistry and Sc <<1. Molecules often reemit and redeposit elsewhere before reacting.CVD systems provide more conformal deposition.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Topography Simulation (Using SPEEDIE)‘
microns-2.0 -1.0 0.0 1.0 2.0
-0.5
0.0
0.5
1.0
1.5
2.0
microns
a)‘
microns-2.0 -1.0 0.0 1.0 2.0
-0.5
0.0
0.5
1.0
1.5
2.0
microns
c)
• SPEEDIE simulations for LPCVD deposition of SiO2 with Sc = 1 (which is more typical of PVD than LPCVD) and varying values of n, the arrival angle distribution factor: (a) n=1; (c) n=10.• Worse step coverage results as n increases (the arrival angle distribution narrows).• Even for n = 1, conformal coverage is not achieved.
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
a)
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
a)
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
b)
• SPEEDIE simulations for LPCVD deposition of SiO2 in a narrow trench with the same isotropic arrival angle distribution (n=1) but different values of Sc: (a) Sc = 1; (b) Sc = 0.1; and (c) Sc = 0.01.• Reducing Sc is much more effective than changing n if conformal deposition is desired.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Simulations
90˚ 85˚ 80˚
• Results of SPEEDIE LPCVD simulations with the sidewall angle changed. Sc = 0.2 and n = 1. Note the improved trench filling.
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
a)
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
b)
• SPEEDIE simulations comparing LPCVD and HDPCVD depositions. (a) LPCVD deposition of SiO2 over rectangular line. Sc = 0.1 and n = 1. (b) HDPCVD deposition, with directed ionic flux and angle-dependent sputtering, over rectangular line showing much more planar topography.• CMP might still be required in the HDPCVD case to fully planarize the surface.
Simulations - CVD
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
c)
‘
-1.00 1.000.0-0.5
0.0
0.5
1.0
1.5
2.0
microns
microns
d)
• SPEEDIE simulations comparing LPCVD and HDPCVD depositions. (c) LPCVD deposition in trench, showing void formation. Sc = 0.2 and n = 1. (d) HDPCVD deposition in trench, showing much better filling.• HDPCVD has a strong directed ion component and any overhangs that form are sputtered away.
0.5 micron
oxide
metal
0.5 micron
oxidemetal
• Actual SEM images of HDP oxide deposition.
Simulations - CVD
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ
Summary of Key Ideas
• Thin film deposition is a key technology in modern IC fabrication.• Topography coverage issues and filling issues are very important, especially as geometries continue to decrease. • CVD and PVD are the two principal deposition techniques.• CVD systems generally operate at elevated temperatures and depend on chemical reactions.• In general either mass transport of reactants to the surface or surface reactions can limit the deposition rate in CVD systems. • In low pressure CVD systems, mass transport is usually not rate limiting.• However even in low pressure systems, shadowing by surface topography can be important. • In PVD systems arrival angle distribution is very important in determining surface coverage. Shadowing can be very important.• A wide variety of systems are used in manufacturing for depositing specific thin films. • Advanced simulation tools are becoming available, which are very useful in predicting topographic issues.• Generally these simulators are based on physical models of mass transport and surface reactions and utilize parameters like arrival angle and sticking coefficients from direct and indirect fluxes to model local deposition rates.
SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin
© 2000 by Prentice HallUpper Saddle River NJ