Thermal Management at Nanoscale - PSMA · 2/1/2010 · Thermal design power is the maximum sustained power dissipated by the microprocessors Æ TDP was increasing with increasing

Alexander A. BalandinNano-Device LaboratoryDepartment of Electrical Engineering andMaterials Science and Engineering ProgramUniversity of California – Riverside

Thermal Management at NanoscaleThermal Management at Nanoscale: : Problems and Opportunities Problems and Opportunities

APEC, Palm Springs, February 2010

Alexander A. Balandin, University of California - Riverside2

UCR Bell Tower

City of Riverside

UCR Botanic Gardens

Joshua Tree Park, California

UCR Engineering Building

Alexander A. Balandin, University of California - Riverside

Nano-Device Laboratory (NDL) Department of Electrical Engineering University of California – Riverside

Profile: experimental and theoretical research in nano materials and devices

Research at NDL is funded by NSF, ONR, SRC, DARPA, NASA, ARO, AFOSR, CRDF, as well as industry, including IBM, Raytheon, TRW, etc.

Research & Applications

Raman, Fluorescence and PL Spectroscopy

Electronic Devices and

Circuits

Optoelectronics

Direct Energy Conversion

Bio- Nanotech

Thermal and Electrical Characterization

Device Design and Characterization

Nanoscale Characterization

Theory and Modeling

PI: Alexander A. Balandin


Outline

MotivationsDownscaling and the thermal issuesHigh-power density electronics and heat removalNew approaches for thermal management High-heat-flux method and hot-spot spreading

Thermal Conductivity of GrapheneNew non-contact measurement techniqueGraphene vs carbon nanotubes

New possibilitiesConclusions

Trench

Graphene


The Thermal “Show Stopper” for Electronics

IEEE Spectrum illustration of the thermal issues in the feature article

A.A. Balandin, Chill Out: New Materials and Designs Can Keep Chips Cool (October 2009)

No BIG fan solutions!

The old industry approach does not work


Trends: Increase in Thermal Design Power

6

Thermal design power is the maximum sustained power dissipated by the microprocessors

TDP was increasing with increasing performance complicating thermal management.

The switch to multi-core designs

Data is after R. Mahajan et al., Proceed. IEEE (2006)

The problem of hot spots:

Non-uniform power densities Power densities above 500 W/cm2


ITRS: Thermal Management Issues

7

IC performance is now limited by the power, which can be dissipated without exceeding the maximum T set by the reliability requirements.

ITRS: power consumption, both dynamic and static, related to unavoidable leakage currents, is an urgent challenge.

In the next five years up to 80% of microprocessor power will beconsumed by the interconnect wiring (compare to 51% at 130 nm node).

Power dissipation in the interconnect structure will increase dramatically due to higher clock frequencies and increase in the number of metal layers and interfaces.

Joule heating in the interconnects may result in significantly higher temperature rise as compared to power dissipated in active devices.


New Aspects of Thermal Transport in Nanoscale Devices and Circuits

8

New Phenomena at Nanoscale:Acoustic phonon MFP in bulk crystalline

Si at T=300K (Debye model): ~ 50 nm

Comparison: electron MFP in Si: 7.6 nm

Dominant phonon wavelength in Si

1.4 nm at T=300 K or 4 mm at T=0.1 K

Device Feature Sizes

CMOS gate length < 50 nm

CMOS gate-oxide thickness ~ 1.2 nm

Superlattice period: ~ 1.5 nm

Technology Trends:

Increasing number of interconnects

Increasing power density

Increased leakage current

High switching frequencies

Increased thermal resistance of the chip

Thermal boundary resistance

Materials with low thermal conductivity

Nanostructured materials do not conduct heat as well as bulk materials

modified from IBM picture


Thermal Issues in High-Power Density Electronics: GaN FETs

Strategy: Incorporation of the thermal management constrains early at the device design stage

-4 -3 -2 -1 0 1 2 3 40

20

40

60

80

100

120

140

Tran

scon

duct

ance

(mS/

mm

)

Gate-Source Voltage (V)

25C 50C 100C 150C 200C 250C

Vds=6V

W.L. Liu, V.O. Turin, A.A. Balandin, Y.L. Chen and K.L. Wang, MRS J. of Nitride Semi Research, 9, 7 (2004).

200 nm n – GaN Active Layer

3 μm SI GaN Buffer

R bd

100 - 300 μm Substrate


300 400 500 600 700 8000

20

40

60

80

100

120

140

160

TEMPERATURE (K)

THER

MA

L C

ON

DU

CTI

VITY

(W/m

-K) Si Bulk Diffuse Scattering (p=0)

Si Nanowire: A

Si Nanowire: B

The “Nano-Problem”: Thermal Conductivity Degradation at Nanoscale

Thermal conductivity definition:

TKAQ ∇−=/&RT thermal conductivity values for important materials:

Si: 145 W/mK

SiO2 : 1-13 W/mK

GaN: 150-300 W/mK

Diamond: 1000 – 2200 W/mK

Graphite: 200 – 2000 W/mK

CNTs: 3000 – 3500 W/mK

J. Zou and A.A. Balandin, J. Appl. Phys., 89, 2932 (2001).

Phonon - boundary scatteringPhonon spectrum changes


Composite Substrates: Diamond Materials For Hot Spot Spreading

New Developments:

Si wafers become thinner (consider the effects on the Si cost of the rapid developments in solar cells)

Progress in synthetic diamond deposition and growth

Diamond heat spreaders will be closer to heat generation areas in thinned Si wafers

Issues:

Compatibility with Si CMOS

Cost

Finding an optimum combination of material properties: grain size vs thermal conductivity vs. interface quality vs. temperature of deposition

Micro-crystalline diamond on Si

Nano-crystalline diamond on Si


Finding the Optimum Synthetic Diamond - Si Combination

10 20 30 40 50 60 70 80 90 10085

86

87

88

89

90

91

92

93

94Ultra-nano-crystalline diamondon silicon substrate

Ther

mal

Con

duct

ivity

, K (W

/mK

)

Temperature (0C)200 400

10-3

10-2

10-1

100

101

102

Hopping Model (22nm, t=0.32)

Hopping Model (26nm, t=0.2)

Minimum K for Carbon

Hopping Model (2μm, t=0.9)

Bulk Diamond: Callaway Model

Ther

mal

Con

duct

ivity

(W/c

mK

)

Temperature (K)

Poly NCD_25 NCD_0

Nanocrystalline diamond offers smoother interface but lower thermal conductivity

Minimization of the thermal boundary resistance (TBR)


New Unique Material Option: Graphene

Individual atomic layers of sp2-hybridized carbon bound in two-dimensions. Crystalline graphite is composed of graphene layers.

“Unrolled Carbon Nanotube”

“Graphene Revolution” brought about by K.S. Novoselov and A.K. Geim (Manchester, UK and Chernogolovka, Russia) with the help of bulk graphite and something similar to a Scotch tape.

[Novoselov, et al., Science (2004)].


1 10 100 1000 100001E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6Double-Gate Graphene Transistor

VDS=0.05 V

Nor

mal

ized

Cur

rent

Noi

se D

ensi

ty (H

z-1)

Frequency (Hz)

VG=0 VVG=10 VVG=20 VVG=30 VVG=40 V

1/f

G. Liu, et al., Appl. Phys. Lett., 95, 033103 (2009).Q. Shao, et al., IEEE Electron Device Lett., 30, 288 (2009).

Practical Applications of Graphene: Transistors and Interconnects


Issues:Insulator vs conductorAnisotropy Thermal expansionTemperature stabilityLarge-area

Prospects of the High-Heat Flux Thermal Management with Graphene

Concept change: from the post-chip making level to the device and materials level consideration at nanoscale

Passive high-heat flux thermal management at the device/chip level

Possible Material Systems:Synthetic diamondCarbon nanotubesGraphene


Conventional Measurement Techniques Do Not Work for Graphene

Cr/Au heater- thermometer sensors patterned on top of the samples by photolithography.

3-ω Thermal Conductivity Setup Transient Plane Source Technique

0 1 2 3 4 50.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

Measurement Time: 5 s

Dissipated PowerSample: 0.05 W Si Wafer: 0.5 W

TEM

PER

ATU

RE

RIS

E (o C

)

TIME (s)

SILICON REFERENCE SAMPLE

Thermal conductivity and heat capacity extraction from the T(t) dependence.

Laser – Flash Technique


Micro-Raman Spectroscopy of Graphene

Alternatives:

low-temperature transport study

cross-sectional TEM

Optical visualization on “magic” substrates

AFM inspection

Disorder D band: ~ 1350 cm-1: in-plane A1g (LA) zone-edge

G peak: double degenerate zone center E2g mode

A.C. Ferrari et al., Phys. Rev. Lett. 97, 187401 (2006).

I. Calizo, A.A. Balandin et al., Nano Letter 7, 2645 (2007)


2D-band features of graphene on a standard Si/SiO2 (300nm) substrate are highly reproducible and, together with the G-peak position, can be used to count the number of graphene layers.

Raman Nanometrology of Graphene Layers

2300 2400 2500 2600 2700 2800 2900 30000

4000

8000

12000

16000

20000

24000

Inte

nsity

(arb

. uni

ts)

Raman Shift (cm-1)

Graphene @ 300Kλ exc = 488 nm

1 layer

2 layers

3 layers

4 layers

5 layers

Deconvolution of 2D band

Double-resonance model

I. Calizo, et al., Appl. Phys. Lett., 91, 201904 (2007).

I. Calizo, et al., Appl. Phys. Lett., 91, 071913 (2007).


IEEE Spectrum illustration of the first measurements of thermal conductivity of graphene carried out at UCR.

See details in A.A. Balandin et al., Nano Letters, 8, 902 (2008).

SEM image of the suspended graphene flake connected to heat sinks

UCR Experiment: Heating Up Graphene


Experimental Approach and Suspended Graphene Layers

Trench

TrenchSLG

FLG

substrate

FLG

Graphene flakes suspended across trenches in Si/SiO2 wafers


Extraction of the Thermal Conductivity Data: Raman Spectrometer as a Thermometer

Excitation laser acts as a heater: ΔPG

Raman spectrometer acts as a thermometer: ΔTG=Δω/χG

Thermal conductivity: K=(L/2aGW)(ΔPG/ΔTG)

1( / 2 ) ( / ) .G G GK L a W Pχ ω −= Δ Δ

0 1 2 3 4

-6

-4

-2

0

2

4

SLOPE: -1.292 cm-1/mW

SUSPENDED GRAPHENE

G P

EAK

POSI

TIO

N S

HIF

T (c

m-1)

POWER CHANGE (mW)

EXPERIMENTAL POINTS LINEAR FITTING

-200 -150 -100 -50 0 50 1001576

1578

1580

1582

1584

1586

1588

1590

1500 1550 1600 1650

3,000

4,500

6,000

7,500

G P

eak

Posi

tion

(cm

)-1

Temperature ()°

G Peak Position Linear Fit of Data

Single Layer Graphene

slope = -0.016 cm-1/ °C

Inte

nsity

(arb

. uni

ts)

Raman Shift (cm-1)

Single LayerGrapheneλexc=488 nm

G Peak1582 cm-1


Graphene Heat Spreaders Designs for Active Devices and Interconnects

Heat Sink

Heat Sink

Silicon Substrate (500μm)

Graphene

SiO2

(100 nm) Heat Sink

S. Subrina, D. Kotchetkov and A.A. Balandin, IEEE Electron Device Letters, 30, 1281 (2009).


Nanoscale Phonon Engineering: New Possibilities for Improved Heat Removal

Theory: V.A. Fonoberov and A.A. Balandin, Nano Letters, 6, 2442 (2006).


Other 2D Crystals with Wan der Waals “Gaps”: Thermoelectric Applications

Quintuple thickness: ~1 nm

Identification: AFM, SEM, TEM

(a)

1 μm

Overlapping Regions

1 μm


COVER IMAGE: Applied Physics Letters, February 1, 2010

Active On-Spot Cooling of Nano-Devices


The Route to Three-Dimensional Electronics

IEEE Spectrum artistic rendering of the future 3D electronic chips with graphene transistors, graphene interconnects and heat spreaders, CNT electrical and thermal vias. After A.A. Balandin, Chill Out: New Materials and Designs Can Keep Chips Cool (October, 2009).

Is Carbon the Answer?


Conclusions

Heat dissipation is a crucial problem for nanometer scale devices and ULSI chips Thermal conductivity of most materials deteriorates when they are structured at nanometer scaleThere are some materials, which maintain or even improve heat conduction property at nanoscale: grapheneGraphene can be used for hot-spot spreading in the active devices and interconnectsPossibility for the high-power electronics: better thermal interface materialsConcept change for thermal management: from post-chip design effort to materials/device level effort


Acknowledgements

Balandin group in front of the Nano-Device Laboratory (NDL), 2008

Documents

Thermal Management at Nanoscale - PSMA · 2/1/2010 · Thermal design power is the maximum sustained power dissipated by the microprocessors Æ TDP was increasing with increasing