Embed Size (px)
Citation preview
Microelectronics Reliability 48 (2008) 1505–1508
Contents lists available at ScienceDirect
Microelectronics Reliability
journal homepage: www.elsevier .com/locate /microrel
Thermal heating within SOI
J.J. Koning a,*, S. Lecaudey b,1, E. Spaan c, M. Stoutjesdijk d, J.H.J. Janssen e
a NXP Semiconductors, Site Innovation and Technology Nijmegen, Gerstweg 2, Building FB2.081, 6534 AE Nijmegen, The Netherlandsb NXP Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlandsc NXP Semiconductors, Gerstweg 2, Building FB2.080, 6534 AE Nijmegen, The Netherlandsd NXP Semiconductors, Gerstweg 2, Building FB2.109, 6534 AE Nijmegen, The Netherlandse NXP Semiconductors, Gerstweg 2, Building BY1.055, 6534 AE Nijmegen, The Netherlands
a r t i c l e i n f o
Article history:Received 7 July 2008Available online 16 August 2008
0026-2714/$ - see front matter � 2008 Elsevier Ltd. Adoi:10.1016/j.microrel.2008.07.057
* Corresponding author. Tel.: +31 (0)24 3535128.E-mail addresses: [email protected] (J.J. K
caramail.com (S. Lecaudey), [email protected] (E.nxp.com (M. Stoutjesdijk), [email protected] (J.H
1 Present address: A+-Metrologie, BP70117, F-50110
a b s t r a c t
Heat diffuses from hot power devices to neighboring components such as bondpads, which shortens thelifetime of bond balls. SOI is a technology with advantages for integrated power applications. For this rea-son heat transport between components within one SOI die has been measured experimentally. The ther-mal time constants are determined. Inside an SOI transistor the heat propagates with 1 lm/ls typicallyuntil other time constants take over.
� 2008 Elsevier Ltd. All rights reserved.
1. Introduction
A Silicon-On Insulator (SOI) process has many advantages over aconventional junction isolated process. Latch-up is eliminated, par-asitic capacitances to substrate are small and leakage at high tem-peratures is absent, oxide walls or trenches increase packingdensity for high voltages [1]. In power applications self-heatingcan be limiting the lifetime, like it has been shown for audio ampli-fiers [2]. On a timescale of 20 ms typically, the chip and the pack-age heat up until equilibrium establishes with higher temperaturein the heating components, causing electro-migration to limit thelifetime of the components. However, we suggest that transportof heat from hot components to other components is also impor-tant on shorter timescales. Within the die a locally generated heatpulse will travel laterally to other circuit parts. Local changes oftemperature and gradients cause variations in resistances, thresh-old voltages, bandgap reference voltages, mismatch of resistorsand transistors, and it causes cross-sensitivity in sensors, whichis all to be modeled. A particularly interesting example of fruitfuluse of such intra-die heat transport has been shown recently byusing a thermal delay line as a time reference [3]. However, inthe case of integrated power devices thermal transport might evenlimit the lifetime of the bond balls close to the device due to theheat diffusion in the top layer within the SOI chip. In Ref. [4] con-siderable aging of bond balls has been shown if the storage tem-
ll rights reserved.
oning), sebastien.lecaudey@Spaan), [email protected]. Janssen).Tourlaville, France.
perature is increased from 150 �C to 200 �C resulting in a reducedjoint strength.
In the case of SOI the modeling of heat transport is complicatedby the factor 100 larger heat resistance of SiO2, the buried oxidelayer. There is a need for a reliable measurement of the rise of tem-perature in the chip and its time dependence. For this, a chip testmodule has been created (Fig. 1). The die has been processed inthe A-BCD2 SOI process at NXP Semiconductors Nijmegen [1].The SOI layer has a thickness of 1.35 lm, the buried oxide layeris 1.0 lm, and the handle wafer substrate is 375 lm.
To study the heat transport in SOI a P-type DMOS serves as aheat source and three diodes serve as temperature sensors, placedat distances from the heater transistor of 300 lm, 630 lm and825 lm for diodes 1, 2 and 3 respectively. Also, the left-upperNDMOST in Fig. 1 has a built-in temperature sensing diode in itscenter. In A-BCD2 all devices are dielectrically isolated by a ringof about 3 lm SiO2, except for the sensing diode in the NDMOST.
2. Experimental part I
The power on the transistor has been applied as a body–draincurrent (IDB) through the diode constituted by drain and body junc-tion. The body is shorted to the source as they share the samesource-metal, while the gate is shorted to the drain externally inorder to avoid a floating gate. Diode temperature sensor calibrationhas been realized in a controllable hot oven at fixed current(I = 100 lA). Heating of the temperature sensing diodes translatesinto a decreasing forward voltage.
On the three sensing diodes a sensitivity factor of �1.4 mV/Khas been determined for the chosen current settings. The rise oftemperature versus time has been recorded with T3Ster software[5]. The measurements have been performed at three different
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0E-04 1.1E-03 2.1E-03 3.1E-03 4.1E-03time (s)
ΔT(
K)
P=0.2WP=0.32WP=0.5W
Fig. 3. Zoom of Fig. 2.
0
5
10
15
20
25
0 200 400 600 800 1000time (s)
ΔT (K
)
diode 1 diode 2 diode 3
Fig. 4. Rise of temperature versus time with P = 0.32 W.
Fig. 1. Layout displaying heater and three sensing diodes, plus Ndmos includingintegrated sensing diode.
0.4
0.6
0.8
1.0
1.2
1.4
1.6
ΔT (K
)
diode 1 diode 2 diode 3
1506 J.J. Koning et al. / Microelectronics Reliability 48 (2008) 1505–1508
DC powers: P = 0.22 W, P = 0.32 W and P = 0.50 W. The die has beenglued with glue containing silver grains and wire-bonded in asealed ceramic package, and the package is placed in a socket.
3. Results
On the three sensing diodes the rise of temperature versus timefor three different values of power has been recorded. Typical re-sults are shown in Fig. 2.
The delay time before arrival at the diode is better shown in amore detailed graph (Fig. 3). Fig. 3 shows that the time it takesfor the heat pulse to arrive at the sensing diode is largely indepen-dent of the amplitude of the heat pulse for this small temperaturescale. The same measurement has been carried out on all threesensing diodes.
The diodes approach different final temperatures in steady state(Fig. 4). This is expected as the steady state heat flow from heaterto package and socket causes the closest diode to be the hottest.
For a heater power P, the diodes heat up DT:
Diode 1: DT/P = 75 K/WDiode 2: DT/P = 66 K/WDiode 3: DT/P = 61 K/W
This shows that self-heating by a power device will cause con-siderable rise of temperature as a function of distances in the chip.Dissipation of milli-Watts will result in temperature rise of up to atenth of a degree on several hundreds micron distance, given thethermal resistance of package and socket. In the zoom, Fig. 5, it isshown that the heat pulse arrives earliest at the nearest diode.
0
5
10
15
20
25
30
35
40
0 200 400 600 800 1000time (s)
ΔT(K
)
power=0.2Wpower=0.32Wpower=0.55W
Fig. 2. Rise of temperature versus time for the diode no. 3 at varying heating power.
0.0
0.2
1.E-04 1.E-03 2.E-03 3.E-03time (s)
Fig. 5. Zoom of Fig. 4.
We assume an absolute uncertainty on our temperature sensorof 1 �C. Due to the set-up, we assume another uncertainty of 1 �C.In total 2 �C of accuracy is a reasonable value.
4. Analysis
The software supplied with the T3Ster equipment [4] uses anevaluation technique based on the NID method (Network Identifi-cation by Deconvolution). The ultimate results of the evaluationare the structure functions, see Ref. [6]. Result of such a deconvo-lution is shown in Fig. 6.
0102030405060708090
100
1.E-04 1.E-02 1.E+00 1.E+02time (s)
Rth
(K/W
)
diode 1
diode 2
diode 3
Fig. 6. Thermal time constants during heating up with 0.32 W.
Fig. 7. Thermal time constants, zoom of Fig. 6.
Table 1Thermal diffusion constant of heat in SOI
Diode Distance (lm) Time (ms) a (cm2/s)
1 300 3 ± 1 0.302 630 16 ± 2 0.253 825 25 ± 3 0.27 Fig. 8. Typical oscilloscope display during a pulse of 80 ls. VG = 3.5 V, VDS = 4 V,
IDS = 24 mA, DVdiode = 24 mV.
0
10
20
30
40
50
60
70
80
90
1.E-04 1.E-02 1.E+00 1.E+02 1.E+04time(s)
Rth
(K/W
)
Fig. 9. Finite element PStar simulation reproducing the experimentally determinedthermal constants in Figs. 6 and 7.
J.J. Koning et al. / Microelectronics Reliability 48 (2008) 1505–1508 1507
The time constants are modeled as heat capacitances Cth andthermal resistances Rth. The two large peaks on the right are dueto the package and the socket respectively. The three first peaksare interpreted as being due to the substrate silicon of the die,the glue between die and lead-frame, and the lead-frame itself.
Fig. 7 shows that the first time constant depends on the distancebetween heater transistor and sensing diode. For diode 1 the reflec-tion of heat inside the die seems to be visible as a broadening to-wards the second peak. With the diode 3 placed at 825 lm only 5peaks are distinguished, as the two first peaks seem to havemerged. The resulting time constants in SOI die are given Table 1.The thermal diffusion constant a is found to be 0.27 cm2/s inaverage.
5. Experimental part II
The second experiment serves to determine the time constantfor heat transport inside the SOI transistor. The NDMOST in Fig. 1
encloses a sensing diode in order to measure the very fast temper-ature rise inside the SOI transistor. A junction of N-Well and SPconstitutes this diode. The distance from the diode junction tothe MOSFET is about 10 lm.
Both the calibration of this diode and the measurements havebeen done on a wafer placed on a controllable hot chuck. For a cur-rent of 10 lA and temperatures from 20 �C to 200 �C, we found asensitivity of �1.8 mV/K.
The pulse duration has been fixed by the gate voltage during themeasurement. Pulse durations were 50 ls, 80 ls, 100 ls and 1 ms.The measured quantity is the voltage drop over the diode. Fig. 8shows a typical oscilloscope screen with VDS, IDS, VG, and Vdiode.The thermal time constant is estimated from the slope of Vdiode giv-ing about 1/4th of a division: s = 1 ls ± 3 ls. This is the time ittakes to heat up the diode inside the ND-MOSFET.
6. Simulation
The finite element simulation is based on a 3D lumped RC cir-cuit with thermal resistors and capacitors in PSTAR. It accountsfor eight layers: the SOI layer, the Buried Oxide layer, four layers
1508 J.J. Koning et al. / Microelectronics Reliability 48 (2008) 1505–1508
for the substrate, a layer for the die-attach glue, and one for thelead-frame, package and socket. Simulation results are shown inFig. 9. The four large peaks are fits to the data. The phenomenonunder study explains the transport in the SOI die qualitatively verywell. The heat diffusion coefficient in bulk silicon as found in [3] isabout three times larger as compared to our findings in this SOIwafer.
7. Conclusions
The thermal time constants in ABCD-SOI are characterized byusing SOI junction diodes as temperature sensors. With this set-up we are able to measure propagation of heat and subsequentheating of neighboring components within the SOI die, resultingin a lateral thermal diffusion constant of 0.27 cm2/s in the SOI sys-tem on a limited time scale. This number allows to estimate howfast the heat diffuses when a device gets warm and how hot sen-sors, MEMS, bond balls and other circuit components become onthe same die. Our conclusion is that transport of heat waves froman integrated power transistor to the nearest bond ball can makethe difference between a local temperature being 150 �C or200 �C which is shown to be limiting the strength of the bond ballas found in Ref. [4]. As a rule of thumb, within the SOI layer of1.35 lm thickness on top of a buried oxide layer of 1 lm, the heat
propagates within an SOI transistor on a short time scale withabout 1 lm per ls.
Acknowledgements
The second author would like to thank Huug van der Vlist, NXPNijmegen, and Jean Luc Chartier, University of Nantes for providingthe opportunity to realize this work. Part of this work has been pre-sented as a poster on the MME2005 workshop in Goeteborg [7].
References
[1] van der Pol Jacob A, Ludikhuize AW, Huizing HGA, van Velzen B, Hueting RJE,Mom JF, et al. In: Proceedings of the international symposium on powersemiconductor devices and processes (ISPSD), May 22–25; 2000. p. 327–30.
[2] Krabbenborg BH, van der Pol JA. In: Proceedings of the international symposiumon power semiconductor devices and processes (ISPSD), June 4–8; 2001. p. 157–60.
[3] Witte Johan F, Makinwa Kofi AA, Huijsing Johan H. In: Proceedings of SeSens ‘02,November 2002, and references therein. p. 696–9.
[4] Sun F, Hochstenbach P, van Driel WD, Zhang GQ. In: Proceedings of the 9thinternational conference on thermal, mechanical and multiphysics simulationand experiments in micro-electronics and micro-systems, EuroSimE2008. p.308–11.
[5] T3ster Hardware On-line Reference manual. <www.micred.com>.[6] Proceedings of the thermionic conference; 2003/2004. p. 168–9.[7] Lecaudey S, Koning JJ, Spaan E, Stoutjesdijk M. In: Proceedings of the 16th MME
micromechanics Europe workshop, 4–6 September 2005, Sweden. p. 288–91.
