The Radio Report

7/31/2019 The Radio Report

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The radio report: do I need to explain why I design the circuit and why I choose the value

of component like that in the circuit?

Yes the 3 page report, due in on the last day of term should explain:

The circuit, and how each module (aerial, tuning, demod, etc) works

How modules connect together

How you will build and test each module

Component values and why you have chosen them

Costs Note that the report should comprise:

Cover page (from labweb)

Circuit diagram Printout of the component order form (from labweb) The report (max 3 pages)

Radio design project


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Introduction

A radio receiver is an electronic circuit that can pick up a broadcasted signal from an antenna,

process it, and output it in an audible form. Radios can vary in complexity, quality and

efficiency depending on their design, yet the underlying principles are the same. This report

describes the design a simple, analogue, Amplitude Modulated (AM) radio receiver. It will first

outline the high-level view of the circuit before explaining each stage in more details.

AM radio signals are transmitted through electromagnetic (EM) waves travelling in air. When

they enter a conductor such as a metallic wire, they generate an alternating voltage proportional

to the amplitude and frequency of the wave. A radio receiver must pick up the signal and filter

out all unwanted frequencies. Then, it amplifies the signal to a reasonable level so as to be able

to separate the message from the carrier, or demodulate. Finally, it amplifies the power of the

signal and sends it to a speaker, which converts it to sound. This sequence of events is shown if

fig.1

Input stage and tuning

The aerial is chosen to be a 30cm wire such that the induced voltage is approximately

VE 1

2 E length =

1

2 1mV 0.3 = 0.15mV. The signal is band-pass filtered by a resonating LC

circuit that allows the user to tune on two different stations: Talk Sport 1053(kHz) AMandLBC

News 1152 AM. Since the two stations are 100kHz apart, the quality factor (Q) of the filter

should be

Q =f0

B=

1M

100k= 10. The smallest available inductor (

100mH) is chosen to minimise

parasitic effects. These can be modelled as a parallel ReffCparasiticLpure circuit whose component

values are calculated using

Reff =Q wL = 90 2p1.053M 100m= 60kW and

Demodulator

Fig.1 shows the high

level design of the AM radio

receiver.


3/11

Cparasitic =1

2pfSRF( )2L=10pF. Given that the capacitors have very high Q, the filters quality is

limited by the inductor and can be approximated as

Q =RT

wLwhere

RT = Reff //R . Using

Q =10 and

substituting in the equations gives

RT = 6.6kW and

R = 7.4kW.

The total capacitance required for resonance at 1.053MhZ and 1.152MHz is 228pF and 190pF

respectively and the tuning can be adjusted using a variable capacitor with a range of 6 to

120pF. As a result, an additional 120pF is needed in the parallel circuit.

Biasing the JFET

Before connecting the input to the amplification stage, it is important to make sure that the next

circuit will not affect the filter and the tuning. A JFET voltage follower with high input

impedance is therefore inserted after the LC filter to stop current from flowing out of the

potential divider it forms. To ensure its good operation, the JFET must be biased in saturation

mode with

VGS >Vth and

VDS VGS - Vth , explaining why the drain is directly connected to the

+9V supply and the source is set to 4V. Note that the gate of the JFET is grounded in quiescent

state because the inductor acts as a short circuit. From the data sheet, the parameters of the

JFET are:

Vth = - 3V,

Idss =10mA and

RDS =150W so

Id = Idss 1-VGS

Vth

2

=10mA 1-0 - 4

- 3

2

Id =1.111mA

1

Hence

RS

=4V

1.11mA= 3.6kW and

gm =2Idss

Vth= 6.66mS

Common Emitter amplifier

Once the signal is filtered, it needs to be amplified before demodulation can take place. This is

done using a single NPN transistor connected as a common emitter amplifier. The quiescent

conditions should be

V0 = 4.5V,

VE =1V and

IC =1mA to allow for largest voltage swing and

optimum operation. Computing resistance values:

RC

= 4.5/1mA = 4.5kW and

RE =1/1mA =1kW. The base of the transistor must be kept at 1.6V, or 0.6V above the emitter,

which requires a biasing circuit. Rearranging the potential divider formula, we can calculate the

1 Formula taken from Practical electronics for inventors, second edition, Paul Scherz, McGraw Hill.


4/11

ratio of resistors needed to keep

VB =1.6V:

R1

R2=VB

VCC - VB

=1.6

9- 1.6=8

37.

The actual resistor values are chosen such that their parallel impedance is greater than the

previous blocks output impedance and smaller than the CEs base input impedance. This way,

the voltage dividers output shouldnt be affected by load conditions. The output impedance of

the JFET voltage follower is

RS //1

gm=

RS

gmRS + 1=

3.6k

3.6k 6.66mS + 1=144W

The base DC input impedance of the BJT is

Rin(base)dc b REload =100 1k=100k

Making

R1 = 8k and

R2 = 37k results in a combined parallel impedance of

6.57k and is

consistent with the requirements.

Since the input of the CE has a different DC bias than the previous stage, an A.C coupling

capacitor is used to separate them in quiescent conditions. The capacitor forms a high-pass filter

with the amplifiers small signal input impedance so the capacitance required for the 3dB point

to be bellow 900kHz is:

C=1

Rin2pf3dB=

1

1.8k 2p900k=100pF. Similarly, the bypass capacitor at

the emitter forms a filter with

rtr =1

gm

= 25Whence

C=1

2pf rtr=

1

2p900k*25W= 7nF

Demodulation

The message signal is separated from the carrier using an envelope detector. The active BJT is

acting as a diode and the RC circuits time constant should be about 10 times smaller than the

period of the envelope. This way, the capacitor stores charge on the rising edge and releases it

slowly when the signal falls.

Since the output of the previous CE amplifier is at 4.5V D.C, there is no need for a new biasingcircuit at the base of the demodulating BJT provided its input impedance is large enough. As a

result, an additional BJT is added to form a Darlington pair, which can be modelled as a single

transistor with

= 1 b 2 and

VBE =1.2V. The new A.C. input impedance is increased by a

factor of

. An important drawback of this configuration is the longer response time, however,

this is less significant because the radio will not be connected in feedback circuits. For

IC =1mA and

VE = 3.3V,

RE = 3.3k hence calculating the value of the capacitor is


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straightforward:

C=0.1T

2pf RE= 7.57nF where T is the shortest period of the message signal2. Note

that the small signal output impedance is bellow 100 while the input impedance

RinAC = b1b 2 ZC =1002

1

2p1.1M 7.5n=192kW.

Power amplification

The final stage of the radio circuit is the power amplifier designed to increase the power and

voltage so as to send the signal to the earphones. The TDA7052A 1W mono audio amplifier

produced by Philips is chosen because of its appropriate characteristics and DC volume

controller. The input impedance of the amplifier circuit is 20k meaning it will not affect the

previous stage. Also, it is designed to power an 8 load, which is the approximate value of thechosen magnetic earphones.

Voltage gain

Assuming the signal picked up by the aerial has amplitude 0.15mV and that the earphones

operate between 20 and 40mV, a minimum voltage gain of 133 is needed. (max 266) The actual

voltage gain of the CE amplifier is found by taking in account input and output impedances and

is equal to -153. The Philips power amplifier can therefore supply any additional gain if needed.

Testing and building the circuit

Each stage of the radio should be tested independently before assembling the whole circuit. It is

probable that the value of some resistors will have to be changed as a result of material

parameters such as Vthreshold for the JFET. Careful attention should be given to testing the LC

circuit used for tuning since the Q and resonant frequencies were calculated using data sheet

parameters, which are likely to differ in reality. The self-resonant frequency of the inductor

could be measured experimentally so as to obtain a better value for its parasitic capacitance.

Also, it should be made sure that the tuning capacitor effectively changes the resonant

frequency by a 100kHz.

The circuit will be mounted on a Veroboard with copper tracks. It is important to lie out the

circuit such that high gain stages do not couple with the weak input signal, producing feedback.

Finally, capacitors should be implemented with the least possible wiring to avoid self resonance

2 For AM signal, the bandwidth is 4kHz hence

T= 0.25ms


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and parasitic effects.


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Voltage gain

The AC input impedance of the CE amplifier with grounded emitter (because of bypass

capacitor) is

Ri = RB rbe = RBb

gm

=1.8kW. Output impedance for CE amplifier is

Ro = RC ro = RCVA

IC= 4.3kW

, which is quite high. Finally, the ideal gain is


8/11

K= - gm RC //ro( ) = - 40mS 4.5k//120k( ) = - 173 and the true gain is

Av =Rin

RS + RinK( )

RL

Ro + RL=

1.8k

145+1.8k- 173( )

192k

4.3k+192k

Av = - 156

Radio design project

Input circuit and aerial

The aerial picks up the signal emitted by the radio station. The impedance of free space is 376

so the antenna can be modelled as a Thevenin source in series with a 376 resistor. The signal

then goes through a band-pass filter made from a parallel LC circuit. To avoid any loss of the

signal, the load of the input circuit must be much larger than the one of free space. This explains

why the input is connected to a voltage follower JFET.

JFET

The JFET is N type hence its threshold voltage is negative. From a page found on the web3the

equations defining the behaviour of the JFET are the following.

Drain current (active)

Id

= Idss

1-V

GS

VGSoff

2

Vgs off is negative for N channel

3http://books.google.com/books?id=NmD0SD1-

1YwC&pg=PA462&lpg=PA462&dq=typical+jfet+transconductance&source=bl&ots=9DyafhCWvz&sig=JihfDvgNXH1h5a3f5rizEg4LM5g&hl=en&ei=AlHGSZKDE4iyjAei9tinCw&sa=X&oi=book_result&resnum=1&ct=r

esult#PPA451,M1


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Drain source resistance

RDS =

1

gm

From the datasheet and labweb we obtain values:

VGSoff = - 3V,

Idss =10mA and

RDS =150W

If we want the output to be at 4V and the gate at 0V then

Id = Idss 1-V

GS

VGSoff

2

=10mA 1-- 4

- 3

2

Id =1.111mA

Now

gm =1

RDS

= 6.66mS

Output impedance of voltage follower is Rds.

And the source resistor should have value:

R =

V

I =

4

1.11mA = 3600W

This is assuming that the JFET is in Active mode, meaning

Vds VGS - Vt which the case.

Common emitter amplifier

The CE amplifier is made of a single NPN transistor. Data sheet says that

= 605 for 1mA

current. The quiescent conditions should be Vo=4.5V, or half the rail difference, to allow for

large voltage swing. Ic = 1mA for optimum operation.

Choosing Rc such that Vout = 4.5V for Ic= 1mA:

RC =4.5

1mA= 4500W

Ve should be around 1V for thermal stability, and for active mode bias, the base is 0.65V above

the emitter. Choosing Re:

RE =

1

1mA=1kW

The base of the transistor needs to be 0.6V above the emitter. This can be done using a potentialdivider between the rail and ground. Rearranging the potential divider formula:

R1

R2=

VB

VCC - VB

=VE + 0.6V

VCC - VE + 0.6V( )

R1

R2=

1V + 0.6V

9V - 1V + 0.6V( )=

8

37

The actual values of the resistors can be found by making sure that their parallel resistance is

greater than the previous blocks output impedance and smaller than the base input impedance.

This way, the voltage dividers output voltage shouldnt change too much under load


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conditions. The output impedance of the JFET voltage follower is

RS //

1

gm=

RS

gmRS +1=

3.6k

3.6k 6.66mS +1=144W

The base DC input impedance of the BJT is

Rin(base)dc = b REload = 605 1k= 605kW

Making

R1 = 8k and

R2 = 37k results in a combined parallel impedance of

6.57k which is

100 times greater than previous Rout and 100 times smaller than Rin base of BJT.

Note AC input impedance for CE amplifier with grounded emitter (because of capacitor) is

Ri = RB rbe and

rbe =

b

gm

=605

40mS=15k hence

Ri =15k//6.5k= 4.5k

Output impedance for CE amplifier is

Ro = RC ro and

ro =

VA

IC

= 120

1mA=120k

Ro =120k//4.5k= 4.3kW which is quite high.

CE amplifier gain.

The ideal gain can only be obtained if there is no loading effect from previous and subsequent

stages. The gain of the amplifier is giver by

K = - gm RC //ro( ) where

gm =

IC

Vtand

ro =

VA

IC

K = - 40mS 4.5k//120k( ) = - 173

The true gain of the CE amplifier is

Av =Rin

Ri + Rin

K( )RL

Ro + RL

where

Rin is the CE input

impedance,

Ro the output impedance,

Ri the previous stages output impedance

RL is the load

impedance and K is the ideal gain. Calculating

Av =4.5k

150+ 4.5k- 173( )

605k

4.3k+ 605k

Av = - 166

which is still reasonable.

Assuming the next stage input resistance is of the order of kOhms.


11/11

Calculating the value of the DC coupling capacitor for the CE amplifier

The AC coupling capacitor is supposed to black any dc levels and unwanted frequencies from

reaching the CE amplifier. It forms a high-pass filter with the amplifiers input resistor. The

3dB point of the highpass filter is

2pf =1

RChence if we want all frequencies below 900kHz to

be filtered, we choose a value:

C=1

Rin

2pf=

1

2p 900k* 4.5k= 40pF

Calculating the bypass capacitor value.

As previously, we want a capacitor that will act as a short for frequencies above 900kHz. The

capacitor forms a highpass filter with

rtrand

rtr

=V

t

IC= 25Whence

C=1

2pf rtr=

1

2p 900k*25W= 7nF

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