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The GLAST experiment at SLAC
The ACD Electronics Module (AEM) Electronics group
Programming ICD specification
Document Version: 2.11 Document Issue: 3 Document Edition: English Document Status: Under release control Document ID: LAT-TD-00639 Document Date: September 8, 2004
Stanford Linear Accelerator Center (SLAC) 2575 Sandhill Road
Menlo Park California, 94025 USAThe ACD Electronics Module (AEM) Programming ICD specificationSeptember 8, 2004 Version/Issue: 2.11/3
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This document has been prepared using the Software Documentation Layout Templates that have been prepared by the IPT Group (Information, Process and Technology), IT Division, CERN (The European Laboratory for Particle Physics). For more information, go to http://framemaker.cern.ch/.
The ACD Electronics Module (AEM) Programming ICD specificationAbstract Version/Issue: 2.11/3
Abstract
A description, written from the viewpoint of use of the AEM (ACD Electronics Module). This includes:
• Naming conventions between ACD and AEM
• Enumeration of the AEM’s registers
• The protocol used to access the AEM’s registers and functional blocks
• A description of the event data emitted by the AEM
Hardware compatibility
This document assumes the following hardware revisions:
AEM: Version TBD
GARC: Version TBD
GAFE: Version TBD
Intended audience
This document is intended principally as a guide for the users of the ACD Electronics Module (AEM). These include:
• Developers of the sub-system electronics which interface with the AEM
• Developers of Flight-Software
• Developers of I&T (Integration and Test) based systems
All readers of this document are expected to be familiar with the concepts described in [1].
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The ACD Electronics Module (AEM) Programming ICD specificationConventions used in this document Version/Issue: 2.11/3
Conventions used in this document
Certain special typographical conventions are used in this document. They are documented here for the convenience of the reader:
• Field names are shown in bold and italics (e.g., respond or parity).
• Acronyms are shown in small caps (e.g., SLAC or TEM).
• Hardware signal or register names are shown in Courier bold (e.g., RIGHT_FIRST or LAYER_MASK_1)
References
1 “LAT Inter-module Communications - A reference manual,” Michael Huffer, LAT-TD-00606.
2 Data sheet for the “MAXIM 145 2.7V, Low-Power, 2-channel 108ksps Serial 12-Bit ADCs in 8-Pin uMAX,” http://www.maxim-ic.com.
3 “ACD-LAT Interface Control Document (ICD) – Mechanical, Thermal and Electrical,” M. Amato, R. Bielawski, G. Haller, M. Nordby, D. Shepard, K. Segal, G. Shiblie, and G. Unger, LAT-SS-00363.
Note: For additional resources, refer to the LAT Electronics, DAQ Critical Design Requirements List. On the LAT Electronics, Data Acquisition & Instrument Flight Software page (http://www-glast.slac.stanford.edu/Elec_DAQ/Elec_DAQ_home.htm), click Hardware and then click List of all documents.
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The ACD Electronics Module (AEM) Programming ICD specificationDocument Control Sheet Version/Issue: 2.11/3
Document Control Sheet
Table 1 Document Control Sheet
Document Title: The ACD Electronics Module (AEM) Programming ICD specification
Version: 2.11
Issue: 3
Edition: English
ID: LAT-TD-00639
Status: Under release control
Created: February 9, 2002
Date: September 8, 2004
Access: V:\GLAST\Electronics\Design Documents\AEM\2.11\frontmat-ter.fm
Keywords: ACD Electronics Module (AEM)
Tools DTP System: Adobe FrameMaker Version: 6.0
Layout Template:
Software Documentation Layout Templates
Version: V2.0 - 5 July 1999
Content Template:
-- Version: --
Authorship Coordinator: Michael Huffer
Written by: Michael Huffer
Table 2 Approval sheet
Name Title Signature Date
Gunther Haller LAT Chief Electronics Engineer
JJ Russell Flight Software Lead
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The ACD Electronics Module (AEM) Programming ICD specificationDocument Status Sheet Version/Issue: 2.11/3
Document Status Sheet
Table 3 Document Status Sheet
Title: The ACD Electronics Module (AEM) Programming ICD specification
ID: LAT-TD-00639
Version Issue Date Reason for change
1.0 1 3/12/2002 Initial draft
1.1 1 3/27/2002 Initial draft for public comment
1.2 1 3/29/2002 Comments from GXH
1.3 1 4/01/2002 Comments from JJ
1.4 1 4/12/2002 Miscellaneous typos as mentioned by Curt and Selim in e-mails of April 3 and April 4
2.0 1 5/29/2002 Many changes given that the AEM design is actually under way, we’ve commissioned the VAEM and we’ve seen and assimilated the ACD interface through testing of the “bud box”:
1. Given AEM constraints and event structure from ACD, the format of an event must be completely rethought. The event chapter has been rewritten to reflect my current thinking. Note: undoubtedly, as the AEM design matures, this will undergo more changes.
2. Table 10 (function block 5) numbered incorrectly. Note, this changes the register numbering.
3. Even read commands require a payload. Updated document accordingly.
4. Miscellaneous typos, mentioned by Curt corrected.
2.1 1 6/07/2002 Still had function block 5 numbered incorrectly. Also fixed mis-cellaneous typos in event chapter.
2.2 1 1/14/2003 In anticipation of G2 test-stand for ACD:1. cleaned up notation and syntax in register chapter
2. Added power management register
3. Added new functional block to support environmental monitoring.
2.3 1 2/27/2003 More changes...1. Fixed typo (SSA to SAA) as per Connie
2. Move timeout field in configuration register to its own register. This field in the configuration register is now used a hardware revision register.
3. Added new register to define node address.
2.4 1 3/03/2003 Mea culpa. When I added new registers (see previous version), I should have added them at the end, in order to increase chances for backward compatibility.
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The ACD Electronics Module (AEM) Programming ICD specificationDocument Status Sheet Version/Issue: 2.11/3
2.5 1 4/30/2003 Changed title and added NASA verbiage in order to make for conformance with both Gunther’s and NASA’s wishes for CDR. While, mucking, changed names of registers 8, 9, 10, and 11within function block 0 of the GARC to satisfy Goddard’s (very reasonable) requests.
2.6 1 5/02/2003 Forgot to add two fields in the configuration register, which follow from the fact the AEM is on the GASU. Curt also points out that I don’t know how to actually compute parity for AEM off-board registers. This changes sections, 2.5 and 2.6.
2.7 1 2/09/2004 As we actually construct the real AEM, more changes...1. Assigned FREE board and cable number to FREE board
name.
2. Each environmental quantity now includes a status bit to indicate whether the read from its corresponding ADC timed- out.
3. Added so-called “thirteenth” environmental register. This measure currents for both the FREE boards and AEM.
4. Added register to relocate memory used to buffer input TEM messages and data contributions from FREE boards.
5. Added register to (configurably) time-out read commands to off-board registers (GARCs and GAFEs).
6. Removed both on/off DAQ board fields from the configuration register as we no longer support this function.
7. Removed section on “mapping accept map to PHA values”. New GARCs no longer need this disclaimer.
8. Curt says I still don’t how to fix parity in the ACD Access Descriptor. Fixed (I hope).
9. Input masking now affects which cable contributions are in the event contribution. Added two fields (End-of-Cable and Cable number) to manage this issue.
10. response payload from off-board registers should have had a start bit (corrected).
11. Changed off-board read function code from 10 to 11.
12. Changed off-board dataless function code to 01
2.8 1 3/05/04 Updated fonts.
Table 3 Document Status Sheet
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The ACD Electronics Module (AEM) Programming ICD specificationDocument Status Sheet Version/Issue: 2.11/3
2.9 1 3/08/04 Corrected some typos, per Eric S. Two non-backward changes:1. Added more control over parity testing. This changed
the structure of the configuration register. Used this opportunity to move version field, to make the aem more in line with other modules of the gasu.
2. Hardware problem in power sequencing garcs required support by aem in order to fix. Power is now sequenced one board at a time. Two new registers to perform this function. Old power register is now read-only and returns the power state.
2.10 1 4/23/04 1. Corrected typos including adding footnote to free board status register.
2. Added Trigger statistics register.
3. Added conversion constant for ADC.
2.10 2 4/23/04 In the GAFE registers, corrected LLD_DAC and HLD_DAC, which were reversed. Changed LLD_DAC name to VETO_VERNIER in line with ACD documentation.
2.11 1 5/17/04 Corrected typos. Have begun work on documenting the GARC and GAFE registers.
2.11 2 5/18/04 Corrected version ID register per Eric Siskind. Sent document for sign-off.
2.11 3 9/08/04 Documentation of GARC and GAFE registers updated, but it is still under construction. Updated References and PDF TOC.
Table 3 Document Status Sheet
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The ACD Electronics Module (AEM) Programming ICD specificationTable of Contents Version/Issue: 2.11/3
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Hardware compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Intended audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Conventions used in this document . . . . . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Document Control Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Document Status Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.2 Common conventions for on-board registers . . . . . . . . . . . . . . 201.3 The AEM (Common Controller) . . . . . . . . . . . . . . . . . . 20
1.3.1 Configuration register . . . . . . . . . . . . . . . . . . . . 211.3.1.1 Version ID . . . . . . . . . . . . . . . . . . . . . . 23
1.3.2 Common status . . . . . . . . . . . . . . . . . . . . . . 231.3.3 FREE board status . . . . . . . . . . . . . . . . . . . . . 241.3.4 Command/Response statistics register . . . . . . . . . . . . . . 251.3.5 Trigger sequencing register . . . . . . . . . . . . . . . . . . 261.3.6 Power status . . . . . . . . . . . . . . . . . . . . . . . 26
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The ACD Electronics Module (AEM) Programming ICD specificationTable of Contents Version/Issue: 2.11/3
1.3.7 Address register . . . . . . . . . . . . . . . . . . . . . . 271.3.8 Timeout register . . . . . . . . . . . . . . . . . . . . . . 271.3.9 Memory relocation register . . . . . . . . . . . . . . . . . . 281.3.10 Response timeout register . . . . . . . . . . . . . . . . . . 281.3.11 Powering up and down FREE boards . . . . . . . . . . . . . . 291.3.12 Trigger message statistics register . . . . . . . . . . . . . . . 30
1.4 The Environmental monitor . . . . . . . . . . . . . . . . . . . . 301.5 The GLAST ACD Readout Controller (GARC) . . . . . . . . . . . . . . 33
1.5.1 GARC registers (function block 0) . . . . . . . . . . . . . . . . 331.5.1.1 Veto delay register . . . . . . . . . . . . . . . . . . . 331.5.1.2 HVBS register . . . . . . . . . . . . . . . . . . . . . 341.5.1.3 SAA register . . . . . . . . . . . . . . . . . . . . . 341.5.1.4 Hold delay register . . . . . . . . . . . . . . . . . . . 351.5.1.5 Veto pulse width register . . . . . . . . . . . . . . . . 351.5.1.6 Hitmap width register . . . . . . . . . . . . . . . . . 361.5.1.7 Hitmap deadtime register . . . . . . . . . . . . . . . . 36
1.5.2 GARC registers (function block 1) . . . . . . . . . . . . . . . . 371.5.2.1 Look at me register . . . . . . . . . . . . . . . . . . . 371.5.2.2 Hitmap delay register . . . . . . . . . . . . . . . . . . 371.5.2.3 PHA enable register (0) . . . . . . . . . . . . . . . . . 381.5.2.4 Veto enable register (0) . . . . . . . . . . . . . . . . . 381.5.2.5 PHA enable register (1) . . . . . . . . . . . . . . . . . 391.5.2.6 Veto enable register (1) . . . . . . . . . . . . . . . . . 391.5.2.7 Max PHA enable register . . . . . . . . . . . . . . . . . 40
1.5.3 GARC registers (function block 2) . . . . . . . . . . . . . . . . 401.5.3.1 Mode register . . . . . . . . . . . . . . . . . . . . . 411.5.3.2 Status register . . . . . . . . . . . . . . . . . . . . 411.5.3.3 Last command register . . . . . . . . . . . . . . . . . 421.5.3.4 Diagnostic register . . . . . . . . . . . . . . . . . . . 421.5.3.5 Command reject register . . . . . . . . . . . . . . . . . 431.5.3.6 FREE ID register . . . . . . . . . . . . . . . . . . . . 441.5.3.7 GARC version register . . . . . . . . . . . . . . . . . . 44
1.5.4 GARC registers (function block 3, 4 and 5) . . . . . . . . . . . . . 441.5.4.1 PHA threshold registers . . . . . . . . . . . . . . . . . 451.5.4.2 ADC Tacq register . . . . . . . . . . . . . . . . . . . 46
1.6 The GLAST ACD Front-End Controller (GAFE) . . . . . . . . . . . . . 461.6.0.1 Configuration register . . . . . . . . . . . . . . . . . . 471.6.0.2 Veto DAC register . . . . . . . . . . . . . . . . . . . 481.6.0.3 Veto Vernier register . . . . . . . . . . . . . . . . . . 481.6.0.4 HLD threshold register . . . . . . . . . . . . . . . . . 481.6.0.5 Bias DAC register . . . . . . . . . . . . . . . . . . . 491.6.0.6 TCI DAC Register . . . . . . . . . . . . . . . . . . . 49
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The ACD Electronics Module (AEM) Programming ICD specificationTable of Contents Version/Issue: 2.11/3
1.6.0.7 Version address register . . . . . . . . . . . . . . . . . 501.6.0.8 Write counter register . . . . . . . . . . . . . . . . . . 501.6.0.9 Reject counter register . . . . . . . . . . . . . . . . . . 501.6.0.10 Loop counter register . . . . . . . . . . . . . . . . . 501.6.0.11 Chip address register . . . . . . . . . . . . . . . . . 51
Chapter 2 Commanding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 532.1.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . 532.1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . 53
2.2 The AEM’s access descriptors . . . . . . . . . . . . . . . . . . . 552.2.1 ACD access descriptor . . . . . . . . . . . . . . . . . . . . 552.2.2 Local Access Descriptor . . . . . . . . . . . . . . . . . . . 57
2.3 Accessing the Common Controller (or AEM) . . . . . . . . . . . . . . 572.3.0.1 Dataless commands . . . . . . . . . . . . . . . . . . 572.3.0.2 Load commands . . . . . . . . . . . . . . . . . . . . 582.3.0.3 Read commands . . . . . . . . . . . . . . . . . . . . 58
2.4 Accessing the environmental monitor . . . . . . . . . . . . . . . . 592.4.0.1 Load commands . . . . . . . . . . . . . . . . . . . . 592.4.0.2 Read commands . . . . . . . . . . . . . . . . . . . . 60
2.5 The GLAST ACD Readout Controller (GARC) . . . . . . . . . . . . . 602.5.1 Dataless commands . . . . . . . . . . . . . . . . . . . . . 612.5.2 Load commands . . . . . . . . . . . . . . . . . . . . . . 622.5.3 Read commands . . . . . . . . . . . . . . . . . . . . . . 63
2.6 The GLAST ACD Front-End Controller (GAFE) . . . . . . . . . . . . . 632.6.1 Dataless commands . . . . . . . . . . . . . . . . . . . . . 642.6.2 Load commands . . . . . . . . . . . . . . . . . . . . . . 642.6.3 Read commands . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 673.1.1 Background . . . . . . . . . . . . . . . . . . . . . . . 67
3.2 The event contribution . . . . . . . . . . . . . . . . . . . . . . 683.2.1 The cable header . . . . . . . . . . . . . . . . . . . . . . 703.2.2 The PHA vector . . . . . . . . . . . . . . . . . . . . . . 723.2.3 Relationship between input masking and number of components . . . . 72
3.3 The error contribution . . . . . . . . . . . . . . . . . . . . . . 733.4 The diagnostic contribution . . . . . . . . . . . . . . . . . . . . 73
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The ACD Electronics Module (AEM) Programming ICD specificationTable of Contents Version/Issue: 2.11/3
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The ACD Electronics Module (AEM) Programming ICD specificationList of Tables Version/Issue: 2.11/3
List of Tables
Table 1 p. 5 Document Control Sheet
Table 2 p. 5 Approval sheet
Table 3 p. 6 Document Status Sheet
Table 4 p. 20 The AEM’s blocks and registers
Table 5 p. 21 The AEM registers
Table 6 p. 23 Usage of the type field of the revision register
Table 7 p. 29 Relationship between FREE board number, offset and name
Table 8 p. 31 The environmental monitor registers
Table 9 p. 33 The GARC registers (function block 0)
Table 10 p. 37 The GARC registers (function block 1)
Table 11 p. 40 The GARC registers (function block 2)
Table 12 p. 44 The GARC registers (function block 3)
Table 13 p. 45 The GARC registers (function block 4)
Table 14 p. 45 The GARC registers (function block 5)
Table 15 p. 46 The GAFE registers
Table 16 p. 57 The Common Controller’s dataless commands
Table 17 p. 61 The GARC dataless commands
Table 18 p. 68 Relationship between cable number and FREE board
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The ACD Electronics Module (AEM) Programming ICD specificationList of Tables Version/Issue: 2.11/3
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The ACD Electronics Module (AEM) Programming ICD specificationList of Figures Version/Issue: 2.11/3
List of Figures
Figure 1 p. 19 Hierarchy of target types
Figure 2 p. 21 AEM configuration register
Figure 3 p. 23 Structure of revision register or field
Figure 4 p. 24 AEM status register
Figure 5 p. 24 FREE board status structure
Figure 6 p. 25 FREE board status register
Figure 7 p. 25 AEM Command/Response statistics register
Figure 8 p. 26 AEM trigger sequencing register
Figure 9 p. 27 AEM power status
Figure 10 p. 27 Address register
Figure 11 p. 28 Timeout register
Figure 12 p. 28 Memory relocation register
Figure 13 p. 28 Response Timeout register
Figure 14 p. 29 Power-up FREE board register
Figure 15 p. 30 Power-down FREE board register
Figure 16 p. 30 Trigger message statistics register
Figure 17 p. 31 FREE board monitoring register
Figure 18 p. 32 DAQ board monitoring register
Figure 19 p. 34 Veto delay register
Figure 20 p. 34 HVBS register
Figure 21 p. 34 SAA register
Figure 22 p. 35 Hold delay register
Figure 23 p. 35 Veto pulse width register
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The ACD Electronics Module (AEM) Programming ICD specificationList of Figures Version/Issue: 2.11/3
Figure 24 p. 36 Hitmap width register
Figure 25 p. 36 Hitmap deadtime register
Figure 26 p. 37 Look at me register
Figure 27 p. 38 Hitmap delay register
Figure 28 p. 38 PHA enable register (0)
Figure 29 p. 39 Veto enable register (0)
Figure 30 p. 39 PHA enable register (1)
Figure 31 p. 40 Veto enable register (1)
Figure 32 p. 40 Max PHA enable register
Figure 33 p. 41 Mode register
Figure 34 p. 42 Status register
Figure 35 p. 42 Last command register
Figure 36 p. 43 Diagnostic register
Figure 37 p. 43 Command reject register
Figure 38 p. 44 FREE ID register
Figure 39 p. 44 GARC version register
Figure 40 p. 46 PHA threshold register
Figure 41 p. 46 ADC Tacq register
Figure 42 p. 47 Configuration register
Figure 43 p. 48 Veto DAC register
Figure 44 p. 48 Veto Vernier register
Figure 45 p. 49 HLD threshold register
Figure 46 p. 49 Bias DAC register
Figure 47 p. 49 TCI DAC register
Figure 48 p. 50 Version address register
Figure 49 p. 50 Write counter register
Figure 50 p. 50 Reject counter register
Figure 51 p. 51 Loop counter register
Figure 52 p. 51 Chip address register
Figure 53 p. 54 Hierarchy of target types
Figure 54 p. 54 Command string prefix for accessing the Common Controller of the AEM
Figure 55 p. 54 Command string prefix for accessing the Environmental Monitor of the AEM
Figure 56 p. 54 Command string prefix for accessing off-board functional blocks and regis-ters of the AEM
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The ACD Electronics Module (AEM) Programming ICD specificationList of Figures Version/Issue: 2.11/3
Figure 57 p. 55 Access descriptor for external ACD commands
Figure 58 p. 57 Access descriptor for local commands
Figure 59 p. 57 Access descriptor for AEM dataless functions
Figure 60 p. 58 Access descriptor for AEM register load commands
Figure 61 p. 58 Payload for AEM register load commands
Figure 62 p. 58 Access descriptor for AEM register read commands
Figure 63 p. 59 Response to AEM register read commands
Figure 64 p. 59 Access descriptor for environmental monitor register load commands
Figure 65 p. 59 Payload for environmental monitor register load commands
Figure 66 p. 60 Access descriptor for environmental monitor register read commands
Figure 67 p. 60 Response to environmental monitor register read commands
Figure 68 p. 61 Access descriptor for GARC dataless commands
Figure 69 p. 62 Payload for GARC dataless and read commands
Figure 70 p. 62 Access descriptor for GARC register load commands
Figure 71 p. 62 Payload for GARC register load commands
Figure 72 p. 63 Access descriptor for GARC register read commands
Figure 73 p. 63 ACD response to GARC register read commands
Figure 74 p. 64 Access descriptor for GAFE register load commands
Figure 75 p. 64 Payload for GAFE register load commands
Figure 76 p. 65 Access descriptor for GAFE register read commands
Figure 77 p. 65 Response to GAFE register read commands
Figure 78 p. 69 ACD tile mapping
Figure 79 p. 70 Overall structure of the AEM’s natural event data
Figure 80 p. 71 Structure of cable header
Figure 81 p. 72 Structure of a PHA value
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The ACD Electronics Module (AEM) Programming ICD specificationList of Figures Version/Issue: 2.11/3
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 1 Registers Version/Issue: 2.11/3
Chapter 1
Registers
1.1 Overview
It is convenient to consider the AEM, its functional blocks types and their registers as organized hierarchically as illustrated in Figure 1. Each type, of course, may have more then one instance. For example, the AEM has twelve GLAST ACD Readout Controllers (GARCs). The number of instances for each type is set out in Table 4.
This hierarchy expresses itself in at least two usages:
Commanding: Commanding is used to access the registers or functional block. For example, to either read or write a register, one must specify a hierarchical path to the register. Thus, to access a register in an ACD Front-End ASIC, one must go through an AEM, GARC and GAFE. The protocol of commanding is described in Chapter 2.
Resets: Resets are propagated downwards from the point they are issued. For example, if the AEM is reset, it will also cause a reset of all its 18 FREE boards. A reset of a FREE board (through its GARC) will cause a reset of its Front-Ends and so forth.
Figure 1 Hierarchy of target types
GAFE
GARC
registers
registers
registers
AEM
env
registers
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 1 Registers Version/Issue: 2.11/3
1.2 Common conventions for on-board registers
In describing the registers on-board the AEM, the following conventions are used or assumed when describing a register’s fields:
Not defined: Undefined fields are identified as Must Be Zero (MBZ) and are illustrated grayed out. An MBZ field will:
— Read back as zero
— Ignore writes
— Reset to zero
Read/Write: A Reset will set a read/write field to zero.
Read-only: Read-only fields are illustrated lightly grayed-out with their value. Any read-only field will:
— Ignore writes
— Reset to zero, unless otherwise documented
Any field used as a boolean has a width of one bit. A value of one (1) is used to indicate its set or true sense, and a value of zero (0) to indicate its clear or false sense. Field numbering for registers is such that offset zero (0) corresponds to a register’s Least Significant Bit (LSB) and the largest offset corresponds to a register’s Most Significant Bit (MSB).
1.3 The AEM (Common Controller)
This section incorporates all the registers which are in common on the AEM. As all these registers are contained physically on a single FPGA called the Common Controller, AEM registers may also be referenced as Common Controller registers. All registers of this block are thirty-two (32) bits in length.
Table 4 The AEM’s blocks and registers
Block type # of blocks # of registers Description
AEM 1 12 AEM Common Controller FPGA
Environmental monitor 1 13 FREE board environmental monitoring
GARC 12 ACD Readout Controller ASIC
GAFE 18 x 12 = 216 ACD Front-End ASIC
Total 229 2917
43 12× 516=
11 216× 2376=
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 1 Registers Version/Issue: 2.11/3
1.3.1 Configuration register
Table 5 The AEM registers
Name Number Access Description
CONFIGURATION 0 R/W Configuration and setup
COMMON_STATUS 1 R/W1
1. On write, the value is ignored and the register is set to zero (0).
CSR latched values (for AEM)
FREEBOARD_STATUS 2 R/W1 CSR latched FREE board status values
COMMAND_RESPONSE 3 R/W Command/response statistics
TRGSEQ 4 R/W Trigger sequencing
POWER_STATUS 5 R/O Returns the power state for all FREE boards
ADDRESS 6 R/W Node address
TIMEOUT 7 R/W Timeout value for FREE board event data
RELOCATION 8 R/W Relocation definition (TBD)
RESPONSE_TIMEOUT 9 R/W Timeout value for GARC/GAFE
POWER_UP 10 R/W Turn-on power for one FREE board
POWER_DOWN 11 R/W Turn-off power for one FREE board
TRIGGER_STATISTICS 12 R/W1 Trigger message statistics
Total 13
Figure 2 AEM configuration register
use even parity (event cell)
016
use even parity (event header)
31 282930
use even parity (response header)
27
FREE board masking
MBZ
12
version
24252632
use even parity (response cell)use even prefix parity use even command parityuse even data parity
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FREE board masking: Determines whether event data emitted from the AEM’s FREE boards is either masked or accepted. Each bit offset corresponds to the masking for a particular FREE board. The correspondence between bit offset and FREE board name is enumerated in Table 7. If a bit is clear, any data from the specified FREE is accepted. If the bit is set, data is masked.
version: Specifies the hardware revision level of the AEM. The structure of this field is defined in Figure 3. Note: This field is read-only.
use even parity (event header): Determines whether odd or even parity is generated for the header of an event packet. If this field is clear, odd parity will be generated. If this field is set, even parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of an event.
use even parity (event cell): Determines whether odd or even parity is generated for the cells of an event packet. If this field is clear, odd parity will be generated. If this field is set, even parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of an event.
use even parity (response header): Determines whether odd or even parity is generated for the header of the command response packet. If this field is clear, odd parity will be generated. If this field is set, even parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of a response.
use even parity (response cell): Determines whether odd or even parity is generated for the cell of a command response packet. If this field is clear, odd parity will be generated. If this field is set, even parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of a response.
use even prefix parity: Determines whether odd or even parity is generated for the prefix of the internally issued commands1 sent to the ACD‘s FREE boards. The commands have three parity fields: prefix, command and data. This option affects the parity of the prefix field. If this field is clear, odd prefix parity will be generated. If this field is set, even prefix parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of these commands, which in this case would be the ACD’s Front-End electronics.
use even command parity: Determines whether odd or even parity is generated for the internally issued commands1 sent to the ACD‘s FREE boards. The commands have three parity fields: prefix, command and data. This option affects the parity of the command field. If this field is clear, odd command parity will be generated. If this field is set, even command parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of these commands, which in this case would be the ACD’s Front-End electronics.
1. Internal commands are TACK and CALSTROBE.
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use even data parity Determines whether odd or even parity is generated for the internally issued commands1 sent to the ACD‘s FREE boards. The commands have three parity fields: prefix, command and data. This option affects the parity of the data field. If this field is clear, odd data parity will be generated. If this field is set, even data parity will be generated. The value of this field lies only in its use as a debugging and commissioning tool to purposely stimulate parity errors at the destination of these commands, which in this case would be the ACD’s Front-End electronics.
1.3.1.1 Version ID
The fields of this register are somewhat self-explanatory with the exception of the type field. This field is intended to differentiate both the context in which the module was implemented and how it was intended to be used. The values for this field are defined in Table 6.
1.3.2 Common status
In general, this register reflects the latched values of the signals the AEM uses in building events. If a signal is asserted, it is latched and the corresponding field is set. Note: This register
1. Internal commands are TACK and CALSTROBE.
Figure 3 Structure of revision register or field
Table 6 Usage of the type field of the revision register
Value1
1. In binary
Description
00 Software emulation
01 Engineering model
10 Qualification model
11 Flight model
VHDL revisionboard layout revision
08 6
type
3
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may be either read or written. However, the value specified on write is ignored and the register is always cleared (all fields set to zero).
event statistics: The event transmission statistics of the TEM. For example, this field specifies the number of events transmitted by the TEM. As events are sent as LATp packets, the structure of this field corresponds to the transmitter statistics register described in [1].
command prefix parity error: Specifies whether the controller has ever detected a parity error when attempting to decode and process a command’s prefix. If the field is set, a parity error has been detected in the prefix.
command parity error: Specifies whether the AEM has ever detected a parity error when attempting to decode and process a command directed to itself. Parity is evaluated in at least one and possibly two places: the local access descriptor and, in the case of a load command, the parity associated with the payload. This field is set if either of these two evaluations fails.
trigger message parity error: Specifies whether the AEM has ever detected a parity error in an incoming trigger message. If the bit is set, a parity error has been detected.
1.3.3 FREE board status
This register reflects potential errors from each of the 12 FREE boards. Anytime the AEM encounters an error, it is latched in this register. Each board can contribute up to two errors. These error signals are captured in the structure illustrated in Figure 5. If a signal is asserted, it is latched and the corresponding field is set. Note: This register may be either read or written. However, the value specified on write is ignored and the register is always cleared (all fields set to zero).
event data parity error: Specifies whether the AEM has ever detected a parity error when attempting to process its input event data. This field is set if a parity error occurs.
Figure 4 AEM status register
029303132
event statistics
16
MBZ
trigger message parity errorcommand parity errorcommand prefix parity error
Figure 5 FREE board status structure
start-bit missing error
012
event data parity
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start-bit missing: Specifies whether the AEM did not detect a start-bit before the timeout period. If the bit is set, a timeout on the start-bit has been detected.
This register contains the latched error status for the 12 FREE boards. The register is organized as a 2 x 12 bit array, where a particular offset of the array corresponds to the errors for the corresponding FREE board as illustrated in Figure 6.
1.3.4 Command/Response statistics register
Note: This register may be either read or written. However, the value specified on write is ignored, and the register is always cleared (all fields set to zero).
command statistics: The packet statistics for the incoming command wire. See [1] for a description of the structure of this field.
response statistics: The packet statistics for the outgoing response wire. See [1] for a description of the structure of this field.
Figure 6 FREE board status register
0
MBZ
2468101214161832 202224
1LA1RB2LA2LB2RA2RB3LA3RB4LA4LB4RA4RB
Figure 7 AEM Command/Response statistics register
32 016
response statisticscommand statistics
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1.3.5 Trigger sequencing register
This register determines the respective timing between the arrival of a trigger message at the AEM and the subsequent command (or commands) it generates to its FREE boards. The two fields of this register are illustrated in Figure 8.
Note: The AEM adds a 7-clock delay between the arrival of the trigger message at the AEM and the issuance of any command.
TACK delay: If either the CALSTROBE field of the trigger message is false (clear), or the TACK field of a trigger message is true (set), this field specifies the transmission delay (in units of sysclk) of the TACK command from the AEM to its FREE boards. The delay’s starting point depends on the state of the CALSTROBE field of the trigger message. If the CALSTROBE field is true (set), the delay is calculated with respect to the start of the transmission of the CALSTROBE. If the CALSTROBE field is false (clear), the delay is calculated with respect to the arrival time of the trigger message at the AEM. As this is an eight-bit field, the maximum delay is 12.750 microseconds.This field is ignored if the CALSTROBE field of the trigger message is true (set) and the TACK field is false (clear).
CALSTROBE delay: If the CALSTROBE field of a trigger message is true (set), this field specifies the transmission delay (in units of sysclk) of the CALSTROBE command from the AEM to its FREE boards. The delay is calculated with respect to the arrival time of the trigger message at the AEM. As this is a four-bit field, the maximum delay is 800 nanoseconds. This field is ignored if the CALSTROBE field of the trigger message is false (clear). Typically, if a subsystem is operating in isolation, the value of this field is irrelevant. However, if more then one subsystem is operating simultaneously, this field may be used to align the relative starting point of CALSTROBEs from subsystem to subsystem and thus may be used to understand correlated effects between subsystems.
1.3.6 Power status
This register is read-only. It reflects the status of the power supplied by the AEM to its FREE boards. The structure of this register is illustrated in Figure 9. Each field corresponds to the
Figure 8 AEM trigger sequencing register
TACK delayCALSTROBE delay
016 820
MBZ
32
MBZ
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state of one FREE card. If a field is set, the corresponding power supply is on; if the field is clear, the supply is off.
Note: On “power-on reset” of the AEM, this register will have a value of zero. In addition, an AEM reset will not affect the state of this register.
1.3.7 Address register
This register is used to specify the AEM’s node address on the Command/Response fabric. (See [1].) In addition, this value is also used by the AEM to set the source address in the LATp header of all event packets sent by it in response to a trigger. Note that all nodes on any one fabric must have a unique value. This register allows for definition of only the address’s lower five bits. As the AEM is a slave on both Command/Response and Event Fabrics, the high order bit is an implied zero (0).
1.3.8 Timeout register
This register specifies the time (in units of sysclk), while waiting for event data from a FREE board before declaring a timeout error. The structure of this register is illustrated in Figure 11:
Figure 9 AEM power status
0
MBZ
24681012 13532 7911
1LA1RB2LA2LB2RA2RB3LA3RB4LA4LB4RA4RB
Figure 10 Address register
05
address
32
MBZ
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1.3.9 Memory relocation register
The structure and function of this register remains to be described. However, the default value is perfectly valid for operation of the AEM. And in fact, within a test-stand environment, any value written to this register will work.
1.3.10 Response timeout register
This register specifies how long the AEM should wait for data from a command that specified a response from its off-board registers. The amount of time is specified in units of sysclk (nominally 50 nanoseconds). There are two different fields: one times-out the registers on a GARC and the other times-out the registers on a GAFE. The defaults should be perfectly adequate for the current generation of FREE boards. These values are:
a. For the GARC, 128 (decimal) clocks
b. For the GAFE, 384 (decimal) clocks
The structure of this register is illustrated in Figure 13:
Figure 11 Timeout register
01632
event timeout
MBZ
Figure 12 Memory relocation register
01632
xxx
MBZ
Figure 13 Response Timeout register
01632
GARC timeout
MBZ MBZ
826
GAFE timeout
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1.3.11 Powering up and down FREE boards
Two registers are used to manage the power for the twelve FREE boards managed by the AEM. Power may be turned on or off only one board at a time. One register is used to turn on the power (Figure 14), another to turn off the power (Figure 15). In order to toggle power, one of the two registers is written with a number corresponding to the FREE board whose power is to be turned on or off. FREE board numbers vary from zero (0) to eleven (11). If the value written is outside this range, the command will be ignored. The correspondence between FREE board number and name is enumerated in Table 7. Reading either of the two registers will return the FREE board number last written. The power state of all the FREE boards is described in Section 1.3.6.
Table 7 Relationship between FREE board number, offset and name
Number or offset FREE board
0 1LA
1 1RB
2 2LA
3 2LB
4 2RA
5 2RB
6 3LA
7 3RB
8 4LA
9 4LB
10 4RA
11 4RB
Figure 14 Power-up FREE board register
0
MBZ
432
FREE board
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1.3.12 Trigger message statistics register
This register contains the counts of TAM messages received.
Note: This register may be either read or written. However, on write the value specified is ignored and the register is simply cleared (all fields set to zero).
messages received: The number of TAM messages received. The counter has a 14-bit range. It is saturating; that is, when the counter overflows, it no longer increments until re-zeroed.
trigger message fault: If a TAM message is received while the AEM is busy, this field is set.
1.4 The Environmental monitor
The AEM monitors various analog quantities associated with its FREE boards. These quantities are digitized and saved in I/O registers contained in the environmental functional block of the AEM. All registers of this block are sixty-four bits wide. The structure of each of these registers is identical and is represented in Figure 17. Each register represents the analog quantities monitored for each FREE board. In reality each register is “fronting” for four individual ADCs. Each of the four ADCs are identical (a commercial part, the MAXIM 145). (See [2].) Four 13-bit fields of this register reflect the state of a conversion for a particular ADC. For the ADC, zero counts corresponds to zero volts and full scale corresponds to 2.5 volts. The first 12 bits contain the converted values of the ADC. The last bit field contains the conversion status. If the field is set, the read of the ADC timed out. If the field is cleared, the conversion was successful. The correspondence between ADC and FREE board is enumerated in Table 8. To begin conversion, the user writes the register. (The value written is ignored.) This will force the not ready field to be set. At a fixed time later, conversion is complete and the not ready field will
Figure 15 Power-down FREE board register
0
MBZ
432
FREE board
Figure 16 Trigger message statistics register
032 14 13
TAMs received message fault
MBZ
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be cleared and the four ADC value fields will have the results of the conversion. If the register is written while a conversion is in progress, the AEM will ignore the write.
Usage of the last environmental monitor is identical to the monitors for the FREE boards. However, the quantities monitored are somewhat different:
Table 8 The environmental monitor registers
Name Number Access Description
ENV_FREE_1LA 0 R/W Environmental quantities for 1LA
ENV_FREE_1RB 1 R/W Environmental quantities for 1RB
ENV_FREE_2LA 2 R/W Environmental quantities for 2LA
ENV_FREE_2LB 3 R/W Environmental quantities for 2LB
ENV_FREE_2RA 4 R/W Environmental quantities for 2RA
ENV_FREE_2RB 5 R/W Environmental quantities for 2RB
ENV_FREE_3LA 6 R/W Environmental quantities for 3LA
ENV_FREE_3RB 7 R/W Environmental quantities for 3RB
ENV_FREE_4LA 8 R/W Environmental quantities for 4LA
ENV_FREE_4LB 9 R/W Environmental quantities for 4LB
ENV_FREE_4RA 10 R/W Environmental quantities for 4RA
ENV_FREE_4RB 11 R/W Environmental quantities for 4RB
ENV_DAQ 12 R/W Environmental quantities for the DAQ board
Total 13
Figure 17 FREE board monitoring register
VDD
64 016
Not ready
122863
Temperature
32444860
MBZ
HV1
HV2
13294561
MBZMBZMBZ
timeout
timeout
timeout
timeout
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a. The sum of the digital (3.3) currents over all FREE boards.
b. The temperature of the DAQ board.
c. The sum of the high voltage (28V) currents measured over all FREE boards.
d. The digital (3.3) voltage of the DAQ board.
The structure of the register for these quantities is show in Figure 18:
Figure 18 DAQ board monitoring register
FREEI
64 016
Not ready
122863
DAQ
32444860
MBZ
HVI
13294561
MBZMBZMBZ
timeout
timeout
timeout
timeout
DAQ boardV
temperature
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1.5 The GLAST ACD Readout Controller (GARC)
NOTE: This section, which discusses the GARC registers, is under construction.
NOTE: This section reflects ELX’s understanding of how the ACD works. For more information, consult the appropriate ACD documentation.
1.5.1 GARC registers (function block 0)
1.5.1.1 Veto delay register
This register specifies the delay, in units of sysclk,1 between the discriminator signal and the veto signal. This is a 5-bit register. The delay is equal to , when n is the value written into the register.
For example, at the nominal value of sysclk, a value of zero in the register results in a delay of A value of 31 (the maximum) results in a delay of
Table 9 The GARC registers (function block 0)
Name Number Access Reg # Description
VETO_DELAY 2 R/W 2 Delay from DISC in to NVETO out
HVBS 8 R/W 8 Requested High Voltage (HV) for normal operation
SAA 9 R/W 9 Requested High Voltage (HV) for SAA operation
USE_HV_NORMAL 10 read only1 10 Current High Voltage (HV) for normal operation
USE_HV_SAA 11 read only1 11 Current High Voltage (HV) for SAA operation
HOLD_DELAY 12 R/W 12 Delay from trigger to hold
VETO_WIDTH 13 R/W 13 Pulse width of NVETO
HITMAP_WIDTH 14 R/W 14 Minimum pulse width of hitmap signals
HITMAP_DEADTIME 15 R/W 15 Time added to hitmap signals
Total 9
1. See Table 17 on page 61.
1. One unit of sysclk is nominally 50 ns.
3 n+( ) sysclk×
3 0+( ) 50× ns 150 ns.=3 31+( ) 50 ns× 1700 ns.=
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Also, add 0 to 50 ns because of the asynchronous nature of the discriminator input signal, and add up to 20 ns for propagation delays.
On reset, the veto delay is 400 ns (a value of 0x5).
1.5.1.2 HVBS register
This register sets high voltage during normal operations. This is a 12-bit register, and its maximum value corresponds to about 1500 V. On reset, the value is 0 (zero).
1.5.1.3 SAA register
This register sets high voltage during SAA operations. This is a 12-bit register, and its maximum value corresponds to about 1500 V. On reset, the value is 0 (zero).
Figure 19 Veto delay register
05
delay
16MBZ
Figure 20 HVBS register
0
HV
16 12
MBZ
Figure 21 SAA register
0
HV
16 12
MBZ
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1.5.1.4 Hold delay register
This register specifies the delay, in units of sysclk,1 between the leading edge of the trigger signal and the hold signal. This is a 7-bit register. The delay is equal to , when n is the value written into the register.
For example, at the nominal value of sysclk, a value of zero in the register results in a delay of A value of 127 in the register (the maximum) results in a delay of
On reset, the hold delay is 7000 ns (a value of 0x1c).
1.5.1.5 Veto pulse width register
This register specifies the width, in units of sysclk,1 of the veto pulse. This is a 3-bit register. The width is equal to , when n is the value written into the register.
For example, at the nominal value of sysclk, a value of zero in the register results in a width of A value of 7 in the register (the maximum) results in a delay of
On reset, the veto pulse width is 150 ns (a value of 0x2).
1. One unit of sysclk is nominally 50 ns.
Figure 22 Hold delay register
5 n+( ) sysclk×
5 0+( ) 50 ns× 250 ns.=5 127+( ) 50 ns× 6600 ns.=
0
delay
16MBZ
7
Figure 23 Veto pulse width register
1 n+( ) sysclk×
1 0+( ) 50 ns× 50 ns.=1 7+( ) 50 ns× 400 ns.=
0
veto pulse width
16 3
MBZ
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1.5.1.6 Hitmap width register
This register specifies the width, in units of sysclk,1 of the hitmap signal. This is a 4-bit register. The width is equal to , when n is the value written into the register.
For example, at the nominal value of sysclk, a value of zero in the register results in a width of . A value of 15 in the register (the maximum) results in a width of
This register is used internally by the GARC. On reset, the hitmap signal width is 500 ns (a value of 0x7).
1.5.1.7 Hitmap deadtime register
This register specifies the time, in units of sysclk,1 added to the hitmap signal. This is a 3-bit register. At the nominal value of sysclk, the added time ranges from 0 ns to
On reset, the added time is 150 ns (a value of 0x3).
Figure 24 Hitmap width register
3 n+( ) sysclk×
3 0+( ) 50 ns× 150 ns.=3 15+( ) 50 ns× 900 ns.=
0
hitmap signal width
16 4
MBZ
1. One unit of sysclk is nominally 50 ns.
Figure 25 Hitmap deadtime register
7( ) 50 ns× 350 ns.=
0
hitmap deadtime
16 3
MBZ
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1.5.2 GARC registers (function block 1)
1.5.2.1 Look at me register
The current interface, A or B, is enabled when 0xeb90 is written to this register. Interface A is enabled by default.
1.5.2.2 Hitmap delay register
This register specifies the delay, in units of sysclk,1 between the discriminator signal and the hitmap signal. The delay is equal to , when n is the value written into the register.
For example, at the nominal value of sysclk, a value of zero in the register results in a delay of A value of 31 in the register (the maximum) results in a delay of
Also, add 0 to 50 ns because of the asynchronous nature of the discriminator input signal and add up to 20 ns for propagation delays.
Table 10 The GARC registers (function block 1)
Name Number Access Reg # Description
LOOK_AT_ME 20 write only 4 Enable current interface, A or B only
HITMAP_DELAY 24 R/W 8 Delay from DISC in to HITMAP signals
PHA_EN_0 25 R/W 9 PHA readout enables for channels 0-15
VETO_EN_0 26 R/W 10 Veto enables for channels 0 -15
PHA_EN_1 28 R/W 12 PHA readout enables for channels 16 -17 (in LSB)
VETO_EN_1 29 R/W 13 Veto enables for channels 16 -17 (in LSB)
MAX_PHA 31 R/W 15 Maximum allowable number of PHA values
Total 7
Figure 26 Look at me register
0
interface (# of bits?????)
16
17 n+( ) sysclk×
17 0+( ) 50 ns× 850 ns.=17 31+( ) 50 ns× 2400 ns.=
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On reset, the delay is 1200 ns (a value of 0x10).
1.5.2.3 PHA enable register (0)
This register enables PHA (Pulse Height Analysis) readout for channels from 0 (LSB) to 15 when the GARC is used in zero suppression mode. This is a 16-bit register. If the bit relevant to the channel is set, the PHA readout for channel is enabled. If the bit relevant to the channel is clear, the PHA readout for channel is disabled. On reset, all the channels are enabled.
1.5.2.4 Veto enable register (0)
This register enables the VETO signal for channels from 0 (LSB) to 15. This is a 16-bit register. If the bit relevant to the channel is set, the VETO signal for channel is enabled. If the bit relevant to the channel is clear, the VETO signal for channel is disabled. On reset, all the channels are enabled.
Figure 27 Hitmap delay register
0
delay (# of bits?????)
16
Figure 28 PHA enable register (0)
0616 10 715 14 13 12 11 9 8 5 4 3 2 1
channel0channel1channel2channel3channel4channel5channel6channel7channel8channel9channel10channel11channel12channel13channel14channel15
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1.5.2.5 PHA enable register (1)
This register enables PHA readout for channels from 16 (LSB) to 17 when the GARC is used in zero suppression mode. This is a 2-bit register. If the bit relevant to the channel is set, the PHA readout for channel is enabled. If the bit relevant to the channel is clear, the PHA readout for channel is disabled. On reset, all the channels are enabled.
1.5.2.6 Veto enable register (1)
This register enables the VETO signal for channels from 16 (LSB) to 17. This is a 2-bit register. If the bit relevant to the channel is set, the VETO signal for channel is enabled. If the bit relevant to the channel is clear, the VETO signal for channel is disabled. On reset, all the channels are enabled.
Figure 29 Veto enable register (0)
0616 10 715 14 13 12 11 9 8 5 4 3 2 1
channel0channel1channel2channel3channel4channel5channel6channel7channel8channel9channel10channel11channel12channel13channel14channel15
Figure 30 PHA enable register (1)
02 1
channel16channel17
MBZ
16
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1.5.2.7 Max PHA enable register
This register selects the maximum number of PHA values, from 0 to 18, that the GARC sends when used in zero suppression mode. This is a 5-bit register. On reset, the value is 0x4.
1.5.3 GARC registers (function block 2)
Figure 31 Veto enable register (1)
02 1
channel16channel17
MBZ
16
Figure 32 Max PHA enable register
05
max PHA values
16MBZ
Table 11 The GARC registers (function block 2)
Name Number Access Reg # Description
MODE 40 R/W 8 Various bit fields for mode settings
STATUS 41 read only 9 Status
LAST_CMD 42 read only 10 Command or data from last command error
DIAGNOSTIC 43 read only 11 Parity and command errors, command counters
CMD_REJECT 44 read only 12 Number of commands rejected
FREE_ID 45 read only 13 FREE board ID
GARC_VERSION 46 read only 14 GARC version number
Total 7
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1.5.3.1 Mode register
This register contains various bit fields which select mode settings. This is a 12-bit register. On reset, its value is 0x300. Its structure is shown in Figure 33:
use even parity on return data: Selects parity for data sent from the GARC to the AEM. If this field is clear, odd data parity will be generated. If this field is set, even data parity will be generated. On reset, this field is clear.
enable HVBS: Enables high voltage for the given interface. If all the 3 bits are clear, high voltage is disabled. If all the 3 bits of this field are set, high voltage is enabled. On reset, this field is clear.
use even parity on GAFE command: Selects parity for commands sent from the GARC to the GAFE. If this field is clear, odd command parity will be generated. If this field is set, even command parity will be generated. On reset, this field is clear. Note: The GAFE currently ignores parity bit.
enable AEM veto outputs: Enables veto output signals for the given interface. If this field is set, AEM veto outputs are enabled. If this field is clear, AEM veto outputs are disabled. On reset, this field is set.
enable test pin: Enables the output of the PHA signal on the test pin. If this field is clear, the PHA signal is disabled on the test pin. If this field is set, the PHA signal is enabled. On reset, this field is clear.
use positive edge in return data shift: Selects negative or positive edge of data sent from the GARC to the AEM. If this field is clear, the negative edge is selected. If this field is set, the positive edge is selected. On reset, this field is clear.
1.5.3.2 Status register
This register contains various bit fields which describe mode settings. This is a 6-bit register. On reset, its value is 0x18. Its structure is shown in Figure 34:
Figure 33 Mode register
0481012 17911
use even parity on return dataenable HVBS 1enable HVBS 2 use even parity on GAFE command enable AEM A veto outputs enable AEM B veto outputsenable test pinuse positive edge in return data shift
16MBZ
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side B enabled: Indicates which interface is enabled: A or B. If this field is clear, B is enabled. If this field is set, A is enabled. On reset, this field is clear.
HV enabled: Indicates if high voltage is enabled on the given interface. If this field is clear, high voltage is disabled. If this field is set, high voltage is enabled. On reset, this field is clear.
AEM veto enabled: Indicates if veto outputs are enabled on the given interface. If this field is set, veto is enabled. If this field is clear, veto is disabled. On reset, this field is set.
last TACK zero suppression: Indicates if last TACK requested zero suppression. If this field is clear, zero suppression was off. If this field is set, zero suppression was on. On reset this field is clear.
1.5.3.3 Last command register
This register contains command or data from last command error. This is a 16-bit register.
1.5.3.4 Diagnostic register
This is a 16-bit register. Its structure is shown in Figure 36:
Figure 34 Status register
0246 135
HV1 enabledHV2 enabledAEM A veto enabledAEM B veto enabled last TACK zero suppression
side B enabled
MBZ
16
Figure 35 Last command register
0
last command
16
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valid command counter: Counts the number of valid commands seen by the GARC after reset. Note: TACKs are not counted by this register, but CALSTROBEs are.
command counter: Counts the number of commands seen by the GARC after reset. Note: Both TACKs and CALSTROBEs are counted by this register.
command error: Latches to true if command was invalid or had invalid parity.
data parity error: Latches to true if command data had invalid parity.
command parity error: Latches to true if command type parity or command parity were invalid.
parity error: Logical OR of command parity error and data parity error.
1.5.3.5 Command reject register
This register contains the number of rejected commands. This is an 8-bit register
Figure 36 Diagnostic register
0816 15 14 13 12
command countervalid command counter
command errordata parity errorcommand parity errorparity error
Figure 37 Command reject register
0
rejected commands
16MBZ
8
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1.5.3.6 FREE ID register
This register contains the GARC serial number. This is an 8-bit register. Note: The value of this register is valid only after the GARC has processed at least one TACK command.
1.5.3.7 GARC version register
This register contains the GARC version number. This is a 3-bit register.
1.5.4 GARC registers (function block 3, 4 and 5)
Figure 38 FREE ID register
0
GARC serial number
16MBZ
8
Figure 39 GARC version register
0
GARC version number
16 3
MBZ
Table 12 The GARC registers (function block 3)
Name Number Access Reg # Description
PHA_THRESHOLD_0 56 R/W 8 PHA threshold for channel 0
PHA_THRESHOLD_1 57 R/W 9 PHA threshold for channel 1
PHA_THRESHOLD_2 58 R/W 10 PHA threshold for channel 2
Total 7
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1.5.4.1 PHA threshold registers
These registers set the minimum value that a channel must exceed in order for the GARC to send out its PHA. They are used by the GARC only in zero suppression mode. They are 12-bit registers. On reset, its value is 0x45a.
PHA_THRESHOLD_3 59 R/W 11 PHA threshold for channel 3
PHA_THRESHOLD_4 60 R/W 12 PHA threshold for channel 4
PHA_THRESHOLD_5 61 R/W 13 PHA threshold for channel 5
PHA_THRESHOLD_6 62 R/W 14 PHA threshold for channel 6
Table 12 The GARC registers (function block 3)
Name Number Access Reg # Description
Total 7
Table 13 The GARC registers (function block 4)
Name Number Access Reg # Description
PHA_THRESHOLD_7 72 R/W 8 PHA threshold for channel 7
PHA_THRESHOLD_8 73 R/W 9 PHA threshold for channel 8
PHA_THRESHOLD_9 74 R/W 10 PHA threshold for channel 9
PHA_THRESHOLD_10 75 R/W 11 PHA threshold for channel 10
PHA_THRESHOLD_11 76 R/W 12 PHA threshold for channel 11
PHA_THRESHOLD_12 77 R/W 13 PHA threshold for channel 12
PHA_THRESHOLD_13 78 R/W 14 PHA threshold for channel 13
Total 7
Table 14 The GARC registers (function block 5)
Name Number Access Reg # Description
PHA_THRESHOLD_14 88 R/W 8 PHA threshold for channel 14
PHA_THRESHOLD_15 89 R/W 9 PHA threshold for channel 15
PHA_THRESHOLD_16 90 R/W 10 PHA threshold for channel 16
PHA_THRESHOLD_17 91 R/W 11 PHA threshold for channel 17
ADC_TACQ 92 R/W 12 ADC acquisition time
Total 5
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1.5.4.2 ADC Tacq register
This register specifies the delay, in units of sysclk, between the hold signal and the start of ADC conversion. This is a 6-bit register. At the nominal value of sysclk, the delay ranges from 0 ns to
On reset, the delay is 0 (zero).
1.6 The GLAST ACD Front-End Controller (GAFE)
NOTE: This section, which discusses the GAFE registers, is under construction.
NOTE: This section reflects ELX’s understanding of how the ACD works. For more information, consult the appropriate ACD documentation.
Figure 40 PHA threshold register
0
PHA threshold
16MBZ
12
Figure 41 ADC Tacq register
63 50 ns× 3150 ns.=
06
delay
MBZ16
Table 15 The GAFE registers
Name Number Access Description
CONFIG_REG 0 R/W Configuration setup
VETO_DAC 1 R/W Set VETO threshold
VETO_VERNIER 2 R/W Set VETO threshold
HLD_DAC 3 R/W Set HLD threshold
Total 11
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1.6.0.1 Configuration register
This register enables charge injection, veto discriminator, HLD discriminator and high gain range. This is a 16-bit register. Value after reset is 0x30. Its structure is shown in Figure 42:
enable TCI: Enables charge injection on CALSTROBE. If this field is clear, charge injection is disabled. If this field is set, charge injection is enabled. On reset, this field is clear.
select manual gain range mode: Indicates whether GAFE should automatically select between high and low gain, depending on the amount of inject charge, or if it should use the gain range select field. If this field is clear, GAFE automatically selects between high and low gain. If this field is set, GAFE uses the gain range select field. On reset, this field is clear.
select high gain range: If the gain range mode is manual, this bit indicates if the GAFE should use high or low gain. If this field is clear, low gain is used. If this field is set, high gain is used. On reset, this field is clear.
BIAS_DAC 4 R/W Set bias value
TCI_DAC 5 R/W Set injected charge
VERS_ADDR 6 read only Version number
WRITE_CTR 7 read only Number of load commands since reset
REJECT_CTR 8 read only Number of commands rejected since reset
LOOP_CTR 9 read only Number of commands since reset
CHIP_ADDR 10 read only GAFE chip address
Table 15 The GAFE registers
Name Number Access Description
Total 11
Figure 42 Configuration register
0246 1357
unusedenable TCIselect manual gain range mode
enable high range TCIenable HLD discriminatorenable veto discriminatorselect high gain range
16MBZ
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enable veto discriminator: Enables veto discriminator output. If this field is set, veto discriminator is enabled. If this field is clear, veto discriminator is disabled. On reset, this field is set.
enable HLD discriminator: Enables HLD discriminator output. If this field is set, HLD discriminator output is enabled. If this field is clear, HLD discriminator output is disabled. On reset, this field is set.
enable high range TCI: Enables the injection system to simulate very high charge injection at GAFE input. If this field is set, the simulation is enabled. If this field is clear, the simulation is disabled. On reset, this field is clear.
1.6.0.2 Veto DAC register
This register sets the coarse veto threshold. This is a 6-bit register. The veto threshold, in MIPs, is , where n is the register value. On reset, the value is 0x39.
1.6.0.3 Veto Vernier register
This register sets the fine veto threshold on top of VETO_DAC. This is a 6-bit register. The fine veto threshold, in MIPs, is , where n is the register value. On reset, the value is 0x26.
1.6.0.4 HLD threshold register
This register sets the HLD threshold. This is a 6-bit register. The HLD threshold, in MIPs, is , where n is the register value. On reset, the value is 0x37.
Figure 43 Veto DAC register
6.3 0.1– n×
06
coarse veto threshold
MBZ16
Figure 44 Veto Vernier register
0.003 n×
06
fine veto threshold
MBZ16
119 1.9– n×
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1.6.0.5 Bias DAC register
This register sets the shift of the base line. This is a 6-bit register, but only the 3 least significant bits are actually used. The shift in the baseline, in MIPs, is for the low energy channel and for the high energy channel, where n is the register value. On reset, the value is 0x20.
1.6.0.6 TCI DAC Register
This register sets the amount of the charge injected upon a CALSTROBE command. This is a 6-bit register. The amount of injected charge, in MIPs, is when TCI low range is enabled and when TCI high range is enabled, where n is the register value. On reset, the value is 0 (zero).
Figure 45 HLD threshold register
06
HLD threshold
MBZ16
Figure 46 Bias DAC register
0.625 n×62.5 n×
06
shift
MBZ16
not used (MBZ?????)
Figure 47 TCI DAC register
1.0 n×17.5 n×
06
injected charge
MBZ16
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1.6.0.7 Version address register
This register contains the GAFE version number. This is a 3-bit register.
1.6.0.8 Write counter register
This register contains the number of load commands since reset. This is a 6-bit register.
1.6.0.9 Reject counter register
This register contains the number of commands rejected since reset. This is a 6-bit register.
1.6.0.10 Loop counter register
This register contains the number of commands since reset. This is a 6-bit register. Note: CALSTROBE and TACK are not interpreted as commands from the GAFE.
Figure 48 Version address register
0
GAFE version number
16 3
MBZ
Figure 49 Write counter register
06
load commands count
MBZ16
Figure 50 Reject counter register
06
rejected commands count
MBZ16
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1.6.0.11 Chip address register
This register contains the GAFE chip addresses from 0 to 17. This is 5-bit register.
Figure 51 Loop counter register
06
commands since reset count
MBZ16
Figure 52 Chip address register
05
GAFE chip address
16MBZ
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 2 Commanding Version/Issue: 2.11/3
Chapter 2
Commanding
2.1 Overview
2.1.1 Conventions
All data structures described in this chapter are from the perspective of being “on-the-wire.” Therefore, the left-most field in any description is transmitted first, or is considered to be transmitted on the zeroth clock. Fields are numbered from the beginning of the command string described in [1].
2.1.2 Introduction
This chapter describes the remote protocol necessary to access both the registers1 and functional blocks of the AEM. It draws on the Command/Response Protocol discussed in [1]. Commanding is hierarchical; i.e., to access any specific register or functional block, it is necessary to specify a hierarchical path to that block or register. Thus, for example, to access a register in an ACD Front-End ASIC (GAFE), one must go through a AEM and GARC. The commanding hierarchy of the AEM is illustrated in Figure 53. Note that operations are defined on both the registers of a functional block and on the block itself. Access to the functions of block are commonly known as a performing a dataless command.
1. Enumerated and described in Chapter 1
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Two of the AEM’s functional blocks are located physically on the AEM as specified in the shaded blocks of Figure 53. Access to on-board or off-board blocks is specified in the first 9-bits, or prefix, of the command string. As there are two on-board blocks and one off-board block, there are three possibilities for the prefix as shown in Figures 54, 55 and 56.
Figure 53 Hierarchy of target types
Figure 54 Command string prefix for accessing the Common Controller of the AEM
Figure 55 Command string prefix for accessing the Environmental Monitor of the AEM
Figure 56 Command string prefix for accessing off-board functional blocks and registers of the AEM
GAFE
GARC
registers
registers
registers
AEM
env
registers
type
2
instance
0 8
external
9
parity
7
broadcast
00increasing clock
0 03
0
type
2
instance
0 8
external
9
parity
7
broadcast
01increasing clock
0 03
0
type
20 8
external
9
parity
7
broadcast
00increasing clock
13
cable number
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Note that accessing the off-board registers requires specification of which of twelve FREE boards should be accessed. This is specified by the cable number field described in Figure 56. The relationship between cable number and FREE board name is enumerated in Table 18 on page 68.
2.2 The AEM’s access descriptors
The AEM has two on-board functional blocks; the first called the Common Controller and the second called the environmental monitor. Each of these block types has its own set of internal registers. In addition the AEM services 12 FREE boards, each of which has its own functional blocks and registers. These FREE boards constitute the AEM’s off-board functional blocks and registers. Thus, the AEM has two different kinds of access descriptors:
ACD: The command will be relayed by the AEM to its appropriate off-board block (on a FREE board) where the command will actually be executed.
Local: The access is constrained entirely within the Common Controller.
2.2.1 ACD access descriptor
The ACD access descriptor allows access to all off-board functional blocks and registers. The access descriptor, when used as part of a command, is prefixed with a fixed four-bit start pattern as illustrated in Figure 57. The access descriptor is also returned as one part of a response to a Read command. However, in this case, it does not include the start pattern. (See, for example, Section 2.6.3.)
Figure 57 Access descriptor for external ACD commands
function
21 26
GAFE address/GARC block
10 19
parity
14
GAFE target
9
register/opcode
25 increasing clock
start pattern
1 0 0 1
13
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GAFE target: This field determines whether the command is intended for the GARC itself or should be forwarded to one or more of the GAFEs managed by the GARC. If the field is true, the command is forwarded to the GAFE whose address is determined by the GAFE address/GARC block field, and the interpretation of the register/opcode field is GAFE specific. If the bit is false, the command is forwarded to the functional block determined by the GAFE address/GARC block field, and the interpretation of the register/opcode field is GARC specific.
GAFE address/GARC block: The address of the functional block targeted by this command. Its interpretation is dependent on the GAFE target field.
— If the GAFE target field is true, this field corresponds to the address of a GAFE. There are 18 possible GAFE addresses varying from zero (0) to seventeen (17). In addition, a value of 0x1F (all bits set) targets all the GAFEs managed by the specified GAFE. This address is called the broadcast address. The broadcast address is not permitted if the function field specifies a read operation.
— If the GAFE target field is false, this field corresponds to a function block within the specified GARC. Function blocks are number from zero (0) through five (5). Within each function block are a number of registers. A specific register within the function block register is determined by the value of the register/opcode field.
function: Enumerates what type of access is required of the target, by the command;1 for example, whether the command will either read or write the specified register. The valid enumerations for this field are described in [1].
register/opcode: If the function field has the value read or load, this field contains the number of the register to be accessed. If the function is dataless, this field determines the type of dataless access. The interpretation of this field depends also on the value of the GAFE target field.
parity: The odd parity value over the entire access descriptor less the first start bit. (This is the dark grayed-out field.)
1. ACD doesn’t really support dataless functions. However, as designed, it does ignore the dataless functioncode and should treat it as a write function. It must continue to do in order to meet LAT communicationsstandards.
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2.2.2 Local Access Descriptor
function: Enumerates what type of access is required of the target by the command; for example, whether the command will either read or write the specified register. The valid enumerations for this field are described in [1].
register/opcode: If the function field has the value read or load, this field contains the number of the register to be accessed. If the function is dataless, this field determines the type of dataless access.
parity: The odd parity value over the entire access descriptor less the first (or start) bit.
2.3 Accessing the Common Controller (or AEM)
2.3.0.1 Dataless commands
Figure 58 Access descriptor for local commands
function
2019
parity
9
register/opcode
12
1
10 increasing clock
Table 16 The Common Controller’s dataless commands
Name Opcode Description
Reset 1 Hard reset of the AEM
Total 1
Figure 59 Access descriptor for AEM dataless functions
type
2
instance
0 8
external
9
parity
7
broadcast
00
function
2019
parity
9
opcode
12
0010 increasing clock
0 03
10
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2.3.0.2 Load commands
Load functions require a 33-bit payload, as they are protected with a trailing parity field. The computed value of the parity field is the odd parity over the preceding 32 bits of data which are to be loaded into the register. The format of this payload is illustrated in Figure 61. As a load requires no response, the respond field of the packet is set to false.
2.3.0.3 Read commands
Read functions require no payload. The value of the register read is returned as a response. As these reads do generate a response, the command packet’s respond field is set to true. The format of that response is illustrated in Figure 63.
Figure 60 Access descriptor for AEM register load commands
Figure 61 Payload for AEM register load commands
type
2
instance
0 8
external
9
parity
7
broadcast
00 0
function
2019
parity
9
register
12
0110 increasing clock
0 03
1
5220
parity
increasing clock53
data
Figure 62 Access descriptor for AEM register read commands
type
2
instance
0 8
external
9
parity
7
broadcast
00 0
function
2019
parity
9
register
12
1010 increasing clock
0 03
1
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2.4 Accessing the environmental monitor
2.4.0.1 Load commands
Load functions require a 65-bit payload, as they are protected with a trailing parity field. The computed value of the parity field is the odd parity over the preceding 64 bits of data which are to be loaded into the register. The format of this payload is illustrated in Figure 65. As a load requires no response, the respond field of the packet is set to false.
Figure 63 Response to AEM register read commands
320 increasing clock
data
Figure 64 Access descriptor for environmental monitor register load commands
Figure 65 Payload for environmental monitor register load commands
type
2
instance
0 8
external
9
parity
7
broadcast
01 0
function
2019
parity
9
register
12
0110 increasing clock
0 03
1
8420
parity
increasing clock85
data
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2.4.0.2 Read commands
Read functions require no payload. The value of the register read is returned as a response. As these reads do generate a response, the command packet’s respond field is set to true. The format of that response is illustrated in Figure 67.
2.5 The GLAST ACD Readout Controller (GARC)
Note: The ACD ICD [3] states that the trailing parity is calculated as odd, over the previous fifteen (15) bits, or starting at bit offset ten (10).
Figure 66 Access descriptor for environmental monitor register read commands
Figure 67 Response to environmental monitor register read commands
type
2
instance
0 8
external
9
parity
7
broadcast
01 0
function
2019
parity
9
register
12
1010 increasing clock
0 03
1
640 increasing clock
data
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2.5.1 Dataless commands
Dataless functions do require a payload. The structure of the payload is the same as the 17-bit payload for Load functions; however, the data portion must be zero. The format of this payload is illustrated in Figure 69. As dataless functions require no response, the respond field of the packet is set to false.
Table 17 The GARC dataless commands
Name OpcodeFunction Block Register Description
RESET 1 0 1 Hard reset of the GARC
CALSTROBE1
1. Reserved for internal use to AEM.
3 0 3 Generate calibration strobe
SET_HVBS2
2. See Table 9 on page 33.
10 0 10 Set HV to normal value
SET_HVSAA 11 0 11 Set HV to SAA value
Total 4
Figure 68 Access descriptor for GARC dataless commands
type
2
GARC
0 8
external
9
parity
7
broadcast
00 13
function
21 26
GARC block
13 19
parity
14
GAFE target
9
1 0 0 1
opcode
25 increasing clock0 01
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Note: Need to edit Figure 68 (9-13).
2.5.2 Load commands
Load functions require a 17-bit payload. The format of this payload is illustrated in Figure 71. As a load requires no response, the respond field of the packet is set to false.
Figure 69 Payload for GARC dataless and read commands
4226 43
parity
increasing clockMBZ
Figure 70 Access descriptor for GARC register load commands
Figure 71 Payload for GARC register load commands
type
2
GARC
0 8
external
9
parity
7
broadcast
00 13
function
21 26
GARC block
13 19
parity
14
GAFE target
9
1 0 0 1
register/opcode
25 increasing clock0 01
4226 43
paritydata
increasing clock
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2.5.3 Read commands
Read functions do require a payload. The structure of the payload is the same as the 17-bit payload for Load functions; however, the data portion must be zero. The format of this payload is illustrated in Figure 69. The value of the register read is returned as a response. As these reads do generate a response, the command packet’s respond field is set to true. The format of that response is illustrated in Figure 73.
Note that the returned access descriptor includes the first field of the start pattern. (See Section 2.2.1.)
2.6 The GLAST ACD Front-End Controller (GAFE)
Note: The ACD ICD [3] states that the trailing parity is calculated as odd, over the previous fifteen (15) bits, or starting at bit offset ten (10).
Figure 72 Access descriptor for GARC register read commands
Figure 73 ACD response to GARC register read commands
type
2
GARC
0 8
external
9
parity
7
broadcast
00 13
function
21 26
GARC block
13 19
parity
14
GAFE target
9
1 0 0 1
register
25 increasing clock0 11
3014 31
parity
dataerror summary
access descriptor
1 32 increasing clock1
0
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2.6.1 Dataless commands
None.
2.6.2 Load commands
Load functions require a 17-bit payload. The format of this payload is illustrated in Figure 75. As a load requires no response, the respond field of the packet is set to false.
Figure 74 Access descriptor for GAFE register load commands
Figure 75 Payload for GAFE register load commands
type
2
GARC
0 8
external
9
parity
7
broadcast
00 13
function
21 26
GAFE address
13 19
parity
14
GAFE target
9
1 0 0 1
register
25 increasing clock1 01
4226 43
paritydata
increasing clock
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2.6.3 Read commands
Read functions do require a payload. The structure of the payload is the same as the 17-bit payload for Load functions; however, the data portion must be zero. The format of this payload is illustrated in Figure 69. The value of the register read is returned as a response. As these reads do generate a response, the command packet’s respond field is set to true. The format of that response is illustrated in Figure 77.
Note that the returned access descriptor includes the first bit of the start pattern. (See Section 2.2.1.)
Figure 76 Access descriptor for GAFE register read commands
Figure 77 Response to GAFE register read commands
type
2
GARC
0 8
external
9
parity
7
broadcast
00 13
function
21 26
GAFE address
13 19
parity
14
GAFE target
9
1 0 0 1
register/opcode
25 increasing clock1 11
3014 31
parity
dataerror summary
access descriptor
1 32 increasing clock1
0
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 3 Events Version/Issue: 2.11/3
Chapter 3
Events
3.1 Introduction
This chapter describes the format of the event data generated by the AEM in response to receiving a trigger message. The shape of the AEM’s event data is governed by the Event Data Protocol (EDP) described in [1].
3.1.1 Background
The ACD consists primarily of scintillating tiles.1 The light output of any one tile is captured twice by two individual fibers, in order to satisfy redundancy requirements. Currently, both fibers are envisioned as being always active, with a fiber’s data being ignored when it fails. Consequently, while from the perspective of fail-over each fiber stands alone, it is convenient from a structural perspective to consider tiles as serviced by a fiber pair. One half of the pair is referred to as the A-fiber and the other half as the B-fiber. The entire ACD contains a total of 216 fibers, or 1082 fiber pairs. The servicing of one fiber is done through an ASIC called the GLAST ACD Front-End (GAFE). In turn, 18 GAFEs are managed and serviced by another ASIC called the GLAST ACD Readout Controller (GARC). A GARC and its GAFEs are all contained on a single PCB called the FREE board. Data is brought redundantaly from each FREE board to the AEM on two cables: the primary cable goes to the primary DAQ board and the redundant cable, to the redundant DAQ board. As each DAQ board contains its own AEM, the issue of cable redundancy will be ignored in this chapter. Consequently, it is convenient to think of the AEM as servicing twelve FREE boards, six for the A-fibers and six for the B-fibers.
1. I ignore the so-called “duct tape.”
2. Actually, potential electronics channels. Geometric considerations leave some channels unoccupied.
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3.2 The event contribution
From the perspective of event readout, it is convenient to consider the ACD as emitting data from twelve cables, with the data from each cable corresponding to a particular FREE board. The correspondence between cable number and FREE board is enumerated in Table 18:
Each FREE board produces information from eighteen individual channels. Figure 78 describes the correspondence between the tiles of the ACD, FREE boards and channel numbers. A channel corresponds to the information from a single fiber serviced through one GAFE. The data on a cable corresponds to the aggregate of data from eighteen GAFEs serviced through one GARC. Each channel of the ACD is capable of producing three kinds of information:
i. Discriminated hit (or veto) information
ii. Discriminated accept information
iii. Zero suppressed, pulse height information
Thus, each cable emits both a fixed and variable sized component. The total contribution of the AEM is just the sum of the twelve FREE boards it services1 as illustrated in Figure 79:
Table 18 Relationship between cable number and FREE board
Cable number FREE board
0 1LA
1 1RB
2 2LA
3 2LB
4 2RA
5 2RB
6 3LA
7 3RB
8 4LA
9 4LB
10 4RA
11 4RB
1. See Section 3.2.3 for the exceptions to this rule.
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 3 Events Version/Issue: 2.11/3
Figure 78 ACD tile mapping
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17Shiblie Changes 11/08/02
0 17 0 171 16 1 162 15 2 153 14 3 144 13 4 135 12 5 126 11 6 117 10 7 108 9 8 99 8 9 8
10 7 10 711 6 11 612 5 12 513 4 13 414 3 14 315 2 15 216 1 16 117 0 17 0
0 17 0 171 16 1 162 15 2 153 14 3 144 13 4 135 12 5 126 11 6 117 10 7 108 9 8 99 8 9 8
10 7 10 711 6 11 612 5 12 513 4 13 414 3 14 315 2 15 216 1 16 117 0 17 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Rev 2.0
032 022
033 023 013
310300
003
403
423
413
303 302 301313 312 311
104114
314304
042
043
1130
1R
B
1500
1100
1110
1120
1102
1101
1111
1121
1113
1103
1122
1112
1501
1123
0502
0120
1124
-X
0101
0111
0121
0103
0102
0112
0122
120130
1L
A
0130
0124
0114
0104
0503
0123
0113
124 123 122 121
2LA
113 112 111103 102 101 100
110
0420
4RA 4RB 2LB
410
0040 1040 420
0030
01000430 1114 1230 0110
1210 02101420 1220 0220
040 030 020
1000 000002001200
010 0001600 0600
220
1010 0010
1104
0400 1400
200
210
400
1030
1221 02210421 1421 1020 0020
0410 1410
1201
421
4110041 1041
0411 1411
02010401 1401 1211 0211
041 031 021
0412
00110031 1031 1001 0001
221
1022 00220402 1402 1021 00210032 1032 1011
011 001 201
211
401
1412
00020601 1601
222
06020042 1042 1222 0222
0422 1422 1002
012 002 202
212
402
1602
422
412+Y
430
0023 1023
0043 1043 223
1223
1203
101212020033 1033
00240423 14230413
0203
1013203
213
0223
0012
230
1213 0213
0003
0202
10030013
02121212
00040044 1044 1014 0014
1004
4240603
0414 1414 1204 02041603
404 044 034
0314
02240424 1424 1214 0214024 014 004 2
04
414
02300304 1300
214
224
1310
1224
1430
0404 1404
0403
10240034 1034
14131403
4LA 4LB 2RB 2RA0330
3L
A
330324 323 322 321 320
0500
0300
0310
0320
0302
0301
0311
0321
0313
0303
0322
0312
0501
0323
1502
1320
0324
1301
1311
1321
1303
1302
1312
1322
-Y
+X
3R
B
1330
1324
1314
1304
1503
1323
1313
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 3 Events Version/Issue: 2.11/3
3.2.1 The cable header
Each contribution from each cable begins with a fixed 48 bits of information as illustrated in Figure 80:
Figure 79 Overall structure of the AEM’s natural event data
cable0
016
header
PHA vector
cable1
cablen
header
header
PHA vector
PHA vector
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 3 Events Version/Issue: 2.11/3
Start-bit: Specifies whether the AEM detected a start-bit before the timeout period. If the field is set, the start-bit for the cable was detected. One may infer, if this field is clear, a timeout on the cable occurred.
Hit map (0-14): The first fifteen channels of the hit map. If a bit at a specified offset is set, the corresponding channel is hit. Channels are organized in ascending order. The LSB bit offset corresponds to the high-order channel. For example, if bit offset 0 is set, a hit occurred on channel 0, or if bit offset 14 is set, a hit occurred on channel 14.
Hit map (15-17): The last three channels of the hit map. If a bit at a specified offset is set, the corresponding channel is hit. Channels are organized in ascending order. The LSB bit offset corresponds to the high-order channel. For example, if bit offset 13 is set, a hit occurred on channel 15, or if bit offset 15 is set, a hit occurred on channel 17.
Accept map (0-12): The first thirteen channels of the zero suppression map. If a bit at a specified offset is set, the corresponding channel’s PHA discriminator was above threshold. Channels are organized in ascending order. The LSB bit offset corresponds to the high-order channel. For example, if bit offset 0 is set, channel 0 was above threshold.
Accept map (13-17): The last five channels of the zero suppression map. If a bit at a specified offset is set, the corresponding channel’s PHA discriminator was above threshold. Channels are organized in ascending order. The LSB bit offset corresponds to the high-order channel. For example, if bit offset 11 is set, channel 13 was above threshold, or if bit offset 15 is set, channel 17 was above threshold.
PHA vector: Specifies whether one or more PHA values follow the header. If this field is set, at least one PHA value follows the header. If the field is clear, there were no PHA values emitted by the cable for this event.
Header parity error: Specifies whether the AEM detected a parity error when attempting to process its input event data. This field is set if a parity error occurs.
Figure 80 Structure of cable header
Hit map0-14Hit map15-17Accept map0-12Accept map13-17PHA vector Header parity error
016
Start-bit
910111315
End of Cables
8 4
Cable number
MBZ
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 3 Events Version/Issue: 2.11/3
End of Cables: Specifies whether any cable contribution follow this contribution. If this field is clear, additional cable contributions follow. If this bit is set, this contribution is the last. If there are no contributions, this field will be set and the cable number (discussed below) will have a value of 0F (hexadecimal). See Section 3.2.3 for more information.
Cable number: Specifies the cable number of the contribution. The relationship between cable number and FREE board is enumerated in Table 18. If there are no contributions, the End of Cables (discussed above) will be set, and the cable number will have a value of 0F (hexadecimal). See Section 3.2.3 for more information.
3.2.2 The PHA vector
Following the header is a n x 16-bit vector containing Pulse Height data. Each element of this vector is a Pulse Height Analysis (PHA) value. The format of a PHA value is illustrated in Figure 81.
parity error: Parity is computed on each PHA value sent on a cable. If the parity calculation fails, this field is set. Note that PHA parity errors are not included in the event summary.
ADC value: The 12-bit ADC value of the PHA.
ADC range: Specifies one of the two different ADC ranges. The field is set for high range, clear for low range.
more: Specifies whether additional PHA values follow. If another PHA value follows, this field is set. If this is the last PHA value, this field is clear.
Note that the PHA vector is only present if the PHA vector field of the header is set. If present, the length of the vector is determined by following the more field of each PHA value of the vector.
3.2.3 Relationship between input masking and number of components
Normally, the event contribution will be made up of data from 12 free boards. However, if any one free-board’s input is masked off (as discussed in Section 1.3.1), the data for that FREE board will not appear in the event contribution. Therefore, potentially, the contribution could
Figure 81 Structure of a PHA value
parity error
1 016 15 13
ADC value ADC range more
14
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The ACD Electronics Module (AEM) Programming ICD specificationChapter 3 Events Version/Issue: 2.11/3
have both holes and a reduced number of components. In order to handle this eventuality, the header contains both a cable number and a field which specifies whether additional components follow. See Section 3.2 for more information. Note: Independent of the number of enabled components, the cable numbers will follow in increasing order, from the lowest enabled cable, to the highest enabled cable.
3.3 The error contribution
There is no error contribution.
3.4 The diagnostic contribution
There is no diagnostic contribution.
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