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The 5th IEEE Workshop on Design & Diagnosis of ectronic Circuits & Systems (DDECS'02 ) Configware / Software Co- Design: be prepared for the Next Revolution! . Reiner Hartenstein University of Kaiserslautern Brno, Czech Republic, April 17 - 19, 2002 viewgraph downloading: link in http://kressarray.de

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Page 1: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

The 5th IEEE Workshop on Design & Diagnosis of

Electronic Circuits & Systems(DDECS'02)

Configware / Software Co-Design: be prepared for the Next

Revolution!

.

Reiner Hartenstein

University ofKaiserslautern

Brno, Czech Republic, April 17 - 19, 2002

viewgraph downloading: link inhttp://kressarray.de

Page 2: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de2

University of Kaiserslautern

Xputer LabSemiconductor Revolutions

“Mainstream Silicon Applicationis switching every 10 Years”

TTL µproc.,memory

“The Programmable System-on-a-Chipis the next wave“

custom

standard

1957

1967

1977

1987

1997

2007

Makimoto’s Wave

ASICs,accel’s

LSI,MSI 1

st D

esig

n C

risis

2n

d D

esig

n C

risis

reconfigurable

Published

in 1989

Tredennick’sParadigm Shifts

hardwired

algorithm: fixed

resources: fixed

procedural programming

algorithm: variable

resources: fixed

structural programming

algorithm: variable

resources: variable

Page 3: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de3

University of Kaiserslautern

Xputer LabImpact of Makimoto’s

wave

TTL µproc.,memory

custom

standard

ASICs,accel’s

LSI,MSI

reconfigurable

1957

1967

1977

1987

1997

2007

Proceduralpersonalization via RAM-based

Machine Paradigm

Personalization(CAD) beforefabrication

structuralpersonalization:

RAM-basedbefore run time

Software Industry’sSecret of Success

Repeat Success Story bynew Machine Paradigm !

ConfigwareIndustry

Page 4: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de4

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://KressArray.de

University of Kaiserslautern

Xputer LabReconfigurable goes mainstream

Topic adopted by congresses: ASP-DAC, DAC, DATE, ISCAS, SPIE ....

http://www.lirmm.fr/fpl2002/

FPL 2002: 214 Submissions -sensational increase by 83%

•FCCM, FPGA (founded 1992), and FPL (founded 1991 at Oxford, UK):International Conference on Field-programmable Logic and

Applications

•FPL 2002, La Grande Motte (Montpellier, France), Sept. 2 – 4

Page 5: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de5

University of Kaiserslautern

Xputer Lab

Makimoto’s 3rd wave

Reconfigurability

The next Revolution:

1978

Transistor entry: Applicon, Calma, CV ...

1992Synthesis: Cadence, Synopsys ...

1985

Schematics entry: Daisy, Mentor, Valid ...

[Keutzer / Newton]

EDA industry paradigmswitching every 7 years

1999(Co-) Compilation &

Data-stream-based (r)DPAs[Hartenstein]

2006

Paradigm Shift

Mainstream

TornadoM

cKin

sey

Curv

e

[Richard Newton]

[Keutzer / Newton]

82% of designershate their tools

Page 6: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de6

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://KressArray.de

University of Kaiserslautern

Xputer Lab missing the next revolution

Page 7: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de7

University of Kaiserslautern

Xputer Lab.... it‘s an alternative culture

....

•now the area is going mainstream: a rapidly widening audience of non-specialists gets interested ...

•severe communication gaps due to educational deficits

•not only to users: still many hardware and EDA experts ask: isn’t it just logic design on a strange platform ?

• it is time to clarify and popularize fundamental aspects and to explain, that it is a fundamentally different culture

Page 8: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de8

University of Kaiserslautern

Xputer Lab>> Outline

• Introduction

•The CPU Machine Paradigm

•DPU & DPA : Antimatter of Computing

•Reconfigurable Computing

•Dominance of Embedded Systemshttp://www.uni-kl.de

Page 9: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de9

University of Kaiserslautern

Xputer Lab

Antimatter Search

.... the Antimatter of CPU-based Computing

•Reconfigurable or Hardwired: Datastream-based Computing is the Antimatter of classical Computing

•This Antimatter has been mainly ignored

• „Antimatter: where is it ?“

Page 10: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de10

University of Kaiserslautern

Xputer LabThe anti universe

•Paul Dirac predicted a complete anti universe consisting of antimatter

•“There are regions in the universe, which consist of antimatter .....

•We are not aware, that there is a new area in computing sciences , which consists of antimatter of computing

•.... But there are asymmetries”

•Reconfigurable Computing is made from this antimatter, especially if it’s data-stream-based

•when a particle hits its antiparticle, both are converted into energy: Annihilation

•.... But there are asymmetries

• and Annihilation(CS curricula)

Page 11: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de11

University of Kaiserslautern

Xputer LabAnti atom created

•1956: anti neutron created on Bevatron

•1928: Paul Dirac: „there should be an anti electron having positive charge“ (Nobel price 1933)

•1932: Carl David Anderson detected this „positron“ in cosmic radiation (Nobel price 1936)

•1955 Owen Chamberlain et al. create anti proton on Bevatron

•1954: new accelerators: cyclotron, like Berkeley‘s Bevatron

•1965: creation of a deuterium anti nucleus at CERN

hydrogen anti hydrogen

•1995: hydrogen anti atom created at CERN – by forcing positron and anti proton to merge by very low energy.

sorry, there is no nobel price

in CS

Page 12: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de12

University of Kaiserslautern

Xputer LabMatter & Antimatter: Atom and Anti

Atom

The World of MatterMachine paradigm:the Atom

Anti Matter

Machine paradigm:Anti Atom

++Electron spinning-

--Positron spinning

+

Page 13: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de13

University of Kaiserslautern

Xputer LabInformatics: Matter & Antimatter:

Anti Machine

instruction stream

spinning

Machine and Anti Machine

+CPU

- 1936 1st el. computer (Konrad Zuse)

Machine paradigm:„von Neumann“Computer

1946 v. N. machine paradigm1971 1st microprocessor (Ted Hoff)

data stream spinning

1979 „data streams“ (systolic array: Kung / Leiserson)

1995 rDPA / DPSS (supersystolic: Rainer Kress)

data-procedural:Xputer

-DPU

+

1990 Xputer machine paradigm

Page 14: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de14

University of Kaiserslautern

Xputer Lab>> The CPU Machine Paradigm

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– FPGA boom

• Dominance of Embedded Systemshttp://www.uni-kl.de

Page 15: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de15

University of Kaiserslautern

Xputer Lab RAM-based

+CPU

DataPath

instructionsequencer RAM

+ simple machine paradigm+ scalability

+ relocatability+ compatibility

= secret of success of software industry

CPU:

Page 16: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de16

University of Kaiserslautern

Xputer LabNasty Matter

+CPU

DataPath

instructionsequencer

Central Processing Unit

RAM

Address Computation Overhead

Instruction Fetch Overhead

central von

Neumannbottleneck

extremely power hungry and area inefficient

performance problems

reconfigurable?

the wrong machine paradigm

alw. new instructionsequencer needed

Page 17: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de17

University of Kaiserslautern

Xputer Lab>>> Concurrency

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– FPGA boom

• Dominance of Embedded Systemshttp://www.uni-kl.de

Page 18: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de18

University of Kaiserslautern

Xputer LabParallelism by Concurrency

+-

+-

-+

- +

+-- +

-+

independent instruction streams

Page 19: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de19

University of Kaiserslautern

Xputer Lab Concurrent Computing

....

Bus(es) or switch box

DataPath

instructionsequencer

DataPath

instructionsequencer

DataPath

instructionsequencer

DataPath

instructionsequencer

DataPath

instructionsequencer

DataPath

instructionsequencerextremely inefficient

CPU

•massive switching activity at runtime•may affect far beyond Amdahl‘s law

Page 20: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de20

University of Kaiserslautern

Xputer Lab

Dead Supercomputer Society

•ACRI •Alliant •American Supercomputer •Ametek •Applied Dynamics •Astronautics •BBN •CDC•Convex•Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent

•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland•Computer•Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel . Machines •Kendall Square Research •Key Computer Laboratories

[Gordon Bell, keynote at ISCA 2000].

•MasPar•Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer•Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics

Page 21: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de21

University of Kaiserslautern

Xputer Lab>> DPU & DPA: Antimatter of

Computing

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– FPGA boom

• Dominance of Embedded Systemshttp://www.uni-kl.de

Page 22: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de22

University of Kaiserslautern

Xputer LabSome differences: CPU versus DPU

+CPU

DataPath

instructionsequencer

transport-triggered

-DPU

DataPathUnit

DPU

data

str

eam

s

datastreamsscheduledelsewhere

instruction streamroutedhere

RAM

datasequencer

RAM

datasequencer

externalsignal, or

nothing central

no vN bottleneck:multiple portsno instructionfetch at run time:no overhead

Page 23: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de23

University of Kaiserslautern

Xputer Lab

© 2001, [email protected]

University of Kaiserslautern

Xputer Lab

instructions

programcounter:

state register

CompilerRAM

Datapath

hardwired

Sequencer

Computer Computer tightly coupledby compact

instruction code

“von Neumann”

“von Neumann”does not supportsoft data pathsdoes not supportsoft data paths

Datapath

reconfigurable

Xputer Xputer

Scheduler

CompilerRAM

(multiple)sequencer

DatapathArray

“instructions”

University of Kaiserslautern

Xputer Lab

loosely coupledby decision data bits only

Xputer:Xputer:The Soft Machine Paradigm

The Soft Machine Paradigm reconfigurablereconfigurable

also for hardwiredalso for hardwired

Computer:the wrong Machine Paradigm

“von Neumann”

data stream specthere are some differences

sdatacounter

(anti machine)

Page 24: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de24

University of Kaiserslautern

Xputer LabMachine Paradigms

machine category Computer

(“v. Neumann”) Xputer

(no transputer!)

driven by: Instruction streams data streams (no “dataflow”)

engine principles instruction sequencing sequencing data streams

state register program counter (multiple) data counter(s)

communication path set-up

at run time at load time

resource DPU (e.g. single ALU) DPU or DPA (DPU array) etc. data path operation sequential parallel pipe network etc.

Page 25: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de25

University of Kaiserslautern

Xputer LabProgramming Language

Paradigms

language category Computer Languages Xputer Languages

both deterministic procedural sequencing: traceable, checkpointable

operationsequencedriven by:

read next instruction, goto (instr. addr.),

jump (to instr. addr.), instr. loop, loop nesting

no parallel loops, escapes,instruction stream branching

read next data item, goto (data addr.),

jump (to data addr.),data loop, loop nesting,parallel loops, escapes,data stream branching

state register program counter data counter(s)addresscomputation

massive memorycycle overhead overhead avoided

Instruction fetch memory cycle overhead overhead avoidedparallel memorybank access interleaving only no restrictions

very easy to learn

multipleGAGs

Page 26: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de26

University of Kaiserslautern

Xputer Lab>> DPA

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– FPGA boom

• Dominance of Embedded Systemshttp://www.uni-kl.de

Page 27: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de27

University of Kaiserslautern

Xputer Lab

hardwired interconnect fabrics

Parallelism at data stream level

-DPU -DPU -DPU

-DPU-DPU

-DPU

-DPU-DPU

no switching overhead at run time

mapping before fabrication

nothing central !

reconfigurable interconnect fabrics

configured after fabrication

-rDPU -rDPU -rDPU

-rDPU-rDPU

-rDPU

-rDPU-rDPU

Page 28: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de28

University of Kaiserslautern

Xputer Labmachine paradigm: some differences

+CPU

-

-DPA

++

+

-DPU

+

matter

antimatte

r

no. of streams = 1

no. of streams 1

Page 29: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de29

University of Kaiserslautern

Xputer LabDPA = DPU array

-DPA-

DPU

-DPU

-DPU

-DPU

-DPU

-DPU

-DPU

-DPU

-DPU-

DPA

+

+

+

+

+

+

++

+

cohere

nt

data

str

eam

ssp

innin

g a

round

Page 30: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de30

University of Kaiserslautern

Xputer LabDPA-based entire System

-DPA

RAM

RAMRAM

RAM

RAMRAM

RAMRAM

memory communication architecture

mapping before fabrication

Page 31: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de31

University of Kaiserslautern

Xputer LabDPA-based entire System

-rDPA

RAM

RAMRAM

RAM

RAMRAM

RAMRAM

mapping after fabrication

reconfigurationRAM

reconfigurable memory communication architecture

M. Herz, et al.: Memory Organisation for Stream-based Reconfigurable Computing; IEEE ICECS 2002, Sept. 15-18, 2002, Dubrovnik, Croatia

1995 rDPA Rainer Kress

Page 32: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de32

University of Kaiserslautern

Xputer Lab>> rDPA: Reconfigurable

Computing

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– FPGA boom

• Dominance of Embedded Systemshttp://www.uni-kl.de

Page 33: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de33

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://www.fpl.uni-kl.de

University of Kaiserslautern

Xputer LabCommercial rDPA

XPU family :PACT AG, Munich

XPU128http://pactcorp.com

Page 34: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de34

University of Kaiserslautern

Xputer Lab

rDPU not used used for routing only operator and routing port location markerLegend: backbus connect

array size: 10 x 16 = 160 rDPUsà 32 bits

http://kressarray.de

Academic DPA example

rout thru only

not usedbackbus connect

SNN filter KressArray Mapping

Page 35: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de35

University of Kaiserslautern

Xputer LabSuper Pipe Networks

pipeline properties array applications

shape resources

mapping scheduling

(data stream formation)

systolic array

regular data dependencies

only

linear only

uniform only

linear projection or algebraic synthesis

super-systolic DPA

no restrictions simulated

annealing or P&R algorithm

(e.g. force-directed) scheduling algorithm

The key is mapping, rather than architecture

*) KressArray [ASP-DAC-1995]

Page 36: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de36

University of Kaiserslautern

Xputer Lab>> The FPGA boom

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– The FPGA boom

• The Dominance of Embedded Systemshttp://www.uni-kl.de

Page 37: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de37

University of Kaiserslautern

Xputer LabTop 4 FPGA Manufacturers 2000

Xilinx42%

Altera37%

Lattice15%

Actel6%

Top 4 PLD Manufacturers 2000total: $3.7 Bio

•[Dataquest] > $7 billion by

2003.

•PLD vendors’ and their alliances provide libraries of “soft IPs”Configware Market

•fastest growing semiconductor market segment

Page 38: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de38

University of Kaiserslautern

Xputer LabSoft rDPA ?

Memorysoft CPU

miscellanous

soft

soft

DPUDPU

arra

y

arra

ysoft

soft

DPUDPU

arra

y

arra

y

HLL Compiler

•Rapid technology progress

•50 million system gates soon

•FPGAs f. relocatable configware code ?

•Compatibility at configuration code level ?

•Slower clock: compensated by more parallelism: low

power

•Even large rDPAs as a soft IP become feasible•By >2005: don’t care about area efficiency ?

Page 39: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de39

University of Kaiserslautern

Xputer Lab>> The Dominance of Embedded

Systems

• Introduction

• The CPU Machine Paradigm– Concurrency

• DPU & DPA: Antimatter of Computing– DPA

• rDPA: Reconfigurable Computing– FPGA boom

• The Dominance of Embedded Systemshttp://www.uni-kl.de

Page 40: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de40

University of Kaiserslautern

Xputer LabUbiquitous embedded systems

20 billion µprocessors (2001)

> 90% in embedded systems

10 times more programmers will write embedded applications than computer software by 2010

That’s where our graduates will go

Embedded systems means:

• hardware / software co-design

• configware / software co-design

• hardware / configware / software co-design

Page 41: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de41

University of Kaiserslautern

Xputer LabAnnihilation?

-+

-

+- +

cras

h

avoidable by

tools ....

Page 42: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de42

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://www.fpl.uni-kl.de

University of Kaiserslautern

Xputer LabJürgen Becker’s Co-DE-X Co-Compiler

Analyzer/ Profiler

HostSoftware

GNU Ccompiler

paradigmComputer machine

DPSSKressArrayConfigware

X-Ccompiler

Xputer machineparadigm

Partitioner

Loop

Transfor-

mationsX-C is C languageextended by MoPLX-C

Resource Parameters

supportingdifferentplatforms

supporting platform-based design

Page 43: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de43

University of Kaiserslautern

Xputer LabCS education .....

hardware person

procedural

structural

software personAn

nihi

latio

n?

Configware / Software Co-Design?Hardware / Software Co-Design?

Page 44: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de44

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://www.fpl.uni-kl.de

University of Kaiserslautern

Xputer LabHowever, current CS Education ….

Hardware invisible:under the surface

… is based on the Submarine Model

Brain usage:procedural-only

Software Faculty Colleagues shy away from the Paradigm Shift:their Brain hurts? - can’t be: this Half has been amputated

Algorithm

Assembly Language

procedural high level Programming

Language

Hardware

Software

This model disables ...

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© 2001, [email protected] http://KressArray.de45

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://KressArray.de

University of Kaiserslautern

Xputer Lab

Hardware,Configware

Hardware and Software as Alternatives

Algorithm

Software

partitioning

Software onlySoftware & Hardw/Configw

procedural structural

Brain Usage:both Hemispheres

Hardw/Configw only

Page 46: The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02)DDECS'02 Configware / Software Co-Design: be prepared for the Next

© 2001, [email protected] http://KressArray.de46

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://KressArray.de

University of Kaiserslautern

Xputer LabDominance of the Submarine Model ...

Hardware

... indicates, that our CS education system produces zillions of mentally disabled

Persons

(procedural) structurallydisabled

… completely disabled to cope with solutions other than software only

It‘s time to attack the software faculty dictatorship.Get

involved!

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© 2001, [email protected] http://KressArray.de47

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://KressArray.de

University of Kaiserslautern

Xputer Lab>>> thank you

thank you for your patience

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© 2001, [email protected] http://KressArray.de48

University of Kaiserslautern

Xputer Lab

© 2001, [email protected] http://KressArray.de

University of Kaiserslautern

Xputer Lab>>> END

END