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Effects of Process and Enviromental Variations

on Adder Architectures

Arun Thakur, Dinesh Chilamakuri, and Dimitrios VelenisDept. of Electrical and Computer Engineering

Illinois Institute of Technology

Chicago, Illinois 60616

Email: [email protected], [email protected], and [email protected]

Abstract Scaling of the on-chip feature size and power supplyvoltage have significantly reduced the noise margins of anintegrated circuit and have aggravated the effects of processand enviromental variations. These effects can introduce delayvariations on the signals within a circuit, possibly causing aviolation of the timing constraints in a clocked register thatcan lead to system malfunctioning. The effects of parametervariations on the timing characteristics of adder structures areinvestigated in this paper. The sensitivity of the critical delay of

sum and carry signals under variations in power supply voltage,temperature, and gate oxide thickness is demonstrated for fourdifferent adder architectures.

I. INTRODUCTION

The dominant characteristic in the evolution of integrated

circuits has been the scaling of the on-chip feature size. This

trend has produced phenomenal improvements in circuit func-

tionality and system performance by increasing the number of

transistors on-chip as well as the transistor switching speed.

However, with shrinking feature sizes the sensitivity of the

circuit elements to imperfections in the manufacturing process

is aggravated [1]. Furthermore, as the power supply voltage is

reduced to decrease the power dissipation, the driving strengthof transistors is weakened [2]. Therefore the propagation delay

of a signal can be significantly affected by variations in

enviromental parameters and on-chip noise [3], [4]. These

effects can introduce variations in signal delay and cause a

violation of the tight timing constraints at a register, especially

at the most critical data paths within a system [5].

One of the most critical functional blocks within a syn-

chronous integrated circuit is the Arithmetic Logic Unit

(ALU). The basic component of an ALU is the adder circuit

which in many applications determines the overall speed of

a system. Therefore, the effects of process and enviromental

parameter variations on signals propagating along an adder

structure can cause a violation of the timing constraints,resulting in a system malfunction. The delay of a critical

path within an adder and the amount of delay variations is

determined by the adder architecture utilized in a particular

implementation.

In this paper the effects of process and environmental pa-

rameter variations on the delay of different adder architectures

are investigated. The sensitivity of the sum and carry signal

delays is evaluated for four different adder architectures. The

adder architectures considered in this paper are introduced in

Section II. The effects of variations in power supply voltage,

temperature, and gate oxide thickness upon the different adder

implementations are discussed in Section III. Finally some

conclusions are presented in Section IV.

I I . ADDER ARCHITECTURES

Addition of binary numbers is implemented in a bitwise

approach. At each bit position the sum value can be determinedbased upon the corresponding bit values of the operands and

the incoming carry value from the previous position. Therefore

the delay of an addition operation is determined by the total

number of bits in the operands since the incoming carry value

should be propagated from the least significant bit position to

the highest one. In order to decrease the total addition delay

different carry propagation techniques have been proposed at

both the logical and circuit level.

The four adder architectures considered in this paper are

introduced in this section. The operand length for each adder

is 16 bits and the different architectures are implemented

in

technology with 1.8 Volts nominal power supply

voltage. The delay of the sum and carry values at the mostsignificant bits are determined using Hspice simulations and

are listed in Table I.

TABLE I

SUM AND CARRY DELAYS AT NOMINAL PARAMETER VALUES

Adder Sum propagation Carry propagationArchitecture delay delay

Ripple Carry Adder 2234 ps 2158 psCarry Select Adder 1745 ps 1731 psSquare Root Adder 1438 ps 1264 ps

Carry Lookahead Adder 571 ps 135 ps

The adder designs listed in Table I are the Ripple Carry

Adder, the Carry Select Adder, the Square Root Adder, and

the Carry Lookahead Adder. These designs are presented in

the following sections.

A. Ripple Carry Adder

The Ripple Carry Adder (RCA) [6] is the adder architecture

that is implemented directly from of the addition logic. The

sum at each bit position is determined by the corresponding

bit values of the operands and the incoming bit value. The

addition is completed once the carry value propagates along


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positions can be calculated using the carry propagate and carry

generate signals in the carry lookahead mirror logic structure

shown in Figure 4(b).

A 4-bit implementation of a Carry Lookahead Adder is

illustrated in Figure 5. Four mirror structures of different sizes

are utilized to determine the incoming carry values at each bit

position. All the carry values are calculated in parallel after the

carry propagate and carry generate signals become available.

Therefore the ripple effect of the carry is eliminated. Once the

carry values are determined, the sum values at each position

are calculated within the corresponding PFA structures. In

addition the group-generate and group-propagate signals are

produced by the carry lookahead logic as shown in Figure 5.

PFA

A0 B0

P0G0

PFA

A1 B1

P1G1

PFA

A2 B2

P2G2

PFA

A3 B3

P3G3

CIN

C1 C2 C3

COUT

GroupGenerate

C0

Sum0 Sum1 Sum2 Sum3

Carry Lookahead Logic

GroupPropagate

Fig. 5. 4-Bit Carry Lookahead Adder

The group-generate and group-propagate output signals are

utilized to implement a 16-bit Carry Lookahead adder by

adding one more level of hierarchy as illustrated in Figure6. The carry lookahead logic shown in Figure 6 is utilized to

produce the incoming carry values at bit positions 4, 8, and

12. The critical paths of the 16-bit Carry Lookahead Adder are

illustrated in Figure 6 with the grey arrows. The performance

enhancement achieved by the implementation of the Carry

4bit

CLA

A0-3 B0-3

P0G0

CIN

C0

S0-3

4bit

CLA

A4-7 B4-7

S4-7

4bit

CLA

A8-11 B8-11

S8-11

4bit

CLA

A12-15 B12-15

S12-15

P1G1 P2G2 P3G3

C3 C7 C11

GroupGenerate

GroupPropagate

Carry Lookahead Logic

C15

Fig. 6. 16-Bit Carry Lookahead Adder

Lookahead Adder is listed in Table I. Furthermore, notice

in Figure 6 that the final carry value at the most significant

bit position is determined at the highest hierarchical level.

Therefore it is produced much faster compared to the final

sum value at the same position, as listed in Table I. For the

calculation of the final sum value, the incoming carry value

at position 12 is required within a lower level of the adder

hierarchy, therefore increasing the delay of the sum signal.

III. PARAMETER VARIATION EFFECTS

The effects of process and enviromental parameter varia-

tions on the adder architectures presented in Section II are in-

vestigated in this section. In particular, the effects of variations

in power supply voltage ( ! " " ), temperature (% &

(

), and gate

oxide thickness (01 3

) on the sum and carry signals at the most

significant bit positions of each adder are demonstrated. The

effects of ! " " variations are discussed in section III-A. The

effects of variations in temperature are presented in section

III-B and the variations in gate oxide thickness are discussed

in section III-C.

A. Variations in power supply voltage

In high performance synchronous integrated circuits, effects

such as the 45

voltage drop and 67 9

7@

noise can affect the

voltage level at the power supply [10]. Furthermore, power

saving mechanisms such as clock gating and system standby

that control the switching activity of large circuit blocks within

an IC may also affect the power supply voltage level. The

effects of ! " " variations on the delay of the different adder

architectures are demonstrated in this section.

The effect in adder delay is evaluated for a drop in the power

supply voltage of 33% below of the nominal value of 1.8 V.

The result of the voltage drop on the sum output delay at the

most significant bit location for the four adder architectures is

illustrated in Figure 7. It is shown that the sum delay of the

Carry Select Adder is the most sensitive to ! " " variations.

Alternatively, the Square Root Adder is the most robust design

under a power supply drop.

0%

10%

20%

30%

40%

50%

60%

70%

Nominal

VDD6% 11% 17% 22% 28% 33%

Ripple Carry Adder

Carry Select Adder

Square Root Adder

Carry Look Ahead Adder

Sum

DelayVariation(%)

Power Supply Drop

Fig. 7. Percent increase in sum delay due to C D D drop


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In addition the effects of variations in the power supply

voltage on the delay of the carry signal are evaluated and the

results are illustrated in Figure 8. It is shown in Figure 8 that

the increase in carry delay is similar to the increase in the

sum signal delay for the RCA, CSA, and SRA architectures.

However, for the Carry Lookahead Adder, the increase in

the delay of the carry signal is larger than the increase in

sum delay. This is due to the long transistor stacks at the

carry lookahead mirror logic blocks utilized in the CLA. As

the power supply voltage drops, the driving strength of the

stacked transistors is farther reduced compared with the rest

of the transistors in the adder structure. Therefore, the percent

increase in the carry signal is higher than the corresponding

increase in the sum delay. However, the carry signal is still

faster than the sum signal. For the lowest level of ! " " drop,

at 33% below the nominal value, the delay of the carry signal

is 256 ps (90% increase) and the delay of the sum signal is

902 ps (58% increase).

CarryDelayVariation(%)

Power Supply Drop

0%

10%

20%

30%

40%

50%

60%

70%

80%90%

100%

Nominal

VDD6% 11% 17% 22% 28% 33%

Ripple Carry Adder

Carry Select Adder

Square Root Adder


Fig. 8. Percent increase in carry delay due to C D D drop

B. Temperature Variations

With increasing die area, circuit density, and on-chip power

dissipation the variation of temperature across an integrated

circuit becomes significant. The operating temperature of a

circuit element depends upon the proximity to a hot spot

within a die. Therefore, the effects of temperature on circuit

performance are non-uniform across a die. The effects of

temperature variations on the delay of the sum and carry

signals along the different adder designs are investigated in

this section.

Variations in the operating temperature within the range ofF

G

1

C to

1

C are considered for the four adder architectures.

The effect of temperature variations on the delay of the sum

signal at the most siginificant bit is illustrated in Figure 9.

As shown in Figure 9, variations in temperature have larger

effect on the delay of the Ripple Carry Adder. Furthermore,

by comparing Figures 9 and 7, it is shown that the percent

increase in adder delay caused by power supply variations is

significantly larger than the percent increase on the adder delay

due to the effect of temperature variations.

Sum

DelayVariation(%)

Temperature (oC)

0%

2%

4%

6%

8%

10%

12%

27 40 60 80 100

Ripple Carry Adder

Carry Select Adder

Square Root Adder


Fig. 9. Percent increase in sum delay due to temperature variations

In addition, the effect of temperature variations in the delay

of the carry signal are investigated and the results are shown

in Figure 10. It is shown in Figure 10 that for the RCA,

CSA, and SRA architectures the delay of the carry signal is

increased at the same percent as the sum signal. Alternatively,in the Carry Lookahead Adder the percent increase in the

delay of the carry signal is higher than the corresponding

increase in the delay of the sum signal. Therefore, the effect

of temperature variations is larger upon the stacked transistor

structures utilized in the carry lookahead mirror logic blocks

than the rest of the transistors in the adder circuit.

CarryDelayVariation(%)

Temperature (oC)

0%

2%

4%

6%

8%

10%

12%

14%

16%

18%

27 40 60 80 100

Ripple Carry Adder

Carry Select Adder

Square Root Adder


Fig. 10. Percent increase in carry delay due to temperature variations

C. Gate Oxide Thickness Variations

As the on-chip feature size is decreased the effects ofvariations in the manufacturing process are aggravated. One of

the device parameters that is susceptible to imperfections in the

manufacturing process is the gate oxide thickness ( 0 13

) with a

nominal value below 20 angstroms for the current technology

nodes [11]. The slightest variation in the gate oxide deposition

process can create a significant variation in 0 13

. In this section

the effects of 01

3

variation within 20% of the nominal 01

3

value on the delay of the different adder architectures are

demonstrated.


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The effect of 01 3

variations on the delay of the sum signal

for theQ four adder designs is illustrated in Figure 11. It is

shown that 01 3

variations have significantly lower effect on

adder delay compared with variations in power supply voltage

and temperature. A RF

T

variation in gate oxide thickness

causes a maximum variation in the sum delay within the RU

T

range. As shown in Figure 11 the most sensitive design to0 1 3

variations is the Square Root Adder.

Sum

DelayVariation(%)

Gate Oxide Thickness Variation (%)

-6%

-4%

-2%

0

2%

4%

6%

8%

-20 -15 -10 -5 0 5 10 15 20

Ripple Carry Adder

Carry Select Adder

Square Root Adder


Fig. 11. Percent variation in sum delay due to W X ` variations

Furthermore the effect of variations in the gate oxide

thickness on the carry delay of the adders is evaluated and

the results are illustrated in Figure 12. It is shown that the

percent variation in the carry delay in the Carry Lookahead

adder is higher compared with the variation in the delay of

the sum signal, due to the stacked transistor structures in the

carry lookahead mirror logic block.

CarryDelayVariation(%

)

Gate Oxide Thickness Variation (%)

-6%

-4%

-2%

0

2%

4%

6%

8%10%

-20 -15 -10 -5 0 5 10 15 20

Ripple Carry Adder

Carry Select Adder

Square Root Adder


Fig. 12. Percent variation in carry delay due toW

X`

variations

IV. CONCLUSIONS

The effects of variations in power supply voltage, temper-

ature, and gate oxide thickness on the critical delays of the

sum and carry signals within four different adder architec-

tures are demonstrated in this paper. It is shown that power

supply variations have the largest effects on adder delay. The

variations demonstrated in the delay of the sum and carry

signals are similar for the Ripple Carry Adder, Carry Select

Adder, and Square Root Adder under the same parameter

variation effects. Alternatively in the Carry Lookahead Adder,

parameter variations have a greater effect on the delay of

the carry signal compared with the variations in the sum

signal delay due to the long stacked transistor structures

utilized within the carry lookahead mirror logic. Therefore, the

Carry Lookahead Adder provides an enhancement in addition

performance albeit an increase in sensitivity on the effects of

process and enviromental parameter variations.

REFERENCES

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[6] N. H. Weste and D. Harris, CMOS VLSI Design: A Circuits and SystemsPerspective, 3rd ed. Boston: Addison-Wesley, May 2004.

[7] O. J. Bedrij, Carry-select adder, IRE Transactions on ElectronicComputers, vol. EC-9, pp. 226231, 1960.

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