Technical Report

High Speed CMOS A/D Converter Circuit forRadio Frequency Signal

Kyusun Choi

Computer Science and Engineering DepartmentThe Pennsylvania State University

Project Goals

1. High speed circuit and layout design

2. Prototype chip fabrication 0.25um and 0.18um CMOS

3. Test and evaluate, explore and improve

Core development and silicon test of6 and 8 bit TIQ based flash ADC

Project Milestones

1. 1st Chip design, 0.25um 12/01/20002. Chip fabrication 02/05/20013. Chip testing 04/04/2001 1st report4. 2nd chip design, 0.18um 07/10/2001 2nd report, chip5. Chip fabrication 10/08/20016. Chip testing 11/09/2001 3rd report7. Project ending 12/31/2001 Chip8. Project presentation 02/15/2002 Final report

Project Feature

1. High speed ADC, 1 GSPS

2. RF applications

3. SOC applications, digital CMOS

4. Future-ready, < 0.10um, < 1.0V

TIQ flash ADC

gain booste

rgain

booster

gain booste

r

gain booste

rThermometer

code tobinary encoder

Vn

V3

V2

V1

Vin

D1

D2

D3

Dk

gain boostercircuit

Other flash ADC

Thermometer code to

binary encoder

–

+

Vin

D1D2D3

Dk

V1

V2

V3

–

+

–

+

–

+

Vn

V1

V2

V3

Vn

R

R

R

R

Vref

Resistor laddercircuit

TIQ comparator

Vr is provided by a voltage references source,External to the voltage comparator

Vm is an internal parameter of an inverter,fixed by the transistor sizes

Vr

_

+

Vin

VinVinVr Vm

Vout Vout

Vout Vin

Vout

Vm

DIFFERENTIAL INPUTVOLTAGE COMPARATOR INVERTER

TIQ comparator

• High speed• Less area• No resistor ladder and reference voltages• No capacitor switching• Future ready

• Scale down• Low supply voltage• Standard digital logic technology• Ideal for SOC

Prototype Test Results

1st prototype chip (0.25um), six ADCs on chip

ADCs Precision Delay Power

6bit0.25 4 bits 3.799 ns 109.38

6bit1.00 6 bits 21.404 ns 35.25

8bit0.25 5 bits 7.249 ns 170.50

8bit0.50 7 bits 18.612 ns 121.25

9bit0.50 6 bits 27.762 ns 200.375

9bit1.00 8 bits 83.595 ns 179.625

Prototype Test Results

2nd prototype chip (0.18um), ten ADCs on chip

ADCs Precision Delay Power

6bit1.00FAT 6 bit 2.65 ns 27.0 mW

6bit1.00ROM 6 bit 4.50 ns 21.6 mW

6bit0.50ROM 3 bit 2.97 ns 36.0 mW

6bit0.18ROM 3 bit 3.35 ns 77.4 mW

8bit1.0ROM 6 bit 15.45 ns 64.8 mW

8bit0.50ROM 5 bit 6.65 ns 75.6 mW

9bit1.50ROM 5 bit 29.20 ns 64.8 mW

9bit1.00ROM 5 bit 36.50 ns 111.6 mW

Prototype Test Results

ADC: 6 bit 1.00um, ROM, 0.18um prototype chip

Input: 100 KHz Saw wave

Prototype Test Results

ADC: 6 bit 1.00um, FAT, 0.18um prototype chip

Input: 100 KHz Saw wave

Prototype Test Results

ADC: 9 bit 1.00um, ROM, 0.25um prototype chip

Input: 100 KHz Saw wave

Prototype Test Results

ADC: 6 bit 1.00um, FAT, 0.18um prototype chipInput: DC

DNL = 0.36 LSB INL = 1.36 LSB

Prototype Test Results

ADC: 6 bit 1.00um, FAT, 0.18um prototype chipInput: 80KHz sign wave, f_sample = 10 MHz

SNR = 23.40 dBSNDR = 21.83 dBSFDR = 9.13 dBENOB = 3.33 bits

Prototype Test Results

ADC: ideal 6 bitInput: 1MHz sign wave, f_sample = 200 MHz

SNR = 37.78 dBSNDR = 36.56 dBSFDR = 37.86 dBENOB = 5.78 bits

Summary

•High speed ADC for RF application

• ADC core - 6 and 8 bit design

• prototype chips (silicon test)

• 0.25 m and 0.18 m

• CMOS digital logic technology

• SOC beyond 0.10um & 1.00V

Innovation/enhancement challenges

• 1 GSPS with digital CMOS• Custom layout generation and modeling CAD tool• 8bit and 10bit ADC• Low power• Low noise• Dynamic calibration

• Offset• Gain• Temperature• Power supply voltage• Process parameter variation

Summary

•High speed ADC for RF application

• ADC core - 6 and 8 bit design

• prototype chips (silicon test)

• 0.25 m and 0.18 m

• CMOS digital logic technology

• SOC beyond 0.10um & 1.00V

Chip1 6bit 1.00um, A1:20KH Sine Input A2: Vdd, w/o R on Probs

Chip1 6bit 1.00um, A1: 20KH Sine Input A2: Vddw/ 4.7K Ohm on Probs

Chip1 6bit 1.00um, A1: 20KH Sine Input A2: Vddw/ R on Probs

1st Prototype Chip Test Board

2nd Prototype Chip Test Board