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SCAN & DFT BasicsPosted on December 11, 2012 by Gayathri
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Here I am trying to explain the very basic concepts ofwhat is DFT, Codec and Boundary Scan.
Basically scan chain is built to find out the stuck at faultsin the circuit. Our design consists of so many sequentiallogic and combinational logic. For scan controllability, weconvert all flops as scan flops. The basic structure of ascan flip-flop is as below.
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When scan enable is high, SD is selected and when lowD is selected. in the scan chain Q output of a flop isconnected to SD of the next flop.
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Now take the case of combo logic in the design. The inputto each gate will be either input to the design or it will befrom Q output of a flip flop.Now we give a pattern whichwill have control on some inputs of combo gates. This isgiven through the scan chain by shifting. Clock is suppliedand scan enable is made high and the full design worksas serial in shift register. Imagine the situation where fullpattern is shifted through the scan chain. Scan enable ishigh at this time. All combination gates also gets theintended values at the inputs and it got propagated tooutputs too.And the outputs from these combinationalgates would have anyway come till some flip-flop’s D pin.
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ie, functional input.
Then make scaneable low, so that D gets selected in allflip-flops. Give one clock pulse, all D’s get propagated toQ. This is the scan capture mode.
Now again think of scan chain. Make scan enable high.And start giving clock pulses. Q of flip-flops will come toSD of next flip-flop. Thus you start getting the shiftedvalues at the output like a serial out shift register.So thesepattern which you got outside after so many clock cyclescan be compared against the expected output pattern. If itis as expected no fault in the design. If some differenceyou can identify the stuck at fault as per the position of themismatch in the output pattern. Thus you can trace thestuck at faults in your design.
Test/Scan Timing analysis.
Scan shift mode covers the shift paths when scan enableis high and scan capture covers the functional pathswhen scan enable is low.
BOUNDARY SCAN
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Boundary scan checks the stuck at faults at the boundaryof the chip. ie, IO paths. Boundary scan flops areconnected in a chain. At first scan enable is made lowand inputs are fed for the registers 1, 2 and 3. Then scanenable is made high. Two values which needs to getshifted out from the output registers are fed through TDI.Maintain the scan enable as high for 5 clock cycles. sothat the values are shifted out. Inputs are checked throughthe outputs of TDO and the values fed through TDI shouldbe shifted out through the output ports.
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Boundary scan shift
Scan enable is high. Timing paths covered are TDI toreg1, registers in the scan chain, last reg to TDO
Boundary Scan Capture
Scan enable is low. Timing paths covered are all inputs toboundary scan input registers, all boundary scan outputregisters to output ports.
In boundary scan the data and clock is shifted in oppositedirections. This is to avoid hold violation. When dataarrives, capture clock edge have already passed thesame edge. ie, Launch flip-flop is having more clock delaythan the capture flip-flop so that hold timing is easily met
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CODEC BASICS
Codec (LBIST) is a compressor decompressor logic(XOR – MUX) which DFTMAX inserts which helps greatlyto reduce tester time.
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Suppose say 16,000 registers are there in a partition. Wehave 16 scan chains too. Then one scan chain will behaving 1000 registers each. So total shift cycle will be1000. So if codec is present which will convert 16 scanchains to 160, then each scan chain will be having only100 registers and the shift cycle is reduced to 100 cycles.
Some more on DFT in my blog
“ CODEC Insertion Flow using Synopsys DFTCompiler“
“Scan Insertion/Stitching Basics.”
This entry was posted in DFT, Technology and tagged DFT, InterviewQuestions, Static Timing Analysis by Gayathri. Bookmark thepermalink.
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VIpul982 • 6 months ago
About Gayathri
I am an experienced hand in semiconductorindustry in VLSI chip implementation. I am anElectronics and Communication Engineeringgraduate, I am into the VLSI domain for morethan a decade. My passion always was to impartknowledge and in the process gain more. I amtrying to add flavours of Technology and thoughtsto these blogs.View all posts by Gayathri →
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ReplyVery nice, well keep me updated in DFT as i am new to the industry. Thanks :)
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