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Nurul Syahirah Ishak 002452
Nadiah Mohd Zaki 002457
2010
[LOW NOISE AMPLIFIER ADS
DESIGN]H63TCE ASSIGNMENT
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Objective
To design a low noise amplifier that operates between 890MHz to
910MHz by using an
Infineon RF transistor BFP640. The requirement of the designed
transistor is:
Noise Figure, NF = less than 1.3dB
Gain = 24 dB 0.5
S22 = better than -15dB
Choice ofBias Condition
The bias condition value is chosen based on graph in BFP640 data
sheet below:
As shown in figure above, the chosen amplifier operating
frequency is 0.9GHz at the gain of
24dB. The correspondent value of Ic is 5mA and The chosen Vce
value is 3V.
By using the marker, the bias condition is:
Figure 1 Bias condition
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From the figure above, it shown that the value of IB and VB are
and. Then, the
dc analysis is done by using the value obtained. The DC bias
schematic diagram is shown
below.
Figure 3 S Parameter Schematic Diagram
The calculation for obtaining the values of resistance is shown
below. There are two
assumption were made; First, the value for Vcc is 4.5V,
Secondly, assume that .
Then, the simulation is done to obtain the normalized impedance
value as shown in the
Figure 4 below.
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Figure 4 Result ofS-Parameter Simulation
The normalized impedance values are chosen in the region of
Noise Figure circle less than
1.3dB. The representation of the amplifier illustration with the
input and output matching
network is shown below.
To determine the perfect matching network (input), the value of
and
are mapping into the ZY smith chart (Refer to Appendix 1). The
step is repeated for
output matching network (Refer to Appendix 2).
Then, after determining the suitable matching network, the
S-Parameter schematic is being
added with the matching network. It is then being simulated in
the AmpDesign. The design
is shown below.
AmpInput Matching
Network
Output Matching
Network
Figure 5 Basic illustration for Amplifier Design
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Figure 6 AmpDesign
Sch
ematic Diagram
The simulation result is shown below;
Figure 7 Result from the AmpDesign simulation
From the result above, it shown that the gain is 24.123dB, noise
figure, NF = 0.758 and S 22
= -30.450 which meet the requirement.
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Then, the design is being implemented with real component value,
the DC Block and the DC
Feed is being replaced with negligible capacitor and inductor
value. The schematic design is
shown below.
Figure 8 Schematic Design with real component
In practical, the components value are limited to certain amount
of number only.
Therefore, the total value of inductor and capacitor is
determined by summing up the real
number of capacitor or inductor value until it meet up the
specification that has been made
in theoretical part previously. The inductors are placed in
series and the capacitors is placed
in parallel. However, during the summation procedure, it would
be better to choose the less
number of components so that the noise would be reduced as
well.
The DC block is a coaxial component that offering the minimum
interference to RF
signal and prevent the flow of DC frequencies. DC feed is an
inductance and have an
infinite inductance.
The simulation result is shown below;
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Figure 9 Result from the simulationofschematic design with the
real components
As shown from the result above, the gain have 0.82% of error
compared to the gain value
from the s-parameter. The difference in the result of the
simulation of the schematic
diagram with the real components are caused by the changes in
the components value as
the resistors, capacitors and inductors.
Conclusion
As a conclusion, the final result do meet the question
requirement as the gain is
23.883dB which approximately equal to 24dB, Noise Figure is
0.930 which less than 1.3dB
and S22 is -17.622 which better than -15dB.
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Appendix 1
Figure 1.1 Matching Network for input
Calculation of Matching Network Z in and ZS
Point Z Y
IN 1 + j0 1 + j0
S 2.2 + j0.3 0.46 j0.08
A 1 + j1.1 0.46 j0.5
ZA Zin = (1 + j1.1) (1 + j0)
= j1.1
L = 1.1(50)
L = 9.73nH
Ys - YA = (0.46 j0.08) (0.46 j0.5)
= j0.42
C = 0.42/(50)
C = 1.49pF
A
Zin
Zs
R Circle
G Circle
9.73nH
1.06pF
ZSZin
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Appendix 2
Figure 10.1 Matching Network for output
Calculation of Matching Network Zout and ZL
Point Z Y
OUT 1 + j0 1 + j0
L 1.2+ j1.6 0.3 j0.4
A 1 + j1.5 0.3 - j0.46
ZA Zout = (1 + j1.5) (1 + j0)
= j1.5
L = 1.5(50)
L = 13.26 nH
YL - YA = (0.3 j0.4) (0.3 - j0.46)
= j0.06
C = 0.06/ (50)
C = 0.212 pF
A
Zout
ZL
R Circle
G Circle
0.212pF
13.26nH
Zout ZL
