TC8 Ly Pres User

8/10/2019 TC8 Ly Pres User

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Agenda

Introduction to Alteras designs and challenges

Alteras approach to LVS debugging

Powerful IC Validator LVS capabilities

Summary


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Introduction to Altera Designs

Intro to what sort of designs Alteramakes

28nm and 20nm process technologies

Billion transistors

leading design DSP, Transceiver, signalintegrity

Design for communication chips,

network signal processing

Advanced FPGA Design


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Agenda




Summary


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Alteras Approach to LVS Debugging

Using IC Validator

1. Review extraction errors FIRST!

2. Check.LAYOUT_ERRORSfor:

a. Device extraction errors

Shorts crossing the Source / Drain of

a transistor

Runset issues

b. Text shorts & opens

c. Soft_check violations

d. ERC checks

Picture to explain

Soft_check violations?


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Agenda




Summary


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Suggested Fix for Connection Error

explain problem

explain suggested

fix

When error occurs, it provides side by side comparison of theconnection between netlist and layout. It groups up all devices that

belong to the same connection issue. It also provides the suggested

right connection that in certain way enable the pin point of the real

issue. Example:


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Suggested Fix for Connection Error

explain problem

explain suggested

fix

Example:


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This runtime status provides a contrast of what was provided vs what was

really used. This enable users to identify early symptoms of possible causes tothe LVS problem, where frequently the LVS error was not cause by incorrect

construction, but by incorrect info supplied,

Example:

Helpful Display of LVS Status


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Account Files

This provides the final extracted device count for each

hierarchy, and its cumulative count from subcells.

It provides another level of debugging especially when

device appear in other hierarchy level.

Example:


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Customizable COMPARE Settings

ICV allows us to changethe severity level of an

issue: WARNING or

ERROR

This allows a behavioral

matching between the

tools to the design style,

and let user make the

judgment on what really

is important to look at,and still getting a clear

digital result.


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Netlist Partition for Each Cell

ICV creates netlists for individual cells These are used in comparison to ease debugging.

Example:


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Easy LVS Compare

Netlist comparison Performs a bottom-up comparison of quick cell pairings

Makes it easy to pin-point which block is causing an LVS mismatch

by isolating and focusing only on data that is really need to looked

at.

Result files and debug

Net and instance cross references

Results files in

Topcell.LVS_Error

Run_details/topcell_lvs.log

Run_details/compare/

layout_equiv_cell

sum.*

xref.*


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Other Helpful LVS Options

in IC Validator

Options to Delete Data in Hierarchy Removes Chip/Logo graffiti cells

Reduces extraction time

Options to Delete Data in Compare

Can delete physical cells Extraction errors will be reported

Isolate cells that are clean from other levels

during debugging.

Black Box option

Use when a sub-block is not ready for LVS

Only check port connectivity

Saves time since lower cells are not

processed


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IC Validator Graphical DebuggingVUE Short Finder

Enables the user to isolate the shorts Hierarchical as well as top level shorts

Investigate multiple shorts in single run

Flexible highlighting options

Net annotation for path polygons

Path reductionmodifying and filtering

Net changes log


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Display Full Path Highlight the entire shorted path

Includes entire hierarchy

Net annotation

Highlight individualpolygons

VCCEH

VCCER



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Short Finder enables the user to walk through each polygons in the shorted

path

path is processed polygon-by-polygon.

Ultimately, the user finds the offending polygon(s).



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Agenda




Summary


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Summary

Numerous designs have been use in ICV- 28nm, 20nm, and 14nm process node

Designs in the range of billion transistors

ICV LVS big benefits

Break down the design debug hierarchy

Runtime improvement

Easy to alter the layout/schematic netlist for debugging

VUE Short Finder

Quick and easy to find shorted path

ICV LVS currently using in all active process node

IC Validator LVS Used Successfully at Altera


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Thank You

Documents

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