Tc7135 4-1_2 Digit Analog-To-digital Converter

3-113TELCOM SEMICONDUCTOR, INC.

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GENERAL DESCRIPTION

The TC7135 4-1/2 digit analog-to-digital converter (ADC)offers 50 ppm (1 part in 20,000) resolution with a maximumnonlinearity error of 1 count. An auto-zero cycle reduces zeroerror to below 10 µV and zero drift to 0.5 µV/°C. Sourceimpedance errors are minimized by a 10 pA maximum inputcurrent. Roll-over error is limited to ±1 count.

By combining the TC7135 with a TC7211A (LCD) orTC7212A (LED) driver, a 4-1/2 digit display DVM or DPM canbe constructed. Overrange and underrange signals supportautomatic range switching and special display blanking/flash-ing applications.

Microprocessor-based measurement systems are sup-ported by BUSY, STROBE, and RUN/HOLD control signals.Remote data acquisition systems with data transfer via UARTsare also possible. The additional control pins and multiplexedBCD outputs make the TC7135 the ideal converter for dis-play or microprocessor-based measurement systems.

TC7135

ORDERING INFORMATION

TemperaturePart No. Package Range

TC7135CBU 64-Pin Plastic 0°C to +70°CFlat Package

TC7135CLI 28-Pin PLCC 0°C to +70°C

TC7135CPI 28-Pin Plastic DIP 0°C to +70°C

TC7135

–5V V

REF INANALOGCOMMON

UR

OR

STROBE

RUN/HOLD

DGND

POL

CLOCK

BUSY

D1

D2

D3

0.1 µF

0.47 µF

1 µFANALOGGROUND

100 kΩ

0.1µFINPUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

+5V

28

27

26

25

24

23

22

21

20

19

TC04

+5V

1/4 CD4030

CLOCK IN

+5V

BP

D

D

D

D

1

2

3

4

4-1/2 DIGIT LCD

SEGMENTDRIVE

5

31

32

33

34

30

29

28

27

TC7211A

SEGOUT

OSC

GND

36 +5V

+5V

1

CD4081

1 1615 1412 5 3 4

7 8 13 1110 9 2 6CD4054A

OPTIONALCAP35

15

120 Hz = 3 READING/SEC

BACKPLANE

B

B

B

B

3

2

1

0

D4

B8

B4

18

17

16

100 kΩ

100 kΩ

6.8 kΩ

1 µF

INT OUT

AZ IN

BUFF OUT

CREFCREF–INPUT

+INPUT

V

D5

B1

B2

+

V+

2,3,46–2637–40

+

–

+5V

FEATURES

Low Roll-Over Error ......................... ±1 Count Max Guaranteed Nonlinearity Error ........ ±1 Count Max Guaranteed Zero Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and

µProcessors Auto-Ranging Supported With Overrange and

Underrange Signals Blinking Display Visually Indicates Overrange

Condition Low Input Current ............................................. 1 pA Low Zero Reading Drift ............................... 2 µV/°C Interfaces to TC7211A (LCD) and TC7212A (LED)

Display Drivers Available in DIP and Surface-Mount Packages

TYPICAL 4-1/2 DIGIT DVM WITH LCD

4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER

TC7135-10 11/6/96

3-114 TELCOM SEMICONDUCTOR, INC.

ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 120 kHz, V+ = +5V, V– = –5V (Figure 1)

Symbol Parameter Test Conditions Min Typ Max Unit

AnalogDisplay Reading With Notes 2 and 3 –0.0000 ±0.0000 +0.0000 DisplayZero Volt Input Reading

TCZ Zero Reading Temperature VIN = 0V — 0.5 2 µV/°CCoefficient Note 4

TCFS Full-Scale Temperature VIN = 2V — — 5 ppm/°CCoefficient Notes 4 and 5

NL Nonlinearity Error Note 6 — 0.5 1 Count

DNL Differential Linearity Error Note 6 — 0.01 — LSB

Display Reading in VIN = VREF +0.9996 +0.9999 +1.0000 DisplayRatiometric Operation Note 2 Reading

±FSE ± Full-Scale Symmetry –VIN = +VIN — 0.5 1 CountError (Roll-Over Error) Note 7

IIN Input Leakage Current Note 3 — 1 10 pA

VN Noise Peak-to-Peak Value Not — 15 — µVP-PExceeded 95% of Time

DigitalIIL Input Low Current VIN = 0V — 10 100 µA

IIH Input High Current VIN = +5V — 0.08 10 µA

VOL Output Low Voltage IOL = 1.6 mA — 0.2 0.4 V

VOH Output High VoltageB1, B2, B4, B8, D1–D5 IOH = 1 mA 2.4 4.4 5 VBusy, Polarity, Overrange, IOH = 10 µA 4.9 4.99 5 V Underrange, Strobe

fCLK Clock Frequency Note 8 0 120 1200 kHz

Power SupplyV+ Positive Supply Voltage 4 5 6 V

V– Negative Supply Voltage –3 –5 –8 V

I+ Positive Supply Current fCLK = 0 Hz — 1 3 mA

I– Negative Supply Current fCLK = 0 Hz — 0.7 3 mA

PD Power Dissipation fCLK = 0 Hz — 8.5 30 mW

NOTES: 1. Limit input current to under 100µA if inputvoltages exceed supply voltage.

2. Full-scale voltage = 2V.3. VIN = 0V.4. 0°C ≤ TA ≤ +70°C.

ABSOLUTE MAXIMUM RATINGS* (Note 1)

Positive Supply Voltage ............................................. +6VNegative Supply Voltage .............................................–9VAnalog Input Voltage (Pin 9 or 10) ......... V+ to V– (Note 2)Reference Input Voltage (Pin 2) ........................... V+ to V–

Clock Input Voltage ..............................................0V to V+

Operating Temperature Range .................... 0°C to +70°CStorage Temperature Range ................. –65°C to +160°C

Lead Temperature (Soldering, 10 sec) ................. +300°CPackage Power Dissipation (TA ≤ 70°C)

Plastic DIP ........................................................1.14WPLCC ................................................................1.00WPlastic Flat Package .........................................1.14W

*Static-sensitive device. Unused devices must be stored in conductivematerial to protect them from static discharge and static fields. Stressesabove those listed under "Absolute Maximum Ratings" may cause perma-nent damage to the device. These are stress ratings only and functionaloperation of the device at these or any other conditions above thoseindicated in the operational sections of the specifications is not implied.

5. External reference temperature coefficient less than 0.01 ppm/°C.6. –2V ≤ VIN ≤ +2V. Error of reading from best fit straight line.7. |VIN| = 1.9959.8. Specification related to clock frequency range over which the

TC7135 correctly performs its various functions. Increased errorsresult at higher operating frequencies.

TC7135

4-1/2 DIGITANALOG-TO-DIGITAL CONVERTER


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TC7135CPI(PDIP)

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4 RUN/HOLD

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12

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28

27

26

25

24

23

22

21

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19

18

17

16

15

STROBE

OVERRANGE

B4

D3

D2

D1 (LSD)

BUSY

CLOCK IN

POLARITY

DIGTAL GND

UNDERRANGE

B2

(LSB) B1

(MSD) D5

V+

+INPUT

– INPUT

CREF

CREF

BUFF OUT

AZ IN

INT OUT

ANALOGCOM

REF IN

V–

D4

B8 (MSB)

4

3

2

16

15

14

10

9

8

7

6

5

12

11

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

TC7135CBU(PFP)

(NOTES 1)

NC

INT

OU

T

NC

AZ

IN NC

CR

EF

NC

NC

CR

EF

NC

–IN

PU

T

NC

+IN

PU

T

NC V+

NOTES: 1. NC = No internal connection.

+

–

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20

21

22

23

24

25

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10

9

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6

5

CLOCK IN

RUN/HOLD

TC7135CLI(PLCC)

AZ IN

POLARITY

12 13 14 15 17 18

(MS

D)

D5

(LS

B)

B1

B2

B4

(MS

B)

B8

D4

D3

DIGTAL GND

BUSY

D1 (LSD)

D2

BUFF OUT

REF CAP–

REF CAP+

–INPUT

V+

4 3 2 1 27 2628

INT

OU

TA

NA

LO

GC

OM

RE

F IN

V–

UR

OR

ST

RO

BE

16

+INPUT

32

BU

FF

OU

T

NC

BU

SY

D2

D1

63 61 60 59 58 57 56 55 54 53 52 51 50 4964

NC

NC

NC

NC

NC

ST

RO

BE

RU

N/H

OL

D

DG

ND

PO

L

NC

CL

OC

K IN

62

NC

NC

NC

NC

NC

NC

OVERRANGE

UNDERRANGE

NC

V–

REF IN

ANALOG COM

NC

NC

NC

NC

NC

NC

D5

NC

NC

NC

NC

D3

NC

NC

D4

B8

B4

B2

NC

B1

NC

13

40

41

42

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34

35

36

37

38

39

33

48

47

1

– +

PIN CONFIGURATIONS

TC7135



TC7135


Figure 3A. Internal Analog Switches

Figure 1. Test Circuit

Figure 2. Digital Logic Input

Figure 3D. Reference Voltage Integration Phase

Figure 3C. Input Signal Integration Phase

Figure 3B. System Zero Phase

TC7135

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25

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21

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17

16

15

100 kΩ

ANALOG GND

100 kΩ

SIGNALINPUT

0.1 µF

SET VREF = 1V

V –

REF IN

ANALOG COMMON

INT OUT

AZ IN BUFF OUT

CREFCREF–INPUT

+INPUT

D5 (MSD)

B1 (LSB)

B2

V+

UNDERRANGE

OVERRANGE

STROBE

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

(LSD) D1

D2

D4

(MSB) B8

B4

D3+5V

1 µF

100 kΩ

1 µF 0.47µF

VREF IN

CLOCKINPUT120 kHz

–5V

+

–

+

–+

–

+

–

+IN

INREF

ANALOGCOM

–IN

SWI

SWR

SWZ

SWI SW1

SWZ

SWIZ SWZ

INTEGRATOR

ANALOG INPUT BUFFER

SWRI+SWRI

–

COMPARATOR

TODIGITALSECTION

SWRI+ SWRI

–

RINTCINT

CREF

CSZ

BUFFERLOGICINPUT

V+

+

–+

–

+

–

+IN

INREF

ANALOGCOM

–IN

SWI

SWR

SWZ

SWI SW1

SWZ

SWIZ SWZ

INTEGRATOR

SWITCH CLOSED

SWITCH OPEN

SWRI+SWRI

–

COMPARATOR

TODIGITALSECTION

SWRI+ SWRI

–

ANALOG INPUT BUFFER

RINTCINT

CREF

CSZ

+

–+

–

+

–

+IN

INREF

ANALOGCOM

–IN

SWI

SWR

SWZ

SWI SW1

SWZ

SWIZ SWZ

INTEGRATOR

SWITCH CLOSED

SWITCH OPEN

SWRI+SWRI

–

COMPARATOR

TODIGITALSECTION

SWRI+ SWRI

–

ANALOG INPUT BUFFER

RINTCINT

CREF

CSZ

+

–+

–

+

–

+IN

INREF

ANALOGCOM

–IN

SWI

SWR

SWZ

SWI SW1

SWZ

SWIZ SWZ

INTEGRATOR

SWITCH CLOSED

SWITCH OPEN

SWRI+SWRI

–

COMPARATOR

TODIGITALSECTION

SWRI+ SWRI

–

ANALOG INPUT BUFFER

RINT CINT

CREF

CSZ


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TC7135


GENERAL THEORY OF OPERATION

(All Pin Designations Refer to 28-Pin DIP)

Dual-Slope Conversion Principles

The TC7135 is a dual-slope, integrating analog-to-digital converter. An understanding of the dual-slope con-version technique will aid in following detailed TC7135operational theory.

The conventional dual-slope converter measurementcycle has two distinct phases:

(1) Input signal integration

(2) Reference voltage integration (deintegration)

The input signal being converted is integrated for a fixedtime period, measured by counting clock pulses. An oppo-site polarity constant reference voltage is then integrateduntil the integrator output voltage returns to zero. Thereference integration time is directly proportional to the inputsignal.

In a simple dual-slope converter, a complete conversionrequires the integrator output to "ramp-up" and "ramp-down."

A simple mathematical equation relates the input signal,reference voltage, and integration time:

For a constant VIN:

VIN = VR .

Figure 4. Basic Dual-Slope Converter

Figure 3E. Integrator Output Zero Phase

The dual-slope converter accuracy is unrelated to theintegrating resistor and capacitor values, as long as they arestable during a measurement cycle. Noise immunity is aninherent benefit. Noise spikes are integrated, or averaged,to zero during integration periods. Integrating ADCs areimmune to the large conversion errors that plague succes-sive approximation converters in high-noise environments.(See Figure 4.)

TC7135 Operational Theory

The TC7135 incorporates a system zero phase andintegrator output voltage zero phase to the normal two-phase dual-slope measurement cycle. Reduced systemerrors, fewer calibration steps, and a shorter overrangerecovery time result.

The TC7135 measurement cycle contains four phases:

(1) System zero

(2) Analog input signal integration

(3) Reference voltage integration

(4) Integrator output zero

Internal analog gate status for each phase is shown inTable 1.

tRI

tSI[ ]

where:VR = Reference voltagetSI = Signal integration time (fixed)tRI = Reference voltage integration time (variable).

1 VR tRI

RC RCVIN(t) dt = ,∫

tSI

0

+

–+

–

+

–

+IN

INREF

ANALOGCOM

–IN

SWI

SWR

SWZ

SWI SW1

SWZ

SWIZ SWZ

INTEGRATOR

SWITCH CLOSED

SWITCH OPEN

SWRI+SWRI

–

COMPARATOR

TODIGITALSECTION

SWRI+ SWRI

–

ANALOG INPUT BUFFER

RINTCINT

CREF

CSZ

+

–

REFVOLTAGE

ANALOGINPUT

SIGNAL

+

–

DISPLAY

SWITCHDRIVER

CONTROLLOGIC

INT

EG

RA

TO

RO

UT

PU

T

CLOCK

COUNTER

POLARITY CONTROL

PHASECONTROL

VINVIN

VFULL SCALE1/2 VFULL SCALE

VARIABLEREFERENCEINTEGRATETIME

FIXEDSIGNAL

INTEGRATETIME

INTEGRATORCOMPARATOR

''


TC7135


Table 1. Internal Analog Gate Status

Conversion ReferenceCycle Phase SW I SWR

+ SWR– SWZ SWR SW1 SWIZ Schematic

System Zero Closed Closed Closed 3B

Input Signal Closed 3CIntegration

Reference Voltage Closed* Closed 3DIntegration

Integrator Closed Closed 3EOutput Zero

*NOTE: Assumes a positive polarity input signal. SWR–

would be closed for a negative input signal.

Internal Analog Gate Status

System Zero PhaseDuring this phase, errors due to buffer, integrator, and

comparator offset voltages are compensated for by charg-ing CAZ (auto-zero capacitor) with a compensating errorvoltage. With zero input voltage, the integrator output re-mains at zero.

The external input signal is disconnected from theinternal circuitry by opening the two SWI switches. Theinternal input points connect to analog common. The refer-ence capacitor charges to the reference voltage potentialthrough SWR. A feedback loop, closed around the integratorand comparator, charges the CAZ with a voltage to compen-sate for buffer amplifier, integrator, and comparator offsetvoltages. (See Figure 3B.)

Analog Input Signal Integration PhaseThe TC7135 integrates the differential voltage between

the +INPUT and –INPUT. The differential voltage must bewithin the device's common-mode range; –1V from eithersupply rail, typically.

The input signal polarity is determined at the end of thisphase. (See Figure 3C.)

Reference Voltage Integration PhaseThe previously-charged reference capacitor is con-

nected with the proper polarity to ramp the integratoroutput back to zero. (See Figure 3D.) The digital readingdisplayed is:

Reading = 10,000 .

Integrator Output Zero PhaseThis phase guarantees the integrator output is at 0V

when the system zero phase is entered and that the truesystem offset voltages are compensated for. This phasenormally lasts 100 to 200 clock cycles. If an overrangecondition exists, the phase is extended to 6200 clock cycles.(See Figure 3E.)

Differential InputVREF

Analog Section Functional Description

Differential InputsThe TC7135 operates with differential voltages (+IN-

PUT, pin 10 and –INPUT, pin 9) within the input amplifiercommon-mode range which extends from 1V below thepositive supply to 1V above the negative supply. Within thiscommon-mode voltage range, an 86 dB common-moderejection ratio is typical.

The integrator output also follows the common-modevoltage and must not be allowed to saturate. A worst-casecondition exists, for example, when a large positive com-mon-mode voltage with a near full-scale negative differentialinput voltage is applied. The negative input signal drives theintegrator positive when most of its swing has been used upby the positive common-mode voltage. For these criticalapplications, the integrator swing can be reduced to lessthan the recommended 4V full-scale swing, with some lossof accuracy. The integrator output can swing within 0.3V ofeither supply without loss of linearity.

Analog CommonANALOG COMMON (pin 3) is used as the –INPUT

return during the auto-zero and deintegrate phases. If– INPUT is different from analog common, a common-modevoltage exists in the system. This signal is rejected by theexcellent CMRR of the converter. In most applications,– INPUT will be set at a fixed known voltage (power supplycommon, for instance). In this application, analog commonshould be tied to the same point, thus removing the common-mode voltage from the converter. The reference voltage isreferenced to analog common.

Reference VoltageThe reference voltage input (REF IN, pin 2) must be a

positive voltage with respect to analog common. Two refer-ence voltage circuits are shown in Figure 5.

[ ]


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TC7135


Digital Section Functional Description

The major digital subsystems within the TC7135 areillustrated in Figure 6, with timing relationships shown inFigure 7. The multiplexed BCD output data can be displayedon an LCD with the TC7211A.

The digital section is best described through a discus-sion of the control signals and data outputs.

RUN/HOLD InputWhen left open, the RUN/HOLD (R/H) input (pin 25)

assumes a logic "1" level. With R/H = 1, the TC7135performs conversions continuously, with a new measure-ment cycle beginning every 40,002 clock pulses.

When R/H changes to logic "0," the measurement cyclein progress will be completed, and data held and displayed,as long as the logic "0" condition exists.

A positive pulse (>300nsec) at R/H initiates a newmeasurement cycle. The measurement cycle in progresswhen R/H initially assumed logic "0" must be completedbefore the positive pulse can be recognized as a singleconversion run command.

The new measurement cycle begins with a 10,001-count auto-zero phase. At the end of this phase, the busysignal goes high.

Figure 6. Digital Section Functional Diagram

Figure 5. Using an External Reference Voltage

LATCH LATCH LATCH LATCH LATCH

COUNTERS

CONTROL LOGIC

MULTIPLEXER

POLARITY D5 D4 D3 D2 D1

13 B114 B2

15 B416 B8

POLARITYFF

MSB DIGIT DRIVE SIGNAL LSB

DATAOUTPUT

24 22 25 27 28 26 21

DIGITALGND

CLOCKIN

RUN/HOLD

OVER–RANGE

STROBE BUSYUNDER–RANGE

ZEROCROSSDETECT

FROMANALOGSECTION

20k

6.8 k

Ω

ΩV+

1.25V REF

TC04

V+

REFIN 2.5VREF

V+

IREF

TC7135

V–

V+

ANALOGGROUND

ANALOGCOMMON

REFIN

TC7135

ANALOGCOMMON

TC05


TC7135


Figure 8. Strobe Signal Pulses Low Five Times per Conversion

Figure 7. Timing Diagrams for Outputs

The active-low STROBE pulses aid BCD data transferto UARTs, microprocessors, and external latches. (SeeApplication Note AN-16.)

BUSY OutputAt the beginning of the signal-integration phase, BUSY

(pin 21) goes high and remains high until the first clock pulseafter the integrator zero crossing. BUSY returns to logic "0"after the measurement cycle ends in an overrange condi-tion. The internal display latches are loaded during the firstclock pulse after BUSY and are latched at the clock pulseend. The BUSY signal does not go high at the beginning ofthe measurement cycle, which starts with the auto-zerophase.

OVERRANGE OutputIf the input signal causes the reference voltage integra-

tion time to exceed 20,000 clock pulses, the OVERRANGEoutput (pin 27) is set to logic "1." The OVERRANGE outputregister is set when BUSY goes low and reset at thebeginning of the next reference-integration phase.

UNDERRANGE OutputIf the output count is 9% of full scale or less (≤1800

counts), the UNDERRANGE output (pin 28) register bit isset at the end of BUSY. The bit is set low at the next signal-integration phase.

STROBE OutputDuring the measurement cycle, the STROBE output

(pin 26) control line is pulsed low five times. The five lowpulses occur in the center of the digit drive signals (D1, D2,D3, D4 and D5; see Figure 8).

D5 goes high for 201 counts when the measurementcycles end. In the center of D5 pulse, 101 clock pulses afterthe end of the measurement cycle, the first STROBE occursfor one-half clock pulse. After D5 strobe, D4 goes high for 200clock pulses. STROBE goes low 100 clock pulses after D4goes high. This continues through the D1 drive pulse.

The digit drive signals will continue to permit displayscanning. STROBE pulses are not repeated until a newmeasurement is completed. The digit drive signals will notcontinue if the previous signal resulted in an overrangecondition.

INTEGRATOROUTPUT

OVERRANGEWHEN

APPLICABLE

UNDERRANGEWHEN

APPLICABLE

SYSTEMZERO10,001

COUNTS

SIGNALINTE

10,000COUNTS(FIXED)

REFERENCEINTEGRATE

20,001COUNTS (MAX)

FULL MEASUREMENT CYCLE40,002 COUNTS

BUSY

EXPANDED SCALEBELOW

D5

D4

D3D2

D1100

COUNTS

DIGIT SCAN

STROBE

AUTO ZERO SIGNALINTEGRATE

REFERENCEINTEGRATE

D5

D4

D3

D2

D1

DIGIT SCANFOR

OVERRANGE

FIRST D5 OF SYSTEM ZEROAND REFERENCE INTEGRATEONE COUNT LONGER.

*

*

*

END OF CONVERSION

D5 (MSD)DATA

BUSY

B1–B8

STROBE

D5

D4

D3

D2

D1

D4DATA

D3DATA

D2DATA

D1 (LSD)DATA

D5DATA

NOTE ABSENCEOF STROBE

201COUNTS

200COUNTS

200COUNTS

200COUNTS

200COUNTS

200COUNTS

200COUNTS

*

*DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE PULSE IS DEPENDENT ON ANALOG INPUT.

TC7135OUTPUTS


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2

8

TC7135


POLARITY OutputA positive input is registered by a logic "1" polarity signal.

The POLARITY output (pin 23) is valid at the beginning ofreference integrate and remains valid until determined dur-ing the next conversion.

The POLARITY bit is valid even for a zero reading.Signals less than the converter's LSB will have the signalpolarity determined correctly. This is useful in null applica-tions.

Digit Drive OutputsDigit drive outputs are positive-going signals. Their scan

sequence is D5, D4, D3, D2 and D1 (pins 12, 17, 18, 19 and20, respectively). All positive signals are 200 clock pulseswide, except D5, which is 201 clock pulses.

All five digits are continuously scanned, unless anoverrange condition occurs. In an overrange condition, alldigit drives are held low from the final STROBE pulse untilthe beginning of the next reference-integrate phase. Thescanning sequence is then repeated, providing a blinkingvisual display.

BCD Data OutputsThe binary coded decimal (BCD) outputs, B8, B4, B2 and

B1 (pins 16, 15, 14 and 13, respectively) are positive true-logic signals. They become active simultaneously with digitdrive signals. In an overrange condition, all data bits arelogic "0".

APPLICATIONS INFORMATION

Component Value Selection

Integrating ResistorThe integrating resistor (RINT) is determined by the full-

scale input voltage and output current of the buffer used tocharge the integrator capacitor (CINT). Both the buffer ampli-fier and the integrator have a Class A output stage, with 100µA of quiescent current. A 20 µA drive current gives negli-gible linearity errors. Values of 5 µA to 40 µA give goodresults. The exact value of RINT for a 20 µA current is easilycalculated:

RINT = .Full-scale voltage

20 µA

Integrating CapacitorThe product of RINT and CINT should be selected to give

the maximum voltage swing to ensure tolerance build-up willnot saturate integrator swing (approximately 0.3V fromeither supply). For ±5V supplies, and analog common tied tosupply ground, a ±3.5V to ±4V full-scale integrator swing is

CINT =

= .

[10,000 x clock period] x IINT

Integrator output voltage swing

(10,000) (clock period) (20 µA)Integrator output voltage swing

Conversion Timing

Line Frequency RejectionA signal-integration period at a multiple of the 60 Hz line

frequency will maximize 60 Hz "line noise" rejection.A 100 kHz clock frequency will reject 50 Hz, 60 Hz and

400 Hz noise, corresponding to 2.5 readings per second.

A very important characteristic of the CINT is that it haslow dielectric absorption to prevent roll-over or ratiometricerrors. A good test for dielectric absorption is to use thecapacitor with the input tied to the reference. This ratiometriccondition should read half-scale 0.9999. Any deviation isprobably due to dielectric absorption. Polypropylenecapacitors give undetectable errors at reasonable cost.Polystyrene and polycarbonate capacitors may also beused in less critical applications.

Auto-Zero and Reference CapacitorsThe size of the auto-zero capacitor (CAZ) has some

influence on system noise. A large capacitor reduces noise.The reference capacitor (CREF) should be large enoughsuch that stray capacitance from its nodes to ground isnegligible.

The dielectric absorption of CREF and CAZ is only impor-tant at power-on, or when the circuit is recovering from anoverload. Smaller or cheaper capacitors can be used ifaccurate readings are not required during the first fewseconds of recovery.

Reference VoltageThe analog input required to generate a full-scale output

is VIN = 2 VREF.The stability of the reference voltage is a major factor in

overall absolute accuracy of the converter. Therefore, it isrecommended that high-quality references be used wherehigh-accuracy, absolute measurements are being made.Suitable references are:

Part Type Manufacturer

TC04 TelCom SemiconductorTC05 TelCom Semiconductor

adequate. A 0.10 µF to 0.47 µF is recommended. In general,the value of CINT is given by:


TC7135


High-Speed Operation

The maximum conversion rate of most dual-slope ADCsis limited by frequency response of the comparator. Thecomparator in this circuit follows the integrator ramp with a3 µs delay, and at a clock frequency of 160 kHz (6 µs period),half of the first reference integrate clock period is lost indelay. This means the meter reading will change from 0 to1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 with 250 µV,etc. This transition at midpoint is considered desirable bymost users; however, if clock frequency is increased appre-ciably above 160 kHz, the instrument will flash "1" on noisepeaks even when the input is shorted.

For many dedicated applications, where the input signalis always of one polarity, comparator delay need not be alimitation. Since nonlinearity and noise do not increasesubstantially with frequency, clock rates up to ~1 MHz maybe used. For a fixed clock frequency, the extra count (orcounts) caused by comparator delay will be constant andcan be digitally subtracted.

The clock frequency may be extended above 160 kHzwithout this error, however, by using a low value resistor inseries with the integrating capacitor. The effect of theresistor is to introduce a small pedestal voltage onto theintegrator output at the beginning of reference-integratephase. By careful selection of the ratio between this resis-tor and the integrating resistor (a few tens of ohms in therecommended circuit), the comparator delay can be com-pensated for and maximum clock frequency extendedby approximately a factor of 3. At higher frequencies, ring-ing and second-order breaks will cause significantnonlinearities during the first few counts of the instrument.

The minimum clock frequency is established by leakageon the auto-zero and reference capacitors. With most de-vices, measurement cycles as long as 10 seconds give nomeasurable leakage error.

The clock used should be free from significant phase orfrequency jitter. Several suitable low-cost oscillators areshown in the applications section. The multiplexed outputmeans if the display takes significant current from the logicsupply, the clock should have good PSRR.

Zero-Crossing Flip-Flop

The flip-flop interrogates data once every clock pulseafter transients of the previous clock pulse and half-clockpulse have died down. False zero-crossings caused byclock pulses are not recognized. Of course, the flip-flopdelays the true zero-crossing by up to one count in everyinstance, and if a correction were not made, the displaywould always be one count too high. Therefore, the counter

Table 3. Conversion Rate vs Clock Frequency

Conversion Rate Clock(Conv/Sec) Frequency (kHz)

2.5 1003.0 1205.0 2007.5 300

10.0 40020.0 80030.0 1200

Displays and Driver Circuits

TelCom Semiconductor manufactures three display de-coder/driver circuits to interface the TC7135 to LCDs or LEDdisplays. Each driver has 28 outputs for driving four 7-segment digit displays.

Device Package Description

TC7211AIPL 40-Pin Epoxy 4-Digit LCD Driver/Encoder

Several sources exist for LCDs and LED displays.

DisplayManufacturer Address Type

Hewlett Packard 640 Page Mill Road LEDComponents Palo Alto, CA 94304

AND 720 Palomar Ave. LCD andSunnyvale, CA 94086 LED

Epson America, Inc. 3415 Kanhi Kawa St. LCDTorrance, CA 90505

Table 2. Line Frequency Rejection

Oscillator Frequency Frequency Rejected(kHz) (Hz)

300, 200, 150, 120, 60100, 40, 33-1/3

250, 166-2/3, 50125, 100

100 50, 60, 400


7

6

5

4

3

1

2

8

TC7135


is disabled for one clock pulse at the beginning of thereference integrate (deintegrate) phase. This one-countdelay compensates for the delay of the zero-crossing flip-flop, and allows the correct number to be latched into thedisplay. Similarly, a one-count delay at the beginning ofauto-zero gives an overload display of 0000 instead of 0001.No delay occurs during signal integrate, so true ratiometricreadings result.

Generating a Negative Supply

A negative voltage can be generated from the positivesupply by using a TC7660. (See Figure 9.)

TC7660

TC7135

11

1

+5V

8

2 3

(–5V)

V+

V –

24

10 µF

5

4

10 µF

+

+

Figure 9. Negative Supply Voltage Generator

TYPICAL APPLICATIONS

R2 R1

fO

GATES ARE 74C04

C

+5V

VOUT

390 pF

30 kΩ

7

82

3

16 kΩ

0.22 µF

16 kΩ

4

1 kΩ

1

+5V

VOUT

2

3

1

4

7

6

R2100 kΩ

R2100 kΩ

R350 kΩ

C210 pF

R42 kΩ

C10.1 µF

–

+

LM311

–

+

LM311

56 kΩ

Comparator Clock CircuitRC Oscillator Circuit

1. fO ≈ , RP =

a. If R = R1 = R2, f ≅ 0.55/RC

b. If R2 >> R1, f ≅ 0.45/R1C

c. If R2 << R1, f ≅ 0.72/R1C

2. Examples:

a. f = 120 kHz, C = 420 pFR1 = R2 ≈ 10.9 kΩ

b. f = 120 kHz, C = 420 pF, R2 = 50 kΩR1 = 8.93 kΩ

c. f = 120 kHz, C = 220 pF, R2 = 5 kΩR1 = 27.3 kΩ

12 C[0.41 RP + 0.70 R1]

R1 R2

R1 + R2


TC7135


TYPICAL APPLICATIONS (Cont.)

4-1/2 Digit ADC With Multiplexed Common Anode LED Display

20 19 18 17 12

23

7

8

16

1514

13

1121

3

9

10

22

6

5

4

621

7

5 9–15

16

b c 7 7 7 7

TC7135

7447

BLANK MSD ON ZERO

D1 D2 D3 D4 D5

INT OUT

AZ IN

BUFFOUT

fIN

+INPUT

–INPUT

ANALOGCOMMON

V– REFIN

POL

CREF

B8

B4B2B1

+5V

+5V

X7

0.47 µF

120 kHz

+

–

ANALOGINPUT 1 µF

100 kΩ

1 µF

4.7 kΩ

1 µF

–5V

100 kΩ

100 kΩ

6.8 kΩ

D

B

C

A

RBI

V+

CREF

–

+

TC04

TC04

TC7211A

TC7135

INT OUT

AZ IN

BUFF OUT

+INPUT

–INPUT

ANALOGCOMMON

REFIN

V– POL

V+

20

19

18

17

16

15

14

13

12

26

27

D1

D2

D3

D4

B8

B4

B2

B1

D5

STROBE

OR

5

31

32

33

34

30

29

28

27

V+

D1

D2

D3

D4

B1

BP

B3

B2

B0GND

Q

RS

D

CLK

CD4071

+5V1/4 CD4030

4-1/2 DIGIT LCD

SEGMENTDRIVE

1

35

+5V

+5V

–5V

+

–

4

5

6

10

9

3

2

1/4 CD4081

1/2 CD4030

23CD4081 1/4 CD4030

1/2CD4013

6.8 kΩ

100 kΩ

100 kΩ

100 kΩ

0.47 µF

1 µF

ANALOGINPUT

1

120 kHz22

fIN

4-1/2 Digit ADC Interfaced to LCD With Digit Blanking on Overrange


7

6

5

4

3

1

2

8

TC7135


TYPICAL APPLICATIONS (Cont.)

4-1/2 Digit ADC With Multiplexed Common Cathode LED Display

TC04

28

27

26

25

24

23

22

21

9

8

7

6

5

4

3

2

1

REF IN

ANALOGGND

INTOUT

AZ INBUFFOUT

CREF

+5V

–5V6.8V

UR

DGND

POLARITY

OR

STROBE

RUN/HOLD

CLK IN

BUSY

1

2

3

4

5

6

7

8

9

SET VREF = 1V

1.22V

100kΩ

ANALOGGND

0.47 µF

100 kΩ

1 µF

47kΩ

150Ω

+5V

150Ω

10

11

12

13

14

15

16

17

18

+5V

CD4513BE

1 µF

TC7135

20

19

18

17

16

15

–INPUT

+INPUT

V+

D5 (MSD)

B1 (LSB)

B2

(LSD) D1

D2

D3

D4

B4

(MSB) B8

10

11

12

13

14

100kΩ

SIGIN

+

–

0.1µF

+5V

fO = 120 kHz

+

CREF–

V –

TC7135

DATA BUS

CONTROL

ADDRESS BUS

6522-VIA-

PA0PA1PA2

PA3PA4PA5PA6PA7CA1CA2

PB5PB4

PB0 PB3PB2PB1

CHANNEL SELECTION

GAIN SELECTION

1Y2Y3Y

1B2B3B

SEL1A2A3A

157

POLORURD5B8B4B2

B1D1D2D3D4STBR/H

V+ REF CAP

BUF

AZ

INT

INPUT+

VR

INPUT–

ANALOGCOMMON

DGND

5V

REF VOLTAGE

10

14

1615

8

11

3

9

GAIN: 10, 20, 50, 10015V 15V

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

DIFFERENTIALMULTIPLEXER

DG529

DA

DB

WR

A1 A0 EN

5V+

–

–+

fIN

fIN

–

+

LH0084

4-Channel Data Acquisition System

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www.datasheetcatalog.com

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Documents

Tc7135 4-1_2 Digit Analog-To-digital Converter