TableofContents RevisionHistory.............................................................................................................................26

Stellaris® LM3S6C11 Microcontroller

DATA SHEET

Copyr ight © 2007-2012Texas Instruments Incorporated

DS-LM3S6C11-11425

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright © 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as theproperty of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

January 23, 20122Texas Instruments-Production Data

Table of ContentsRevision History ............................................................................................................................. 26About This Document .................................................................................................................... 28Audience .............................................................................................................................................. 28About This Manual ................................................................................................................................ 28Related Documents ............................................................................................................................... 28Documentation Conventions .................................................................................................................. 29

1 Architectural Overview .......................................................................................... 311.1 Overview ...................................................................................................................... 311.2 Target Applications ........................................................................................................ 331.3 Features ....................................................................................................................... 331.3.1 ARM Cortex-M3 Processor Core .................................................................................... 331.3.2 On-Chip Memory ........................................................................................................... 351.3.3 Serial Communications Peripherals ................................................................................ 361.3.4 System Integration ........................................................................................................ 401.3.5 Analog .......................................................................................................................... 461.3.6 JTAG and ARM Serial Wire Debug ................................................................................ 461.3.7 Packaging and Temperature .......................................................................................... 471.4 Hardware Details .......................................................................................................... 47

2 The Cortex-M3 Processor ...................................................................................... 482.1 Block Diagram .............................................................................................................. 492.2 Overview ...................................................................................................................... 502.2.1 System-Level Interface .................................................................................................. 502.2.2 Integrated Configurable Debug ...................................................................................... 502.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 512.2.4 Cortex-M3 System Component Details ........................................................................... 512.3 Programming Model ...................................................................................................... 522.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 522.3.2 Stacks .......................................................................................................................... 522.3.3 Register Map ................................................................................................................ 532.3.4 Register Descriptions .................................................................................................... 542.3.5 Exceptions and Interrupts .............................................................................................. 672.3.6 Data Types ................................................................................................................... 672.4 Memory Model .............................................................................................................. 672.4.1 Memory Regions, Types and Attributes ........................................................................... 692.4.2 Memory System Ordering of Memory Accesses .............................................................. 692.4.3 Behavior of Memory Accesses ....................................................................................... 692.4.4 Software Ordering of Memory Accesses ......................................................................... 702.4.5 Bit-Banding ................................................................................................................... 712.4.6 Data Storage ................................................................................................................ 732.4.7 Synchronization Primitives ............................................................................................. 742.5 Exception Model ........................................................................................................... 752.5.1 Exception States ........................................................................................................... 762.5.2 Exception Types ............................................................................................................ 762.5.3 Exception Handlers ....................................................................................................... 792.5.4 Vector Table .................................................................................................................. 79

3January 23, 2012Texas Instruments-Production Data


2.5.5 Exception Priorities ....................................................................................................... 802.5.6 Interrupt Priority Grouping .............................................................................................. 812.5.7 Exception Entry and Return ........................................................................................... 812.6 Fault Handling .............................................................................................................. 832.6.1 Fault Types ................................................................................................................... 832.6.2 Fault Escalation and Hard Faults .................................................................................... 842.6.3 Fault Status Registers and Fault Address Registers ........................................................ 852.6.4 Lockup ......................................................................................................................... 852.7 Power Management ...................................................................................................... 852.7.1 Entering Sleep Modes ................................................................................................... 852.7.2 Wake Up from Sleep Mode ............................................................................................ 862.8 Instruction Set Summary ............................................................................................... 87

3 Cortex-M3 Peripherals ........................................................................................... 903.1 Functional Description ................................................................................................... 903.1.1 System Timer (SysTick) ................................................................................................. 903.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 913.1.3 System Control Block (SCB) .......................................................................................... 933.1.4 Memory Protection Unit (MPU) ....................................................................................... 933.2 Register Map ................................................................................................................ 983.3 System Timer (SysTick) Register Descriptions .............................................................. 1003.4 NVIC Register Descriptions .......................................................................................... 1043.5 System Control Block (SCB) Register Descriptions ........................................................ 1173.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 146

4 JTAG Interface ...................................................................................................... 1564.1 Block Diagram ............................................................................................................ 1574.2 Signal Description ....................................................................................................... 1574.3 Functional Description ................................................................................................. 1584.3.1 JTAG Interface Pins ..................................................................................................... 1584.3.2 JTAG TAP Controller ................................................................................................... 1604.3.3 Shift Registers ............................................................................................................ 1604.3.4 Operational Considerations .......................................................................................... 1614.4 Initialization and Configuration ..................................................................................... 1634.5 Register Descriptions .................................................................................................. 1644.5.1 Instruction Register (IR) ............................................................................................... 1644.5.2 Data Registers ............................................................................................................ 166

5 System Control ..................................................................................................... 1685.1 Signal Description ....................................................................................................... 1685.2 Functional Description ................................................................................................. 1695.2.1 Device Identification .................................................................................................... 1695.2.2 Reset Control .............................................................................................................. 1695.2.3 Non-Maskable Interrupt ............................................................................................... 1745.2.4 Power Control ............................................................................................................. 1755.2.5 Clock Control .............................................................................................................. 1755.2.6 System Control ........................................................................................................... 1825.3 Initialization and Configuration ..................................................................................... 1845.4 Register Map .............................................................................................................. 1845.5 Register Descriptions .................................................................................................. 186


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6 Hibernation Module .............................................................................................. 2596.1 Block Diagram ............................................................................................................ 2606.2 Signal Description ....................................................................................................... 2606.3 Functional Description ................................................................................................. 2616.3.1 Register Access Timing ............................................................................................... 2616.3.2 Hibernation Clock Source ............................................................................................ 2626.3.3 System Implementation ............................................................................................... 2636.3.4 Battery Management ................................................................................................... 2646.3.5 Real-Time Clock .......................................................................................................... 2646.3.6 Battery-Backed Memory .............................................................................................. 2656.3.7 Power Control Using HIB ............................................................................................. 2656.3.8 Power Control Using VDD3ON Mode ........................................................................... 2656.3.9 Initiating Hibernate ...................................................................................................... 2656.3.10 Waking from Hibernate ................................................................................................ 2656.3.11 Interrupts and Status ................................................................................................... 2666.4 Initialization and Configuration ..................................................................................... 2666.4.1 Initialization ................................................................................................................. 2666.4.2 RTC Match Functionality (No Hibernation) .................................................................... 2676.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 2676.4.4 External Wake-Up from Hibernation .............................................................................. 2686.4.5 RTC or External Wake-Up from Hibernation .................................................................. 2686.5 Register Map .............................................................................................................. 2686.6 Register Descriptions .................................................................................................. 269

7 Internal Memory ................................................................................................... 2867.1 Block Diagram ............................................................................................................ 2867.2 Functional Description ................................................................................................. 2867.2.1 SRAM ........................................................................................................................ 2877.2.2 ROM .......................................................................................................................... 2877.2.3 Flash Memory ............................................................................................................. 2897.3 Register Map .............................................................................................................. 2947.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 2967.5 Memory Register Descriptions (System Control Offset) .................................................. 308

8 Micro Direct Memory Access (μDMA) ................................................................ 3328.1 Block Diagram ............................................................................................................ 3338.2 Functional Description ................................................................................................. 3338.2.1 Channel Assignments .................................................................................................. 3348.2.2 Priority ........................................................................................................................ 3358.2.3 Arbitration Size ............................................................................................................ 3358.2.4 Request Types ............................................................................................................ 3358.2.5 Channel Configuration ................................................................................................. 3368.2.6 Transfer Modes ........................................................................................................... 3388.2.7 Transfer Size and Increment ........................................................................................ 3468.2.8 Peripheral Interface ..................................................................................................... 3468.2.9 Software Request ........................................................................................................ 3468.2.10 Interrupts and Errors .................................................................................................... 3478.3 Initialization and Configuration ..................................................................................... 3478.3.1 Module Initialization ..................................................................................................... 3478.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 348



8.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 3498.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 3518.3.5 Configuring Channel Assignments ................................................................................ 3538.4 Register Map .............................................................................................................. 3538.5 μDMA Channel Control Structure ................................................................................. 3558.6 μDMA Register Descriptions ........................................................................................ 362

9 General-Purpose Input/Outputs (GPIOs) ........................................................... 3929.1 Signal Description ....................................................................................................... 3929.2 Functional Description ................................................................................................. 3969.2.1 Data Control ............................................................................................................... 3979.2.2 Interrupt Control .......................................................................................................... 3989.2.3 Mode Control .............................................................................................................. 3999.2.4 Commit Control ........................................................................................................... 3999.2.5 Pad Control ................................................................................................................. 3999.2.6 Identification ............................................................................................................... 4009.3 Initialization and Configuration ..................................................................................... 4009.4 Register Map .............................................................................................................. 4019.5 Register Descriptions .................................................................................................. 403

10 General-Purpose Timers ...................................................................................... 44410.1 Block Diagram ............................................................................................................ 44410.2 Signal Description ....................................................................................................... 44510.3 Functional Description ................................................................................................. 44710.3.1 GPTM Reset Conditions .............................................................................................. 44810.3.2 Timer Modes ............................................................................................................... 44810.3.3 DMA Operation ........................................................................................................... 45510.3.4 Accessing Concatenated Register Values ..................................................................... 45510.4 Initialization and Configuration ..................................................................................... 45610.4.1 One-Shot/Periodic Timer Mode .................................................................................... 45610.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 45710.4.3 Input Edge-Count Mode ............................................................................................... 45710.4.4 Input Edge Timing Mode .............................................................................................. 45810.4.5 PWM Mode ................................................................................................................. 45810.5 Register Map .............................................................................................................. 45910.6 Register Descriptions .................................................................................................. 460

11 Watchdog Timers ................................................................................................. 49111.1 Block Diagram ............................................................................................................ 49211.2 Functional Description ................................................................................................. 49211.2.1 Register Access Timing ............................................................................................... 49311.3 Initialization and Configuration ..................................................................................... 49311.4 Register Map .............................................................................................................. 49311.5 Register Descriptions .................................................................................................. 494

12 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 51612.1 Block Diagram ............................................................................................................ 51712.2 Signal Description ....................................................................................................... 51712.3 Functional Description ................................................................................................. 51912.3.1 Transmit/Receive Logic ............................................................................................... 51912.3.2 Baud-Rate Generation ................................................................................................. 519


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12.3.3 Data Transmission ...................................................................................................... 52012.3.4 Serial IR (SIR) ............................................................................................................. 52112.3.5 ISO 7816 Support ....................................................................................................... 52212.3.6 Modem Handshake Support ......................................................................................... 52212.3.7 LIN Support ................................................................................................................ 52312.3.8 FIFO Operation ........................................................................................................... 52512.3.9 Interrupts .................................................................................................................... 52512.3.10 Loopback Operation .................................................................................................... 52612.3.11 DMA Operation ........................................................................................................... 52612.4 Initialization and Configuration ..................................................................................... 52712.5 Register Map .............................................................................................................. 52812.6 Register Descriptions .................................................................................................. 529

13 Synchronous Serial Interface (SSI) .................................................................... 57913.1 Block Diagram ............................................................................................................ 58013.2 Signal Description ....................................................................................................... 58013.3 Functional Description ................................................................................................. 58113.3.1 Bit Rate Generation ..................................................................................................... 58113.3.2 FIFO Operation ........................................................................................................... 58213.3.3 Interrupts .................................................................................................................... 58213.3.4 Frame Formats ........................................................................................................... 58313.3.5 DMA Operation ........................................................................................................... 59013.4 Initialization and Configuration ..................................................................................... 59113.5 Register Map .............................................................................................................. 59213.6 Register Descriptions .................................................................................................. 593

14 Inter-Integrated Circuit (I2C) Interface ................................................................ 62114.1 Block Diagram ............................................................................................................ 62214.2 Signal Description ....................................................................................................... 62214.3 Functional Description ................................................................................................. 62314.3.1 I2C Bus Functional Overview ........................................................................................ 62314.3.2 Available Speed Modes ............................................................................................... 62514.3.3 Interrupts .................................................................................................................... 62614.3.4 Loopback Operation .................................................................................................... 62714.3.5 Command Sequence Flow Charts ................................................................................ 62814.4 Initialization and Configuration ..................................................................................... 63514.5 Register Map .............................................................................................................. 63614.6 Register Descriptions (I2C Master) ............................................................................... 63714.7 Register Descriptions (I2C Slave) ................................................................................. 650

15 Ethernet Controller .............................................................................................. 65915.1 Block Diagram ............................................................................................................ 66015.2 Signal Description ....................................................................................................... 66115.3 Functional Description ................................................................................................. 66215.3.1 MAC Operation ........................................................................................................... 66215.3.2 Internal MII Operation .................................................................................................. 66515.3.3 PHY Operation ............................................................................................................ 66515.3.4 Interrupts .................................................................................................................... 66815.3.5 DMA Operation ........................................................................................................... 66815.4 Initialization and Configuration ..................................................................................... 669



15.4.1 Hardware Configuration ............................................................................................... 66915.4.2 Software Configuration ................................................................................................ 67015.5 Register Map .............................................................................................................. 67015.6 Ethernet MAC Register Descriptions ............................................................................. 67215.7 MII Management Register Descriptions ......................................................................... 697

16 Analog Comparators ............................................................................................ 71816.1 Block Diagram ............................................................................................................ 71816.2 Signal Description ....................................................................................................... 71816.3 Functional Description ................................................................................................. 71916.3.1 Internal Reference Programming .................................................................................. 72016.4 Initialization and Configuration ..................................................................................... 72116.5 Register Map .............................................................................................................. 72216.6 Register Descriptions .................................................................................................. 722

17 Pin Diagram .......................................................................................................... 73018 Signal Tables ........................................................................................................ 73218.1 100-Pin LQFP Package Pin Tables ............................................................................... 73218.2 108-Ball BGA Package Pin Tables ................................................................................ 75218.3 Connections for Unused Signals ................................................................................... 772

19 Operating Characteristics ................................................................................... 77420 Electrical Characteristics .................................................................................... 77520.1 Maximum Ratings ....................................................................................................... 77520.2 Recommended Operating Conditions ........................................................................... 77520.3 Load Conditions .......................................................................................................... 77620.4 JTAG and Boundary Scan ............................................................................................ 77620.5 Power and Brown-Out ................................................................................................. 77820.6 Reset ......................................................................................................................... 77920.7 On-Chip Low Drop-Out (LDO) Regulator ....................................................................... 78020.8 Clocks ........................................................................................................................ 78020.8.1 PLL Specifications ....................................................................................................... 78020.8.2 PIOSC Specifications .................................................................................................. 78120.8.3 Internal 30-kHz Oscillator Specifications ....................................................................... 78120.8.4 Hibernation Clock Source Specifications ....................................................................... 78220.8.5 Main Oscillator Specifications ....................................................................................... 78220.9 Sleep Modes ............................................................................................................... 78320.10 Hibernation Module ..................................................................................................... 78320.11 Flash Memory ............................................................................................................. 78520.12 Input/Output Characteristics ......................................................................................... 78520.13 Synchronous Serial Interface (SSI) ............................................................................... 78520.14 Inter-Integrated Circuit (I2C) Interface ........................................................................... 78720.15 Ethernet Controller ...................................................................................................... 78820.16 Analog Comparator ..................................................................................................... 79020.17 Current Consumption .................................................................................................. 79120.17.1 Nominal Power Consumption ....................................................................................... 79120.17.2 Maximum Current Consumption ................................................................................... 792

A Register Quick Reference ................................................................................... 794B Ordering and Contact Information ..................................................................... 817


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B.1 Ordering Information .................................................................................................... 817B.2 Part Markings .............................................................................................................. 817B.3 Kits ............................................................................................................................. 818B.4 Support Information ..................................................................................................... 818

C Package Information ............................................................................................ 819C.1 100-Pin LQFP Package ............................................................................................... 819C.1.1 Package Dimensions ................................................................................................... 819C.1.2 Tray Dimensions ......................................................................................................... 821C.1.3 Tape and Reel Dimensions .......................................................................................... 821C.2 108-Ball BGA Package ................................................................................................ 823C.2.1 Package Dimensions ................................................................................................... 823C.2.2 Tray Dimensions ......................................................................................................... 825C.2.3 Tape and Reel Dimensions .......................................................................................... 826



List of FiguresFigure 1-1. Stellaris LM3S6C11 Microcontroller High-Level Block Diagram ............................... 32Figure 2-1. CPU Block Diagram ............................................................................................. 50Figure 2-2. TPIU Block Diagram ............................................................................................ 51Figure 2-3. Cortex-M3 Register Set ........................................................................................ 53Figure 2-4. Bit-Band Mapping ................................................................................................ 73Figure 2-5. Data Storage ....................................................................................................... 74Figure 2-6. Vector Table ........................................................................................................ 80Figure 2-7. Exception Stack Frame ........................................................................................ 82Figure 3-1. SRD Use Example ............................................................................................... 96Figure 4-1. JTAG Module Block Diagram .............................................................................. 157Figure 4-2. Test Access Port State Machine ......................................................................... 160Figure 4-3. IDCODE Register Format ................................................................................... 166Figure 4-4. BYPASS Register Format ................................................................................... 166Figure 4-5. Boundary Scan Register Format ......................................................................... 167Figure 5-1. Basic RST Configuration .................................................................................... 171Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 172Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 172Figure 5-4. Power Architecture ............................................................................................ 175Figure 5-5. Main Clock Tree ................................................................................................ 178Figure 6-1. Hibernation Module Block Diagram ..................................................................... 260Figure 6-2. Using a Crystal as the Hibernation Clock Source ................................................. 263Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 263Figure 7-1. Internal Memory Block Diagram .......................................................................... 286Figure 8-1. μDMA Block Diagram ......................................................................................... 333Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 339Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 341Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 342Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 344Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 345Figure 9-1. Digital I/O Pads ................................................................................................. 396Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 397Figure 9-3. GPIODATA Write Example ................................................................................. 398Figure 9-4. GPIODATA Read Example ................................................................................. 398Figure 10-1. GPTM Module Block Diagram ............................................................................ 445Figure 10-2. Timer Daisy Chain ............................................................................................. 450Figure 10-3. Input Edge-Count Mode Example ....................................................................... 452Figure 10-4. 16-Bit Input Edge-Time Mode Example ............................................................... 454Figure 10-5. 16-Bit PWM Mode Example ................................................................................ 455Figure 11-1. WDT Module Block Diagram .............................................................................. 492Figure 12-1. UART Module Block Diagram ............................................................................. 517Figure 12-2. UART Character Frame ..................................................................................... 519Figure 12-3. IrDA Data Modulation ......................................................................................... 521Figure 12-4. LIN Message ..................................................................................................... 524Figure 12-5. LIN Synchronization Field ................................................................................... 525Figure 13-1. SSI Module Block Diagram ................................................................................. 580


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Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 584Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 584Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 585Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 585Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 586Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 587Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 587Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 588Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 589Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 590Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 590Figure 14-1. I2C Block Diagram ............................................................................................. 622Figure 14-2. I2C Bus Configuration ........................................................................................ 623Figure 14-3. START and STOP Conditions ............................................................................. 624Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 624Figure 14-5. R/S Bit in First Byte ............................................................................................ 625Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 625Figure 14-7. Master Single TRANSMIT .................................................................................. 629Figure 14-8. Master Single RECEIVE ..................................................................................... 630Figure 14-9. Master TRANSMIT with Repeated START ........................................................... 631Figure 14-10. Master RECEIVE with Repeated START ............................................................. 632Figure 14-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated

START .............................................................................................................. 633Figure 14-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated

START .............................................................................................................. 634Figure 14-13. Slave Command Sequence ................................................................................ 635Figure 15-1. Ethernet Controller ............................................................................................. 660Figure 15-2. Ethernet Controller Block Diagram ...................................................................... 660Figure 15-3. Ethernet Frame ................................................................................................. 662Figure 15-4. Interface to an Ethernet Jack .............................................................................. 669Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 718Figure 16-2. Structure of Comparator Unit .............................................................................. 720Figure 16-3. Comparator Internal Reference Structure ............................................................ 720Figure 17-1. 100-Pin LQFP Package Pin Diagram .................................................................. 730Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 731Figure 20-1. Load Conditions ................................................................................................ 776Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 777Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 777Figure 20-4. Power-On Reset Timing ..................................................................................... 778Figure 20-5. Brown-Out Reset Timing .................................................................................... 778Figure 20-6. Power-On Reset and Voltage Parameters ........................................................... 779Figure 20-7. External Reset Timing (RST) .............................................................................. 779Figure 20-8. Software Reset Timing ....................................................................................... 779Figure 20-9. Watchdog Reset Timing ..................................................................................... 780Figure 20-10. MOSC Failure Reset Timing ............................................................................... 780Figure 20-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 784Figure 20-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 784



Figure 20-13. SSI Timing for TI Frame Format (FRF=01), Single Transfer TimingMeasurement .................................................................................................... 786

Figure 20-14. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 786Figure 20-15. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 787Figure 20-16. I2C Timing ......................................................................................................... 788Figure 20-17. External XTLP Oscillator Characteristics ............................................................. 790Figure C-1. Stellaris LM3S6C11 100-Pin LQFP Package Dimensions ..................................... 819Figure C-2. 100-Pin LQFP Tray Dimensions .......................................................................... 821Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 822Figure C-4. Stellaris LM3S6C11 108-Ball BGA Package Dimensions ...................................... 823Figure C-5. 108-Ball BGA Tray Dimensions ........................................................................... 825Figure C-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 826


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List of TablesTable 1. Revision History .................................................................................................. 26Table 2. Documentation Conventions ................................................................................ 29Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 53Table 2-2. Processor Register Map ....................................................................................... 54Table 2-3. PSR Register Combinations ................................................................................. 59Table 2-4. Memory Map ....................................................................................................... 67Table 2-5. Memory Access Behavior ..................................................................................... 70Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 72Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 72Table 2-8. Exception Types .................................................................................................. 77Table 2-9. Interrupts ............................................................................................................ 78Table 2-10. Exception Return Behavior ................................................................................... 83Table 2-11. Faults ................................................................................................................. 83Table 2-12. Fault Status and Fault Address Registers .............................................................. 85Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 87Table 3-1. Core Peripheral Register Regions ......................................................................... 90Table 3-2. Memory Attributes Summary ................................................................................ 93Table 3-3. TEX, S, C, and B Bit Field Encoding ..................................................................... 96Table 3-4. Cache Policy for Memory Attribute Encoding ......................................................... 97Table 3-5. AP Bit Field Encoding .......................................................................................... 97Table 3-6. Memory Region Attributes for Stellaris Microcontrollers .......................................... 97Table 3-7. Peripherals Register Map ..................................................................................... 98Table 3-8. Interrupt Priority Levels ...................................................................................... 125Table 3-9. Example SIZE Field Values ................................................................................ 153Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 157Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 158Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 159Table 4-4. JTAG Instruction Register Commands ................................................................. 164Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 168Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 168Table 5-3. Reset Sources ................................................................................................... 169Table 5-4. Clock Source Options ........................................................................................ 176Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 179Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 179Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 180Table 5-8. System Control Register Map ............................................................................. 184Table 5-9. RCC2 Fields that Override RCC Fields ............................................................... 205Table 6-1. Hibernate Signals (100LQFP) ............................................................................. 260Table 6-2. Hibernate Signals (108BGA) .............................................................................. 261Table 6-3. Hibernation Module Clock Operation ................................................................... 267Table 6-4. Hibernation Module Register Map ....................................................................... 269Table 7-1. Flash Memory Protection Policy Combinations .................................................... 290Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 294Table 7-3. Flash Register Map ............................................................................................ 294Table 8-1. μDMA Channel Assignments .............................................................................. 334Table 8-2. Request Type Support ....................................................................................... 336



Table 8-3. Control Structure Memory Map ........................................................................... 337Table 8-4. Channel Control Structure .................................................................................. 337Table 8-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 346Table 8-6. μDMA Interrupt Assignments .............................................................................. 347Table 8-7. Channel Control Structure Offsets for Channel 30 ................................................ 348Table 8-8. Channel Control Word Configuration for Memory Transfer Example ...................... 348Table 8-9. Channel Control Structure Offsets for Channel 7 .................................................. 349Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 350Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 351Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 352Table 8-13. μDMA Register Map .......................................................................................... 354Table 9-1. GPIO Pins With Non-Zero Reset Values .............................................................. 393Table 9-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 393Table 9-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 394Table 9-4. GPIO Pad Configuration Examples ..................................................................... 400Table 9-5. GPIO Interrupt Configuration Example ................................................................ 401Table 9-6. GPIO Pins With Non-Zero Reset Values .............................................................. 402Table 9-7. GPIO Register Map ........................................................................................... 402Table 9-8. GPIO Pins With Non-Zero Reset Values .............................................................. 413Table 9-9. GPIO Pins With Non-Zero Reset Values .............................................................. 419Table 9-10. GPIO Pins With Non-Zero Reset Values .............................................................. 421Table 9-11. GPIO Pins With Non-Zero Reset Values .............................................................. 424Table 9-12. GPIO Pins With Non-Zero Reset Values .............................................................. 430Table 10-1. Available CCP Pins ............................................................................................ 445Table 10-2. General-Purpose Timers Signals (100LQFP) ....................................................... 446Table 10-3. General-Purpose Timers Signals (108BGA) ......................................................... 447Table 10-4. General-Purpose Timer Capabilities .................................................................... 448Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 449Table 10-6. 16-Bit Timer With Prescaler Configurations ......................................................... 450Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 451Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 451Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 453Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 454Table 10-11. Timers Register Map .......................................................................................... 459Table 11-1. Watchdog Timers Register Map .......................................................................... 494Table 12-1. UART Signals (100LQFP) .................................................................................. 518Table 12-2. UART Signals (108BGA) .................................................................................... 518Table 12-3. Flow Control Mode ............................................................................................. 523Table 12-4. UART Register Map ........................................................................................... 528Table 13-1. SSI Signals (100LQFP) ...................................................................................... 581Table 13-2. SSI Signals (108BGA) ........................................................................................ 581Table 13-3. SSI Register Map .............................................................................................. 592Table 14-1. I2C Signals (100LQFP) ...................................................................................... 622Table 14-2. I2C Signals (108BGA) ........................................................................................ 622Table 14-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 626Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 636Table 14-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 642


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Table 15-1. Ethernet Signals (100LQFP) ............................................................................... 661Table 15-2. Ethernet Signals (108BGA) ................................................................................ 661Table 15-3. TX & RX FIFO Organization ............................................................................... 664Table 15-4. Ethernet Register Map ....................................................................................... 671Table 16-1. Analog Comparators Signals (100LQFP) ............................................................. 719Table 16-2. Analog Comparators Signals (108BGA) .............................................................. 719Table 16-3. Internal Reference Voltage and ACREFCTL Field Values ..................................... 721Table 16-4. Analog Comparators Register Map ..................................................................... 722Table 18-1. GPIO Pins With Default Alternate Functions ........................................................ 732Table 18-2. Signals by Pin Number ....................................................................................... 732Table 18-3. Signals by Signal Name ..................................................................................... 739Table 18-4. Signals by Function, Except for GPIO ................................................................. 745Table 18-5. GPIO Pins and Alternate Functions ..................................................................... 750Table 18-6. Possible Pin Assignments for Alternate Functions ................................................ 751Table 18-7. Signals by Pin Number ....................................................................................... 752Table 18-8. Signals by Signal Name ..................................................................................... 759Table 18-9. Signals by Function, Except for GPIO ................................................................. 765Table 18-10. GPIO Pins and Alternate Functions ..................................................................... 770Table 18-11. Possible Pin Assignments for Alternate Functions ................................................ 771Table 18-12. Connections for Unused Signals (100-Pin LQFP) ................................................. 772Table 18-13. Connections for Unused Signals (108-Ball BGA) .................................................. 773Table 19-1. Temperature Characteristics ............................................................................... 774Table 19-2. Thermal Characteristics ..................................................................................... 774Table 19-3. ESD Absolute Maximum Ratings ........................................................................ 774Table 20-1. Maximum Ratings .............................................................................................. 775Table 20-2. Recommended DC Operating Conditions ............................................................ 775Table 20-3. JTAG Characteristics ......................................................................................... 776Table 20-4. Power Characteristics ........................................................................................ 778Table 20-5. Reset Characteristics ......................................................................................... 779Table 20-6. LDO Regulator Characteristics ........................................................................... 780Table 20-7. Phase Locked Loop (PLL) Characteristics ........................................................... 780Table 20-8. Actual PLL Frequency ........................................................................................ 781Table 20-9. PIOSC Clock Characteristics .............................................................................. 781Table 20-10. 30-kHz Clock Characteristics .............................................................................. 781Table 20-11. Hibernation Clock Characteristics ....................................................................... 782Table 20-12. HIB Oscillator Input Characteristics ..................................................................... 782Table 20-13. Main Oscillator Clock Characteristics .................................................................. 782Table 20-14. Supported MOSC Crystal Frequencies ................................................................ 782Table 20-15. Sleep Modes AC Characteristics ......................................................................... 783Table 20-16. Hibernation Module Battery Characteristics ......................................................... 783Table 20-17. Hibernation Module AC Characteristics ............................................................... 784Table 20-18. Flash Memory Characteristics ............................................................................ 785Table 20-19. GPIO Module Characteristics ............................................................................. 785Table 20-20. SSI Characteristics ............................................................................................ 785Table 20-21. I2C Characteristics ............................................................................................. 787Table 20-22. Ethernet Controller DC Characteristics ................................................................ 788Table 20-23. 100BASE-TX Transmitter Characteristics ............................................................ 788Table 20-24. 100BASE-TX Transmitter Characteristics (informative) ......................................... 788



Table 20-25. 100BASE-TX Receiver Characteristics ................................................................ 788Table 20-26. 10BASE-T Transmitter Characteristics ................................................................ 789Table 20-27. 10BASE-T Transmitter Characteristics (informative) ............................................. 789Table 20-28. 10BASE-T Receiver Characteristics .................................................................... 789Table 20-29. Isolation Transformers ....................................................................................... 789Table 20-30. Ethernet Reference Crystal ................................................................................ 789Table 20-31. External XTLP Oscillator Characteristics ............................................................. 790Table 20-32. Analog Comparator Characteristics ..................................................................... 790Table 20-33. Analog Comparator Voltage Reference Characteristics ........................................ 791Table 20-34. Nominal Power Consumption ............................................................................. 791Table 20-35. Detailed Current Specifications ........................................................................... 792Table 20-36. Hibernation Detailed Current Specifications ......................................................... 792Table B-1. Part Ordering Information ................................................................................... 817


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List of RegistersThe Cortex-M3 Processor ............................................................................................................. 48Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 55Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 55Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 55Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 55Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 55Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 55Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 55Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 55Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 55Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 55Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 55Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 55Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 55Register 14: Stack Pointer (SP) ........................................................................................................... 56Register 15: Link Register (LR) ............................................................................................................ 57Register 16: Program Counter (PC) ..................................................................................................... 58Register 17: Program Status Register (PSR) ........................................................................................ 59Register 18: Priority Mask Register (PRIMASK) .................................................................................... 63Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 64Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 65Register 21: Control Register (CONTROL) ........................................................................................... 66

Cortex-M3 Peripherals ................................................................................................................... 90Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 101Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 103Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 104Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 105Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 106Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 107Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 108Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 109Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 110Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 111Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 112Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 113Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 114Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 115Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 115Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 115Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 115Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 115Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 115Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 115Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 115Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 115



Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 115Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 115Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 115Register 26: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 115Register 27: Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 115Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 117Register 29: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 118Register 30: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 120Register 31: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 121Register 32: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 124Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 125Register 34: System Control (SYSCTRL), offset 0xD10 ....................................................................... 127Register 35: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 129Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 131Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 132Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 133Register 39: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 134Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 138Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 144Register 42: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 145Register 43: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 146Register 44: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 147Register 45: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 148Register 46: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 150Register 47: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 151Register 48: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 151Register 49: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 151Register 50: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 151Register 51: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 153Register 52: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 153Register 53: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 153Register 54: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 153

System Control ............................................................................................................................ 168Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 187Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 189Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 190Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 192Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 194Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 196Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 198Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 202Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 203Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 205Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 208Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 209Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 211Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 213Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 214


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Register 16: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 216Register 17: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 217Register 18: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 219Register 19: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 221Register 20: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 223Register 21: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 225Register 22: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 226Register 23: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 227Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 231Register 25: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 232Register 26: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 233Register 27: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 235Register 28: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 237Register 29: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 239Register 30: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 242Register 31: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 245Register 32: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 248Register 33: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 250Register 34: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 252Register 35: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 254Register 36: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 255Register 37: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 257

Hibernation Module ..................................................................................................................... 259Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 270Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 271Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 272Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 273Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 274Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 277Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 279Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 281Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 283Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 284Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 285

Internal Memory ........................................................................................................................... 286Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 297Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 298Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 299Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 302Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 303Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 304Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 305Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 306Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 307Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 308Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 309Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 310Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 311



Register 14: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 312Register 15: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 314Register 16: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 315Register 17: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 316Register 18: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 317Register 19: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 318Register 20: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 319Register 21: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0