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Getting Started with SystemCUVM

Verification in SystemC Perspective

Puneet Goel

Coverify Systems Technology

April 2012

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Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

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Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

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Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

Cover i fyo

Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

Cover i fyo

Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

Cover i fyo

Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

Cover i fyo

Introduction

I UVM stands for Universal VerificationMethodology

I UVM is the Accellera approved standardmethodology for verification

I UVM is primarily coded in SystemVerilogI In November 2011, Cadence released UVM

Multi-language package on UVM websitehttp://uvmworld.com

I The package contains a partial port of UVMLibrary in SystemC and e

I In Feburary 2012, Mentor Graphics releasedopensource implementation of uvm::connect,and named the library UVMC

I Both UVM-ML and UVMC have been releasedunder Apache License

Getting Started with SystemC UVM 2 / 22

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UVM Testbench

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

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Figure: UVM Testbench Infrastructure

Getting Started with SystemC UVM 3 / 22

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SystemC UVM Testbench

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

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Figure: Currently Supported by SystemC UVM

Getting Started with SystemC UVM 4 / 22

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SystemC UVM Testbench

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

Sign

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CheckerConstrained

Randomization

Figure: Currently Supported by SystemC UVM

Getting Started with SystemC UVM 4 / 22

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SystemC UVM Testbench

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

Sign

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RegisterAbstraction Layer

Figure: Currently Supported by SystemC UVM

Getting Started with SystemC UVM 4 / 22

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In this section . . .

SystemC PerspectiveWhy SystemC for Verification

UVM for SystemC

Getting Started with SystemC UVM SystemC Perspective 5 / 22

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Why SystemC?

A couple of questions that obviously prop are:I Is not verification meant to be done using HVLs like

Specman/Vera/SystemVerilog etc?I Is not UVM primarily coded in SystemVerilog?I What advantage does SystemC has over SystemVerilog?

Getting Started with SystemC UVM SystemC Perspective 6 / 22

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Why SystemC?

A couple of questions that obviously prop are:I Is not verification meant to be done using HVLs like

Specman/Vera/SystemVerilog etc?I Is not UVM primarily coded in SystemVerilog?I What advantage does SystemC has over SystemVerilog?

Getting Started with SystemC UVM SystemC Perspective 6 / 22

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Why SystemC?

A couple of questions that obviously prop are:I Is not verification meant to be done using HVLs like

Specman/Vera/SystemVerilog etc?I Is not UVM primarily coded in SystemVerilog?I What advantage does SystemC has over SystemVerilog?

Getting Started with SystemC UVM SystemC Perspective 6 / 22

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SystemC UVM Use Cases

I Verification of ESL componentscoded in SystemC usingSystemVerilog based testbenches

I Using SystemC Driver andMonitor components inSystemVerilog testbench

I SystemC model used as goldenreference model for verification

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

Sign

alLa

yer

Com

man

dLa

yer

Fun

ctio

nal

Laye

rSe

quen

ceLa

yer

Test

Laye

r

Functional

Cov

erag

e

Checker

Getting Started with SystemC UVM SystemC Perspective 7 / 22

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SystemC UVM Use Cases

I Verification of ESL componentscoded in SystemC usingSystemVerilog based testbenches

I Using SystemC Driver andMonitor components inSystemVerilog testbench

I SystemC model used as goldenreference model for verification

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

Sign

alLa

yer

Com

man

dLa

yer

Fun

ctio

nal

Laye

rSe

quen

ceLa

yer

Test

Laye

r

Functional

Cov

erag

e

Checker

Getting Started with SystemC UVM SystemC Perspective 7 / 22

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SystemC UVM Use Cases

I Verification of ESL componentscoded in SystemC usingSystemVerilog based testbenches

I Using SystemC Driver andMonitor components inSystemVerilog testbench

I SystemC model used as goldenreference model for verification

Testcase

Sequencer

Transactor

Driver Collector

DesignUnder Test

AssertionsCollector

Monitor

Sign

alLa

yer

Com

man

dLa

yer

Fun

ctio

nal

Laye

rSe

quen

ceLa

yer

Test

Laye

r

Functional

Cov

erag

e

Checker

Getting Started with SystemC UVM SystemC Perspective 7 / 22

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SystemC for coding Reference Model

I SystemVerilog is a Hardware Design and Verification LanguageI Often your DUT (or a part of it) would be coded using verilogI Coding reference model in the same language as the language in which

your design has been coded is often a bad idea

I When designers and verificationengineers use same language,there is a risk that they mightshare code

I Or might make same mistakes –they would have the same set oflanguage gotchas to deal with

Getting Started with SystemC UVM SystemC Perspective 8 / 22

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SystemC for coding Reference Model

I SystemVerilog is a Hardware Design and Verification LanguageI Often your DUT (or a part of it) would be coded using verilogI Coding reference model in the same language as the language in which

your design has been coded is often a bad idea

I When designers and verificationengineers use same language,there is a risk that they mightshare code

I Or might make same mistakes –they would have the same set oflanguage gotchas to deal with

Getting Started with SystemC UVM SystemC Perspective 8 / 22

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SystemC for coding Reference Model

I SystemVerilog is a Hardware Design and Verification LanguageI Often your DUT (or a part of it) would be coded using verilogI Coding reference model in the same language as the language in which

your design has been coded is often a bad idea

I When designers and verificationengineers use same language,there is a risk that they mightshare code

I Or might make same mistakes –they would have the same set oflanguage gotchas to deal with

Getting Started with SystemC UVM SystemC Perspective 8 / 22

Cover i fyo

SystemC for coding Reference Model

I SystemVerilog is a Hardware Design and Verification LanguageI Often your DUT (or a part of it) would be coded using verilogI Coding reference model in the same language as the language in which

your design has been coded is often a bad idea

I When designers and verificationengineers use same language,there is a risk that they mightshare code

I Or might make same mistakes –they would have the same set oflanguage gotchas to deal with

Getting Started with SystemC UVM SystemC Perspective 8 / 22

Cover i fyo

SystemC for coding Reference Model

I SystemVerilog is a Hardware Design and Verification LanguageI Often your DUT (or a part of it) would be coded using verilogI Coding reference model in the same language as the language in which

your design has been coded is often a bad idea

I When designers and verificationengineers use same language,there is a risk that they mightshare code

I Or might make same mistakes –they would have the same set oflanguage gotchas to deal with

Getting Started with SystemC UVM SystemC Perspective 8 / 22

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Generic Library

I Though SystemVerilog supports parameterized classes, it does notsupport function and operator overloading

I As a result, SystemVerilog lacks a generic algorithmic libraryI For example if you develop a sort function in systemverilog that works for

builtin number types, you can not generalize this function to work onuser-defined data types

I In comparison SystemC, since it is built over C++, has generic librariessuch as STL and boost

I These libraries come in handy when you are modeling at behavioral levelI Also since C++ has a much bigger user-base, these libraries are well-tested

and therefor are ideal for creating reference models

Getting Started with SystemC UVM SystemC Perspective 9 / 22

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Generic Library

I Though SystemVerilog supports parameterized classes, it does notsupport function and operator overloading

I As a result, SystemVerilog lacks a generic algorithmic libraryI For example if you develop a sort function in systemverilog that works for

builtin number types, you can not generalize this function to work onuser-defined data types

I In comparison SystemC, since it is built over C++, has generic librariessuch as STL and boost

I These libraries come in handy when you are modeling at behavioral levelI Also since C++ has a much bigger user-base, these libraries are well-tested

and therefor are ideal for creating reference models

Getting Started with SystemC UVM SystemC Perspective 9 / 22

Cover i fyo

Generic Library

I Though SystemVerilog supports parameterized classes, it does notsupport function and operator overloading

I As a result, SystemVerilog lacks a generic algorithmic libraryI For example if you develop a sort function in systemverilog that works for

builtin number types, you can not generalize this function to work onuser-defined data types

I In comparison SystemC, since it is built over C++, has generic librariessuch as STL and boost

I These libraries come in handy when you are modeling at behavioral levelI Also since C++ has a much bigger user-base, these libraries are well-tested

and therefor are ideal for creating reference models

Getting Started with SystemC UVM SystemC Perspective 9 / 22

Cover i fyo

Generic Library

I Though SystemVerilog supports parameterized classes, it does notsupport function and operator overloading

I As a result, SystemVerilog lacks a generic algorithmic libraryI For example if you develop a sort function in systemverilog that works for

builtin number types, you can not generalize this function to work onuser-defined data types

I In comparison SystemC, since it is built over C++, has generic librariessuch as STL and boost

I These libraries come in handy when you are modeling at behavioral levelI Also since C++ has a much bigger user-base, these libraries are well-tested

and therefor are ideal for creating reference models

Getting Started with SystemC UVM SystemC Perspective 9 / 22

Cover i fyo

Generic Library

I Though SystemVerilog supports parameterized classes, it does notsupport function and operator overloading

I As a result, SystemVerilog lacks a generic algorithmic libraryI For example if you develop a sort function in systemverilog that works for

builtin number types, you can not generalize this function to work onuser-defined data types

I In comparison SystemC, since it is built over C++, has generic librariessuch as STL and boost

I These libraries come in handy when you are modeling at behavioral levelI Also since C++ has a much bigger user-base, these libraries are well-tested

and therefor are ideal for creating reference models

Getting Started with SystemC UVM SystemC Perspective 9 / 22

Cover i fyo

Generic Library

I Though SystemVerilog supports parameterized classes, it does notsupport function and operator overloading

I As a result, SystemVerilog lacks a generic algorithmic libraryI For example if you develop a sort function in systemverilog that works for

builtin number types, you can not generalize this function to work onuser-defined data types

I In comparison SystemC, since it is built over C++, has generic librariessuch as STL and boost

I These libraries come in handy when you are modeling at behavioral levelI Also since C++ has a much bigger user-base, these libraries are well-tested

and therefor are ideal for creating reference models

Getting Started with SystemC UVM SystemC Perspective 9 / 22

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In this section . . .

SystemC Perspective

UVM for SystemCUVM Constructs

Getting Started with SystemC UVM UVM for SystemC 10 / 22

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SystemC UVM Features

Configuration Global configuration object that records configuration for UVMcomponents even before they are constructed. Helpful forcreating object specific behaviour.

Factory Implementation of Abstract and Concrete factories in C++.Useful for transaction and component creation.

Packing Packer class implementation. Enables passing datatransactions between SystemC and SystemVerilog.

Phasing Enables synchronized build, configure, connect, run, reportoperations.

Connect Enables connections between SystemVerilog and SystemCcomponents.

Conversion Package for conversion between SystemC and SystemVerilogstandard data types.

Getting Started with SystemC UVM UVM for SystemC 11 / 22

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SystemC UVM Features

Configuration Global configuration object that records configuration for UVMcomponents even before they are constructed. Helpful forcreating object specific behaviour.

Factory Implementation of Abstract and Concrete factories in C++.Useful for transaction and component creation.

Packing Packer class implementation. Enables passing datatransactions between SystemC and SystemVerilog.

Phasing Enables synchronized build, configure, connect, run, reportoperations.

Connect Enables connections between SystemVerilog and SystemCcomponents.

Conversion Package for conversion between SystemC and SystemVerilogstandard data types.

Getting Started with SystemC UVM UVM for SystemC 11 / 22

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SystemC UVM Features

Configuration Global configuration object that records configuration for UVMcomponents even before they are constructed. Helpful forcreating object specific behaviour.

Factory Implementation of Abstract and Concrete factories in C++.Useful for transaction and component creation.

Packing Packer class implementation. Enables passing datatransactions between SystemC and SystemVerilog.

Phasing Enables synchronized build, configure, connect, run, reportoperations.

Connect Enables connections between SystemVerilog and SystemCcomponents.

Conversion Package for conversion between SystemC and SystemVerilogstandard data types.

Getting Started with SystemC UVM UVM for SystemC 11 / 22

Cover i fyo

SystemC UVM Features

Configuration Global configuration object that records configuration for UVMcomponents even before they are constructed. Helpful forcreating object specific behaviour.

Factory Implementation of Abstract and Concrete factories in C++.Useful for transaction and component creation.

Packing Packer class implementation. Enables passing datatransactions between SystemC and SystemVerilog.

Phasing Enables synchronized build, configure, connect, run, reportoperations.

Connect Enables connections between SystemVerilog and SystemCcomponents.

Conversion Package for conversion between SystemC and SystemVerilogstandard data types.

Getting Started with SystemC UVM UVM for SystemC 11 / 22

Cover i fyo

SystemC UVM Features

Configuration Global configuration object that records configuration for UVMcomponents even before they are constructed. Helpful forcreating object specific behaviour.

Factory Implementation of Abstract and Concrete factories in C++.Useful for transaction and component creation.

Packing Packer class implementation. Enables passing datatransactions between SystemC and SystemVerilog.

Phasing Enables synchronized build, configure, connect, run, reportoperations.

Connect Enables connections between SystemVerilog and SystemCcomponents.

Conversion Package for conversion between SystemC and SystemVerilogstandard data types.

Getting Started with SystemC UVM UVM for SystemC 11 / 22

Cover i fyo

SystemC UVM Features

Configuration Global configuration object that records configuration for UVMcomponents even before they are constructed. Helpful forcreating object specific behaviour.

Factory Implementation of Abstract and Concrete factories in C++.Useful for transaction and component creation.

Packing Packer class implementation. Enables passing datatransactions between SystemC and SystemVerilog.

Phasing Enables synchronized build, configure, connect, run, reportoperations.

Connect Enables connections between SystemVerilog and SystemCcomponents.

Conversion Package for conversion between SystemC and SystemVerilogstandard data types.

Getting Started with SystemC UVM UVM for SystemC 11 / 22

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Harnessing the UVM Factory

I UVM Components as well as SystemC models tend to be hierarchical innature

I Different components in a hierarchy are bound by ports and channelsI Ports and Channels form the interface of a component (or module)I Any other component (or module) that wants to access a given module,

does it through the interface

I Such structural models give rise to rigidityI A change in one module, disturbs all the modules that are bound to this

module

Getting Started with SystemC UVM UVM for SystemC 12 / 22

Cover i fyo

Harnessing the UVM Factory

I UVM Components as well as SystemC models tend to be hierarchical innature

I Different components in a hierarchy are bound by ports and channelsI Ports and Channels form the interface of a component (or module)I Any other component (or module) that wants to access a given module,

does it through the interface

I Such structural models give rise to rigidityI A change in one module, disturbs all the modules that are bound to this

module

Getting Started with SystemC UVM UVM for SystemC 12 / 22

Cover i fyo

Harnessing the UVM Factory

I UVM Components as well as SystemC models tend to be hierarchical innature

I Different components in a hierarchy are bound by ports and channelsI Ports and Channels form the interface of a component (or module)I Any other component (or module) that wants to access a given module,

does it through the interface

I Such structural models give rise to rigidityI A change in one module, disturbs all the modules that are bound to this

module

Getting Started with SystemC UVM UVM for SystemC 12 / 22

Cover i fyo

Harnessing the UVM Factory

I UVM Components as well as SystemC models tend to be hierarchical innature

I Different components in a hierarchy are bound by ports and channelsI Ports and Channels form the interface of a component (or module)I Any other component (or module) that wants to access a given module,

does it through the interface

I Such structural models give rise to rigidityI A change in one module, disturbs all the modules that are bound to this

module

Getting Started with SystemC UVM UVM for SystemC 12 / 22

Cover i fyo

Harnessing the UVM Factory

I UVM Components as well as SystemC models tend to be hierarchical innature

I Different components in a hierarchy are bound by ports and channelsI Ports and Channels form the interface of a component (or module)I Any other component (or module) that wants to access a given module,

does it through the interface

I Such structural models give rise to rigidityI A change in one module, disturbs all the modules that are bound to this

module

Getting Started with SystemC UVM UVM for SystemC 12 / 22

Cover i fyo

Harnessing the UVM Factory

I UVM Components as well as SystemC models tend to be hierarchical innature

I Different components in a hierarchy are bound by ports and channelsI Ports and Channels form the interface of a component (or module)I Any other component (or module) that wants to access a given module,

does it through the interface

I Such structural models give rise to rigidityI A change in one module, disturbs all the modules that are bound to this

module

Getting Started with SystemC UVM UVM for SystemC 12 / 22

Cover i fyo

Harnessing the UVM Factory

I In UVM testbenches and in SystemC models, the problem is compundedby availability of various forms of comonents modeled at differentabstraction levels

I For example various models may be available for a given component,including:

I untimedI loosely timeI cycle accurateI a combination

Getting Started with SystemC UVM UVM for SystemC 13 / 22

Cover i fyo

Harnessing the UVM Factory

I In UVM testbenches and in SystemC models, the problem is compundedby availability of various forms of comonents modeled at differentabstraction levels

I For example various models may be available for a given component,including:

I untimedI loosely timeI cycle accurateI a combination

Getting Started with SystemC UVM UVM for SystemC 13 / 22

Cover i fyo

Harnessing the UVM Factory

I In UVM testbenches and in SystemC models, the problem is compundedby availability of various forms of comonents modeled at differentabstraction levels

I For example various models may be available for a given component,including:

I untimedI loosely timeI cycle accurateI a combination

componentA

componentB

componentC

Getting Started with SystemC UVM UVM for SystemC 13 / 22

Cover i fyo

Harnessing the UVM Factory

I In UVM testbenches and in SystemC models, the problem is compundedby availability of various forms of comonents modeled at differentabstraction levels

I For example various models may be available for a given component,including:

I untimedI loosely timeI cycle accurateI a combination

componentA

componentB

componentC

Getting Started with SystemC UVM UVM for SystemC 13 / 22

Cover i fyo

Harnessing the UVM Factory

I In UVM testbenches and in SystemC models, the problem is compundedby availability of various forms of comonents modeled at differentabstraction levels

I For example various models may be available for a given component,including:

I untimedI loosely timeI cycle accurateI a combination

componentA

componentB

componentC

Getting Started with SystemC UVM UVM for SystemC 13 / 22

Cover i fyo

Harnessing the UVM Factory

I In UVM testbenches and in SystemC models, the problem is compundedby availability of various forms of comonents modeled at differentabstraction levels

I For example various models may be available for a given component,including:

I untimedI loosely timeI cycle accurateI a combination

componentA

componentB

componentC

Getting Started with SystemC UVM UVM for SystemC 13 / 22

Cover i fyo

Harnessing the UVM Factory

I The OOP paradigm comes to our rescue here, in form of polymorphism

I OOP principles tell us notto program to theimplementation

I Instead program to theinterfaces, we are told

Getting Started with SystemC UVM UVM for SystemC 14 / 22

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Harnessing the UVM Factory

I The OOP paradigm comes to our rescue here, in form of polymorphism

I OOP principles tell us notto program to theimplementation

I Instead program to theinterfaces, we are told Component C Package

Component B Package

Component A Package

UVMcomponent A

component Aservice

UVMcomponent B

UVMcomponent B

UVMcomponent B

component Bservice

UVMcomponent B

UVMcomponent B

UVMcomponent C

Getting Started with SystemC UVM UVM for SystemC 14 / 22

Cover i fyo

Harnessing the UVM Factory

I The OOP paradigm comes to our rescue here, in form of polymorphism

I OOP principles tell us notto program to theimplementation

I Instead program to theinterfaces, we are told Component C Package

Component B Package

Component A Package

UVMcomponent A

component Aservice

UVMcomponent B

UVMcomponent B

UVMcomponent B

component Bservice

UVMcomponent B

UVMcomponent B

UVMcomponent C

Getting Started with SystemC UVM UVM for SystemC 14 / 22

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Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

Cover i fyo

Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

Cover i fyo

Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

Cover i fyo

Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

Cover i fyo

Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

Cover i fyo

Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

Comp B<<interface>>

Comp A<<creates>>

Comp BLoosely Timed

Comp BCycle Accurate

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

Cover i fyo

Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

Comp B<<interface>>

Comp A<<creates>>

Comp BLoosely Timed

Comp BCycle Accurate

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

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Harnessing the UVM Factory

I Logical application of OOP paradigm makes our code independent of theimplementation details – instead the compenents are now bound to aninterface (virtual base class)

I Polymorphism ROCKS, but whoa, does it really work all the time:

Comp B<<interface>>

Comp A<<creates>>

Comp BLoosely Timed

Comp BCycle Accurate

I While all other methods (classfunctions) can be made virtual, theconstructor can not be

I As a result, at the time of creating thecomponent, a particularimplementation has to be specified

I Object generation spoils much of whatpolymorphism had to offer

Getting Started with SystemC UVM UVM for SystemC 15 / 22

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Harnessing the UVM Factory

I This is exactly where UVM Factory comes to our rescue:I UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

I UVM (concrete) Factory is a globalsingleton object

I Base classes as well as derived classesare registered with the global factory

I Configuration interface is provided for anybase class, so that when you create anobject of the base class, the actual objectcreated is for a derived class as per theconfiguration

Getting Started with SystemC UVM UVM for SystemC 16 / 22

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Harnessing the UVM Factory

I This is exactly where UVM Factory comes to our rescue:I UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

I UVM (concrete) Factory is a globalsingleton object

I Base classes as well as derived classesare registered with the global factory

I Configuration interface is provided for anybase class, so that when you create anobject of the base class, the actual objectcreated is for a derived class as per theconfiguration

Getting Started with SystemC UVM UVM for SystemC 16 / 22

Cover i fyo

Harnessing the UVM Factory

I This is exactly where UVM Factory comes to our rescue:I UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

I UVM (concrete) Factory is a globalsingleton object

I Base classes as well as derived classesare registered with the global factory

I Configuration interface is provided for anybase class, so that when you create anobject of the base class, the actual objectcreated is for a derived class as per theconfiguration

Comp B<<interface>>

Comp B

Comp A

UVM Factory<<interface>>

UVM Factory

+ create()

Loosely Timed

Comp BCycle Accurate

Getting Started with SystemC UVM UVM for SystemC 16 / 22

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Harnessing the UVM Factory

I This is exactly where UVM Factory comes to our rescue:I UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

I UVM (concrete) Factory is a globalsingleton object

I Base classes as well as derived classesare registered with the global factory

I Configuration interface is provided for anybase class, so that when you create anobject of the base class, the actual objectcreated is for a derived class as per theconfiguration

Comp B<<interface>>

Comp B

Comp A

UVM Factory<<interface>>

UVM Factory

+ create()

Loosely Timed

Comp BCycle Accurate

Getting Started with SystemC UVM UVM for SystemC 16 / 22

Cover i fyo

Harnessing the UVM Factory

I This is exactly where UVM Factory comes to our rescue:I UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

I UVM (concrete) Factory is a globalsingleton object

I Base classes as well as derived classesare registered with the global factory

I Configuration interface is provided for anybase class, so that when you create anobject of the base class, the actual objectcreated is for a derived class as per theconfiguration

Comp B<<interface>>

Comp B

Comp A

UVM Factory<<interface>>

UVM Factory

+ create()

Loosely Timed

Comp BCycle Accurate

Getting Started with SystemC UVM UVM for SystemC 16 / 22

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UVM Phases

SystemC has only a few phases. In contrast, UVM has a very elaborate phasesequence.

VerilogElaboration

UVM Build Phase

SystemCElaboration

UVM Connect Phase

End of Elaboration

End of Elaboration

Start of Simulation

Start of Simulation

UVM Run Phase Simulation Run

UVM Extract Phase

UVM Check Phase

UVM Report Phase

End of Simulation

I Note that Start of Elaboration andStart of Simulation etc are PLIhooks in Verilog and similarly arefunction hooks in SystemC

I The Build and Connect phase inUVM happen at ZERO simulationtime

Getting Started with SystemC UVM UVM for SystemC 17 / 22

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UVM Phases

SystemC has only a few phases. In contrast, UVM has a very elaborate phasesequence.

VerilogElaboration

UVM Build Phase

SystemCElaboration

UVM Connect Phase

End of Elaboration

End of Elaboration

Start of Simulation

Start of Simulation

UVM Run Phase Simulation Run

UVM Extract Phase

UVM Check Phase

UVM Report Phase

End of Simulation

I Note that Start of Elaboration andStart of Simulation etc are PLIhooks in Verilog and similarly arefunction hooks in SystemC

I The Build and Connect phase inUVM happen at ZERO simulationtime

Getting Started with SystemC UVM UVM for SystemC 17 / 22

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Configuring a Build

I Not all the instances of a class(UVM Component) may be exactlysame in behaviour

I There may be a need to configurea UVM Component

I Often, it might be useful to build aUVM component while takingsome configuration parametersinto account

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

GlobalMemory

GlobalIO

GlobalIO

Figure: Asymmetric Architecture

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Configuring a Build

I Not all the instances of a class(UVM Component) may be exactlysame in behaviour

I There may be a need to configurea UVM Component

I Often, it might be useful to build aUVM component while takingsome configuration parametersinto account

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

GlobalMemory

GlobalIO

GlobalIO

Figure: Asymmetric Architecture

Getting Started with SystemC UVM UVM for SystemC 18 / 22

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Configuring a Build

I Not all the instances of a class(UVM Component) may be exactlysame in behaviour

I There may be a need to configurea UVM Component

I Often, it might be useful to build aUVM component while takingsome configuration parametersinto account

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

ProcessorMaster

RoutingNode

GlobalMemory

GlobalIO

GlobalIO

Figure: Asymmetric Architecture

Getting Started with SystemC UVM UVM for SystemC 18 / 22

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Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configurationparameters in the build phase

I The parameters are tied with the hierarchical name of the componentbeing built. This is useful for enabling instance-specific custom behaviourfor a component.

Caveat Note that the configuration object needs the same fields on ptheconfigure and component side.

I This results in a strong binding (in the software sense).I Sometimes it results in confusing situations (because of

typos in the configure parameters).

Use with care

Getting Started with SystemC UVM UVM for SystemC 19 / 22

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Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configurationparameters in the build phase

I The parameters are tied with the hierarchical name of the componentbeing built. This is useful for enabling instance-specific custom behaviourfor a component.

Caveat Note that the configuration object needs the same fields on ptheconfigure and component side.

I This results in a strong binding (in the software sense).I Sometimes it results in confusing situations (because of

typos in the configure parameters).

Use with care

Getting Started with SystemC UVM UVM for SystemC 19 / 22

Cover i fyo

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configurationparameters in the build phase

I The parameters are tied with the hierarchical name of the componentbeing built. This is useful for enabling instance-specific custom behaviourfor a component.

Caveat Note that the configuration object needs the same fields on ptheconfigure and component side.

I This results in a strong binding (in the software sense).I Sometimes it results in confusing situations (because of

typos in the configure parameters).

Use with care

Getting Started with SystemC UVM UVM for SystemC 19 / 22

Cover i fyo

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configurationparameters in the build phase

I The parameters are tied with the hierarchical name of the componentbeing built. This is useful for enabling instance-specific custom behaviourfor a component.

Caveat Note that the configuration object needs the same fields on ptheconfigure and component side.

I This results in a strong binding (in the software sense).I Sometimes it results in confusing situations (because of

typos in the configure parameters).

Use with care

Getting Started with SystemC UVM UVM for SystemC 19 / 22

Cover i fyo

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configurationparameters in the build phase

I The parameters are tied with the hierarchical name of the componentbeing built. This is useful for enabling instance-specific custom behaviourfor a component.

Caveat Note that the configuration object needs the same fields on ptheconfigure and component side.

I This results in a strong binding (in the software sense).I Sometimes it results in confusing situations (because of

typos in the configure parameters).

Use with care

Getting Started with SystemC UVM UVM for SystemC 19 / 22

Cover i fyo

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configurationparameters in the build phase

I The parameters are tied with the hierarchical name of the componentbeing built. This is useful for enabling instance-specific custom behaviourfor a component.

Caveat Note that the configuration object needs the same fields on ptheconfigure and component side.

I This results in a strong binding (in the software sense).I Sometimes it results in confusing situations (because of

typos in the configure parameters).

Use with care

Getting Started with SystemC UVM UVM for SystemC 19 / 22

Cover i fyo

UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

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UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

Cover i fyo

UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

Cover i fyo

UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

Cover i fyo

UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

Cover i fyo

UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

Cover i fyo

UVM Transactions

I UVM-SC library provides a base class for creating a transaction (calledsequence item in UVM)

I The UVM-SC implementation lacks CPP macros to automatically createvirtual methods for print, pack, unpack, copy and compare operations

I UVM-SC makes it mendatory for the user to implement these functionsI A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factoryI UVM-SC depends on the pack/unpack operations to send transactions

across the language boundariesI A user must make sure that pack/unpack methods for the transaction

class in SystemC and SystemVerilog remain in sync

Caveat When you pack data in SystemVerilog or in SystemC, you loosethe control bits for any 4-valued logic data.

Getting Started with SystemC UVM UVM for SystemC 20 / 22

Cover i fyo

UVM Connect Library

I The UVM Connect package from Mentor Graphics is built on top ofUVM-SC package by Cadence

I It provides an opensource implementation for connecting SystemVerilogand SystemC ports

I Also implements conversion between standard SystemC andSystemVerilog data types

I UVMC package does not require you to create a UVM transaction on theSystemC side

I Instead it provides macros to automatically define the pack/unpackfunctionality on SystemC side

I Since these macros define functions (not class methods) for thepack/unpack functionality, UVMC does not bind your SystemC transactionclass to any base class

Getting Started with SystemC UVM UVM for SystemC 21 / 22

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UVM Connect Library

I The UVM Connect package from Mentor Graphics is built on top ofUVM-SC package by Cadence

I It provides an opensource implementation for connecting SystemVerilogand SystemC ports

I Also implements conversion between standard SystemC andSystemVerilog data types

I UVMC package does not require you to create a UVM transaction on theSystemC side

I Instead it provides macros to automatically define the pack/unpackfunctionality on SystemC side

I Since these macros define functions (not class methods) for thepack/unpack functionality, UVMC does not bind your SystemC transactionclass to any base class

Getting Started with SystemC UVM UVM for SystemC 21 / 22

Cover i fyo

UVM Connect Library

I The UVM Connect package from Mentor Graphics is built on top ofUVM-SC package by Cadence

I It provides an opensource implementation for connecting SystemVerilogand SystemC ports

I Also implements conversion between standard SystemC andSystemVerilog data types

I UVMC package does not require you to create a UVM transaction on theSystemC side

I Instead it provides macros to automatically define the pack/unpackfunctionality on SystemC side

I Since these macros define functions (not class methods) for thepack/unpack functionality, UVMC does not bind your SystemC transactionclass to any base class

Getting Started with SystemC UVM UVM for SystemC 21 / 22

Cover i fyo

UVM Connect Library

I The UVM Connect package from Mentor Graphics is built on top ofUVM-SC package by Cadence

I It provides an opensource implementation for connecting SystemVerilogand SystemC ports

I Also implements conversion between standard SystemC andSystemVerilog data types

I UVMC package does not require you to create a UVM transaction on theSystemC side

I Instead it provides macros to automatically define the pack/unpackfunctionality on SystemC side

I Since these macros define functions (not class methods) for thepack/unpack functionality, UVMC does not bind your SystemC transactionclass to any base class

Getting Started with SystemC UVM UVM for SystemC 21 / 22

Cover i fyo

UVM Connect Library

I The UVM Connect package from Mentor Graphics is built on top ofUVM-SC package by Cadence

I It provides an opensource implementation for connecting SystemVerilogand SystemC ports

I Also implements conversion between standard SystemC andSystemVerilog data types

I UVMC package does not require you to create a UVM transaction on theSystemC side

I Instead it provides macros to automatically define the pack/unpackfunctionality on SystemC side

I Since these macros define functions (not class methods) for thepack/unpack functionality, UVMC does not bind your SystemC transactionclass to any base class

Getting Started with SystemC UVM UVM for SystemC 21 / 22

Cover i fyo

UVM Connect Library

I The UVM Connect package from Mentor Graphics is built on top ofUVM-SC package by Cadence

I It provides an opensource implementation for connecting SystemVerilogand SystemC ports

I Also implements conversion between standard SystemC andSystemVerilog data types

I UVMC package does not require you to create a UVM transaction on theSystemC side

I Instead it provides macros to automatically define the pack/unpackfunctionality on SystemC side

I Since these macros define functions (not class methods) for thepack/unpack functionality, UVMC does not bind your SystemC transactionclass to any base class

Getting Started with SystemC UVM UVM for SystemC 21 / 22

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Thank You!