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Synchronous Digital Hierarchy Muhammad Zeeshan Frame Structure, Overheads and Pointers

Synchronous Digital Hierarchy

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Page 1: Synchronous Digital Hierarchy

Synchronous Digital Hierarchy

Synchronous Digital Hierarchy

Muhammad Zeeshan

Frame Structure, Overheads and Pointers

Page 2: Synchronous Digital Hierarchy

2

SDH Overview

SDH Frame Structure

SDH Multiplexing

Overhead

Pointers

Page 3: Synchronous Digital Hierarchy

SDH OVERVIEW

Page 4: Synchronous Digital Hierarchy

4

SDH – Definition

Synchronous Digital Hierarchy (SDH) is a standard

which is developed by the International

Telecommunication Union (ITU)

It is documented in standard G.707 and its extension G.708

It was developed to replace the Plesiochronous Digital

Hierarchy (PDH) system for transporting large amounts of

telephone and data traffic and to allow for interoperability

between equipment from different vendors

Page 5: Synchronous Digital Hierarchy

5

Limitation of PDH

INTERFACES:

Electrical interfaces

There are only regional standards, instead of universal standards

Optical interfaces

No unified standards for optical line equipments, manufacturers

develop equipment according to their own standards

Page 6: Synchronous Digital Hierarchy

6

PDH: the electric interface is a standard interface, but the optical interface is not a standard interface

Special PDH optical signal

Manufacturer

A

Manufacturer

B

Standard electric interface

2Mbit/s or 34Mbit/s

PDH Network

Manufacturer

B

Standardization of optical interface

Page 7: Synchronous Digital Hierarchy

7

Limitations of PDH

MULTIPLEXING METHOD:

Asynchronous Multiplexing

Code rate justification is required for matching and

accepting clock difference

The locations of the low-rate signals in high-rate signals

are not regular nor fixed

Page 8: Synchronous Digital Hierarchy

8

European Series

565Mb/s565Mb/s

139Mb/s139Mb/s

34Mb/s34Mb/s

8Mb/s8Mb/s

2Mb/s2Mb/s

×4

×4

×4

×4

Japanese Series North American Series

1.6Gb/s1.6Gb/s

400Mb/s400Mb/s

100Mb/s100Mb/s

32Mb/s32Mb/s

6.3Mb/s6.3Mb/s

1.5Mb/s1.5Mb/s

274Mb/s274Mb/s

45Mb/s45Mb/s

6.3Mb/s6.3Mb/s

×4×4

×4

×4

×6

×7

×3

×5

64Kb/s64Kb/s

×24 ×30

×3

×3

Limitations of PDH

Page 9: Synchronous Digital Hierarchy

9

Limitations of PDH

140/34 Mb/s 34/140Mb/s

34/8 Mb/s 8/34 Mb/s

8/2 Mb/s 2/8 Mb/s

2 Mb/s

Optical/Electrical Electrical/Optical

multiplexingdemultipexing

Adding and Dropping in PDH

Page 10: Synchronous Digital Hierarchy

10

Limitations of PDH

OPERATION & MAINTENANCE (OAM)

PDH signal frame structure has very few overhead bytes

for Operation, Administration, and Maintenance (OAM)

NETWORK MANAGEMENT INTERFACE

No universal network management interface for PDH

network

Page 11: Synchronous Digital Hierarchy

11

Advantages of SDH over PDH

INTERFACE

Electrical interfaces

SDH provides a set of standard rate levels----STM-N.

(N= 4n =1, 4, 16, 64……).

The basic signal transmission structure level is STM-1, at a rate of

155Mb/s

Optical interfaces

Optical interfaces adopt universal standards. Line coding of SDH

signals involves scrambling, instead of inserting redundancy codes

Page 12: Synchronous Digital Hierarchy

12

SDH Network

Standard optical interface

Uniform STM-N optical signal

Manufacturer

A

Manufacturer

B

Standardization of optical interface

SDH has standard optical interface

Page 13: Synchronous Digital Hierarchy

13

Advantages of SDH over PDH

MULTIPLEXING METHOD

Low-rate SDH signals → high-rate SDH

Signals via byte interleaved multiplexing method

PDH signals → SDH

Synchronous multiplexing method and flexible mapping structure

Page 14: Synchronous Digital Hierarchy

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STM-256

STM-64

STM-16

STM-4

STM-1

×4

×4

×4

×4

STM-1, 2, 34, 140 Mb/s

STM-N

×N

SDH Multiplexing

Page 15: Synchronous Digital Hierarchy

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SDH SignalsSDH Signals Bit rate(Mb/s)Bit rate(Mb/s)

STM-1STM-1 155.520 or 155M155.520 or 155M

STM-4STM-4 622.080 or 622M622.080 or 622M

STM-16STM-16 2488.320 or 2.5G2488.320 or 2.5G

STM-64STM-64 9953.280 or 10G9953.280 or 10G

SDH higher-rate signal (STM-4,16,64) is exactly 4 times that

of the lower-rate signal (STM-1)

STM: Synchronous Transport Module

SDH Signals and Data Rates

Page 16: Synchronous Digital Hierarchy

16

ADM155Mbit/s

Optical interface

155Mbit/s

Optical interface

2Mbit/s

Electric signal

SDH: Economical and easy way for network!

Adding and dropping in SDH

Page 17: Synchronous Digital Hierarchy

17

Advantages of SDH over PDH

OPERATION & MAINTENANCE

Abundant overhead bits are used for OAM.

Unnecessary to add redundancy bits to monitor line

performance during line coding

COMPATIBILITY

SDH network and the existing PDH network can work

together

SDH network can accommodate the signals of other hierarchies

such as ATM, FDDI, and Ethernet

Page 18: Synchronous Digital Hierarchy

SDH FRAME STRUCTURE

Page 19: Synchronous Digital Hierarchy

19

STM-N Frame Structure

For the convenience of signal analysis, the frame

structures of the signals are often illustrated as block

frame structures

The frame structure of PDH signals, ATM signals and

data packets of IP network are also block frames

The frame of E1 signals is a block frame of 1 Rows x

32 Columns consisting of 32 Bytes

Page 20: Synchronous Digital Hierarchy

20

RSOHRSOH

MSOHMSOH

11

33

44

55

99

STM-N payloadSTM-N payload

(including POH)(including POH)

99 261261

270 Columns270 Columns

9 Rows9 Rows

P P O O HH

AU-PTRAU-PTR

RSOH: Regenerator Section OverheadRSOH: Regenerator Section OverheadMSOH: Multiplex Section OverheadMSOH: Multiplex Section OverheadPOH: Path OverheadPOH: Path OverheadAUPTR: Administrative Unit PointerAUPTR: Administrative Unit Pointer

125 125 μμssSTM-1 Frame Structure

Page 21: Synchronous Digital Hierarchy

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RSOHRSOH

MSOHMSOH

11

33

44

55

99

STM-N payloadSTM-N payload

(including POH)(including POH)

9×N9×N 261×N261×N

270×N 270×N

ColumnsColumns

9 Rows9 Rows

P P O O HH

AU-PTRAU-PTR

RSOH: Regenerator Section OverheadRSOH: Regenerator Section OverheadMSOH: Multiplex Section OverheadMSOH: Multiplex Section OverheadPOH: Path OverheadPOH: Path OverheadAUPTR: Administrative Unit PointerAUPTR: Administrative Unit Pointer

STM-N Frame Structure125 125 μμss

Page 22: Synchronous Digital Hierarchy

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SDH Frame Structure - ANATOMY

Transmission rate of single byte of STM-N frame:

STM-N frame contains 2430xN Bytes and each frame is

transmitted every 125 μs

That means a given byte is transmitted 8000 times a second

Transmission rate of a single byte:

8000 x 8 = 64 Kbps

Transmission rate of a STM-1 frame:

9 rows x 270 columns x 8000 frames/s x 8 bits = 15,55,20,000 bps

= 155.52 Mbps

Page 23: Synchronous Digital Hierarchy

23

11

21612161

270270

24302430

271271 540540

1st Byte of 1st Byte of

STM frame # 1STM frame # 1Last byte of Last byte of

STM frame # 1STM frame # 1

STM-1 Frame # 1STM-1 Frame # 1 1st Byte1st Byte

STM STM Frame # 2Frame # 2

Transmission Mode: Byte-by-Byte, Transmission Mode: Byte-by-Byte,

From Left to right & top to bottomFrom Left to right & top to bottom

Transmission DirectionTransmission Direction

1st 1st

ByteByte

24302430thth

ByteByte

STM-1 Frame Transmission

Page 24: Synchronous Digital Hierarchy

24

SDH Frame Structure

Payload – area for services transmission in STM-N

2M, 34M, and 140M signals are packed and carried

in the payload of STM-N frame over SDH network

Path Overhead (POH) – after packing low rate

signals, POH is added for OAM of every frame

Page 25: Synchronous Digital Hierarchy

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SDH Frame Structure

Section Overhead (SOH) – monitors the whole STM-

N frame

Regenerator Section Overhead (RSOH) – monitors the

whole STM-N frame.

Multiplex Section Overhead (MSOH) – monitors each

STM-1 of the STM-N frame.

RSOH, MSOH, and POH compose the integrated

monitoring system of SDH.

Page 26: Synchronous Digital Hierarchy

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SDH Network – NE Types

Terminal Multiplexer (TM)

Add/Drop Multiplexer (ADM)

Regenerator (REG)

Page 27: Synchronous Digital Hierarchy

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Regenerator

Regenerator has the job of regenerating the clock and amplitude

relationships of the incoming data signals that have attenuated

and distorted by dispersion

The regenerator replaces the RSOH bytes before re-transmitting

the signal

RegeneratorSTM-N STM-N

Page 28: Synchronous Digital Hierarchy

28

Terminal Multiplexer

Terminal multiplexers are used to combine

plesiochronous and synchronous input signals into

higher bit rate STM-N signals

Terminal Multiplexer

PDH

SDH STM-N

Page 29: Synchronous Digital Hierarchy

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Add / Drop Multiplexer

PDH and SDH signals can be extracted from or

inserted into high speed SDH bit streams by means of

ADMs

Add / Drop Multiplexer

PDHSDH

STM-N

Towards other NEs

Customers

IPATM

STM-N

Towards other NEs

Page 30: Synchronous Digital Hierarchy

30

Sections in the SDH Network

There are three sections in the SDH

Path

Multiplex Section

Regenerator Section

The overheads are always generated at the beginning of a

section and only evaluated at the end of a section

Terminal Multiplexer

Add/Drop Multiplexer

Terminal Multiplexer

REG REG REG

Path

Multiplex Section

Regenerator Section

Page 31: Synchronous Digital Hierarchy

31

Payload

Path

Section

Optical

Payload

Path

Section

OpticalOptical Fiber Cable

RSOH

MSOH

POH

Overhead Layer

Page 32: Synchronous Digital Hierarchy

32

How to understand SOH and POH?

Both SOH and POH are OAM bytes added to ensure correct and

flexible transmission of signals

SOH and POH are used in different layers to supervise and

administrate the signals. RSOH and MSOH are used in RS and MS

separately, but HPOH and LPOH are used for VC-3/VC4 and VC12

LPOH----used to supervise small package (VC-12)

HPOH----used to supervise big package (VC-3 / VC-4)

MSOH----used to supervise the “carriage”(STM-1) of the “truck”

RSOH----used to supervise the motorcade formed by trucks (STM-4/16/64)

Page 33: Synchronous Digital Hierarchy

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SDH Frame Structure

AU Pointer (AU-PTR)

Used for alignment of lower rate signals in the payload of STM-N

frame to accurately locate the payload

AU-PTR is added in transmitting end, when the signal is packed

into the payload of STM-N frame

At receiving end, the low rate signal is dropped from STM-N

frame according to the AU-PTR value

Low-rate signals in the STM frame are arranged obeying some

rules – byte interleave; so only have to locate the first low-rate

signal in the STM frame

Page 34: Synchronous Digital Hierarchy

SDH MULTIPLEXING

Page 35: Synchronous Digital Hierarchy

35

SDH Multiplexing

SDH Multiplexing includes:Low to high rate SDH signals (STM-1 STM-N)

PDH to SDH signals (2M, 34M & 140M STM-N)

Other hierarchy signals to SDH Signals (ATM STM-N)

Page 36: Synchronous Digital Hierarchy

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SDH Multiplexing Structure

STM-1 AU-4

TU-3

AUG-1

TUG-3 VC-3 C-3

VC-4 C-4

TU-12 VC-12 C-12

TUG-2

×1 ×1

×3

×1

×7

×3

139264 kbit/s

34368 kbit/s

2048 kbit/s

Pointer processing

Multiplexing

Mapping

Aligning

AUG-4

AUG-16

AUG-64

STM-4

STM-16

STM-64

×1

×1

×1

×4

×4

×4

Page 37: Synchronous Digital Hierarchy

37

Mapping, Aligning and MultiplexingLow-rate tributaries are multiplexed into STM-N signals through three procedures:

Mapping

Aligning

Multiplexing.

MAPPING

SDH mapping  is a procedure by which tributaries are adapted into virtual containers at the

boundary of an SDH network, for example, E1 into VC-12, E3 into VC-3, E4 into VC-4.

ALIGNING

SDH aligning is a procedure by which the frame-offset information is incorporated into the

tributary unit, by adding a pointer

The pointer value constantly locates the start point of the VC frame within the payload, so that

the receiving end can correctly separate the corresponding VC

MULTIPLEXING

SDH multiplexing is the procedure by which multiple lower order path layer signals are adapted

into a higher order path

Page 38: Synchronous Digital Hierarchy

38

Multiplexing Structure

C: ContainerVC: Virtual ContainerTU: Tributary UnitTUG: Tributary Unit GroupAU: Administrative UnitAUG: Administrative Unit Group

Page 39: Synchronous Digital Hierarchy

39

2 Mb Signal Mapping Procedure

C–12

Rate Adaptation

2 Mbps Signal

1 4

1

9

125 μs

1 Byte Path Overhead

(POH)

1 4

1

9

VC–12

C-12 Size: (9 Rows x 4 Columns) – 2 = 34 Bytes

C–12

POH

VC-12 Size: (9 Rows x 4 Columns) – 1 = 35 Bytes

125 μs

VC-12 = C-12 + (1 Byte POH)

C-12 Frame Duration = 125 μs

VC-12 Frame Duration = 125 μs

There can be four different POH bytes for one C-12 V5, J2, N2, K4

MAPPING

Page 40: Synchronous Digital Hierarchy

40

2 Mb Signal Mapping Procedure

Multiplexing x 3

1 12

1

9

TUG–2

T

U

-

12

125 μs

1 4

1

9

VC–12

C–12

POH

125 μs

1 Byte Tributary Unit Pointer (TU-

PTR) 1 4TU–12

C–12

POH

125 μs

PTR

T

U

-

12

T

U

-

12

TUG-2 size: (9 Rows x 12 Columns) = 108 Bytes

TU-12 Size : (9 Rows x 12 Columns) = 36 Bytes

TU-12 = VC-12 + (1 Byte TU-PTR)

TUG-2 = TU-12 + TU-12 + TU-12

TU-12 and TUG-2 Frame Duration = 125 μs

ALIGNING MULTIPLEXING

Page 41: Synchronous Digital Hierarchy

41

RR

2 Mb Signal Mapping Procedure

1 12

1

9

TUG–2

T

U

-

12

125 μs

T

U

-

12

T

U

-

12

Multiplexing x 7

1 86

1

9

TUG–3

125 μs

T

U

G

-

2

T

U

G

-

2

T

U

G

-

2

T

U

G

-

2

T

U

G

-

2

T

U

G

-

2

T

U

G

-

2

TUG-3 Size = (TUG-2) x 7 + R (2 Columns)

TUG-3 Frame Duration = 125 μs

Page 42: Synchronous Digital Hierarchy

42

2 Mb Signal Mapping Procedure

1 86

1

9

TUG–3

125 μs

Multiplexing x 3

R

P

O

H

1 261

1

9

VC–4

125 μs

T

U

G

-

3

T

U

G

-

3

T

U

G

-

3

R

VC-4 = TUG-3 + TUG-3 + TUG-3 + R (2 Columns) + POH (1 Column)

VC-4 Frame Size = 9 Rows x 261 Columns = 2349 Bytes

VC-4 Frame Duration = 125 μs

Page 43: Synchronous Digital Hierarchy

43

VC–4

2 Mb Signal Mapping Procedure

1 2611

9

125 μs

AU-PTR

AU–4

VC–4

1 2701

9

125 μs

AUG1 2701

9

125 μs

STM-11 2701

9

125 μs

Multiplexing x 1

RSOH and MSOH

AU-PTR

VC–4AU-PTR

VC–4AU-PTR

MSOH

RSOH

2 Mb Multiplexing Route

2 Mb C-12 VC-12 TU-12 TG-2 TG-3 VC-4 AU-4 AUG STM-1

Page 44: Synchronous Digital Hierarchy

44

34 Mb Signal Mapping Procedure

C–3

Rate Adaptation

34 Mbps Signal

1 84

1

9

125 μs

Path Overhead

(POH)

C–3

1 85

1

9

125 μs

P

O

H

VC–3

C-3 Frame Size: 9 rows x 84 columns = 756 Bytes

C-3 Frame Duration: 125 μs

VC-3 = C-3 + (POH) POH = 9 Rows x 1 Column = 9 Byte

VC-3 Frame Size: 9 Rows x 85 Columns = 765 Bytes

VC-3 Frame Duration: 125 μs

Page 45: Synchronous Digital Hierarchy

45

34 Mb Signal Mapping Procedure

VC–3

Tributary Unit Pointer

1 86

1

9

125 μs

Fixed Stuffing Bits

1 86

1

9

125 μs

TU–3

H1H2H3

R

TUG–3TU–3H1H2H3

TU-3 = VC-3 + TU-PTR TU-PTR = 3 Byte Pointer (H1, H2 and H3)

TUG-3 = TU-3 + R (Fixed Stuffing

Bits)

R (Fixed Stuffing Bits) = 6 Bytes (Fixed Stuffing Bits)

TU-3 and TUG-3 Frame Duration = 125 μs

STUFFING

Page 46: Synchronous Digital Hierarchy

46

34 Mb Signal Mapping Procedure

T

U

G

3

1 261

1

9

125 μs

P

O

H

R R

VC–4Multiplexing

x 3

TU–3

1 86

1

9

125 μs

H1H2H3

R

TUG–3

VC-4 = TUG-3 + TUG-3 + TUG-3 + R (2 Columns) + POH (1 Column)

VC-4 Frame Size = 9 Rows x 261 Columns = 2349 Bytes

VC-4 Frame Duration = 125 μs

T

U

G

3

T

U

G

3

Page 47: Synchronous Digital Hierarchy

47

VC–4

34 Mb Signal Mapping Procedure

1 2611

9

125 μs

AU-PTR

AU–4

VC–4

1 2701

9

125 μs

AUG1 2701

9

125 μs

STM-11 2701

9

125 μs

Multiplexing x 1

RSOH and MSOH

AU-PTR

VC–4AU-PTR

VC–4AU-PTR

MSOH

RSOH

34 Mb Multiplexing Route

34 Mb C-3 VC-3 TU-3 TUG-3 VC-4 AU-4 AUG STM-1

Page 48: Synchronous Digital Hierarchy

48

VC-4 = C-4 + (POH) POH = 9 Rows x 1 Column = 9 Byte

VC-4 Frame Size: 9 Rows x 261 Columns = 2349 Bytes

140 Mb Signal Mapping Procedure

C–4

Rate Adaptation

140 Mbps Signal

1 260

1

9

125 μs

C-4 Frame Size: 9 rows x 260 columns = 2340 Bytes

C-4 Frame Duration: 125 μs

Path Overhead

(POH)

C–4

1 261

1

9

125 μs

P

O

H

VC–4

Rate Adaptation: The process of “Bit stuffing”, to account for different clock rates of the signals coming from different sources

Page 49: Synchronous Digital Hierarchy

49

140 Mb Signal Mapping Procedure

VC–4

AU-PTR

10 2701

9

125 μs

Multiplexing x 1

AU-PTR

AU-PTR: A 9 byte pointer is inserted at Row No 4

AU–4 Size: (1x9)+(9x261) = 2358 Bytes

1 9

A U – 4

10 2701

9

125 μs

1 9

AU–4 AUG–4

In case of 140 Mb signal mapping in STM-1, AU-4 and AUG are identical

AU-4 and AUG Frame Duration: 125 μs

4

Page 50: Synchronous Digital Hierarchy

50

140 Mb Signal Mapping Procedure

STM-1

RSOH and MSOH

1 270

1

9

125 μs

A U – 4

10 2701

9

125 μs

1 9

RSOH

MSOH

AUG–4

RSOH Size: 3 Rows x 9 Columns = 27 Bytes

MSOH Size: 5 Rows x 9 Columns = 45 Bytes

STM-1 Size: 9 Rows x 270 Columns = 2430 Bytes

STM-1 Frame Size: 125 μs

3

5

A U – 4

270

125 μs

1AUG–4

Page 51: Synchronous Digital Hierarchy

OVERHEADS

Page 52: Synchronous Digital Hierarchy

52

Overhead Bytes

270

1

9

STM-1 Frame Structure

RSOH

MSOH

AU-PTRP

O

H

OVERHEAD

1

PAYLOAD

Page 53: Synchronous Digital Hierarchy

53

Section Overhead (SOH)

Overhead in SDH frame structure are classified as:

Section Overhead SOH

Path Overhead POH

SOH is further divided into RSOH and MSOH

RSOH can be accessed in the regenerator or at the terminal

equipment

MSOH can be processed at the terminal equipment

Page 54: Synchronous Digital Hierarchy

54

Regenerator Section Overhead – RSOH

A1 A1 A1 A2 A2 A2 J0 X X

B1 ∆ ∆ E1 ∆ F1 X X

D1 ∆ ∆ D2 ∆ D3

∆: Media dependent bytes

X: Bytes reserved for national use

Page 55: Synchronous Digital Hierarchy

A1 and A2 Bytes

Frame Alignment (Framing) Bytes Indicate the beginning of the STM-N frame A1 = F6H (11110110), A2 = 28H (00101000) In STM-N: (3XN) A1 bytes, (3XN) A2 bytes

stream

STM-N STM-N STM-N STM-N STM-N STM-N

Finding frame head

Frame # 1 Frame # 2 Frame # 3 Frame # 4 Frame # 5 Frame # 6

Page 56: Synchronous Digital Hierarchy

A1 and A2 Bytes

Framing

Nextprocess

FindA1,A2

OOF

LOF

N

Y

AIS

over 3ms

625 μs

OOF: Out Of Frame

LOF: Loss Of Frame

AIS: Alarm Indication Signal

Page 57: Synchronous Digital Hierarchy

57

Regenerator Section Trace – J0 Byte

Regenerator Section Trace Byte: J0

It’s used to transmit repetitively a Section Access Point

Identifier so that a section receiver can verify its continued

connection to the intended transmitter

Another usage of the J0 byte is that J0 byte in each STM-N

frame is defined as an STM identifier C1 i.e., to identify

individual STM-1 inside a multiplexed STM-N

Within the domain of a single operator, this byte may use

any character

Page 58: Synchronous Digital Hierarchy

B1 Byte

Tx

2#STM-N

Rx

1#STM-NCalculateB1 of STM-N #1

1#STM-N

2#STM-N

Verify B1 B2

STM-NA1 00110011A2 11001100A3 10101010A4 00001111

B 01011010

BIP-8

Bit interleaved Parity Code (BIP-8) Byte A parity code (even parity), used to check the transmission

errors over the RS

Place the result of BIP in B1 of STM-N #2

Page 59: Synchronous Digital Hierarchy

59

F1 Byte

User Channel Byte: F1

Provides a 64 kb/s data/voice channel for special

maintenance purposes.

F1

TM REG TMADM

Page 60: Synchronous Digital Hierarchy

E1 and E2 Bytes

Digital telephone channelE1-RS, E2-MS

E1 and E2

TM ADM TMREG

Orderwire Bytes: Provides one 64 kbps each for voice communication

E1: RS Orderwire Byte – RSOH orderwire message E2: MS Orderwire Byte – MSOH orderwire message

Page 61: Synchronous Digital Hierarchy

61

Quiz

If only E2 byte is used as order wire byte, then order

wire voice communication is provided between:

A and B

B and C

C and D

Page 62: Synchronous Digital Hierarchy

62

Quiz

If only E1 byte is used as order wire byte, then order

wire voice communication is provided between:

A and B

B and C

C and D

A and D

Page 63: Synchronous Digital Hierarchy

D1 ~ D12 Bytes

TMN

DCC channel

NE NE NENE

OAM Information: Control, Maintenance, Remote Provisioning, Monitoring (Alarm & Performance), Administration

Data Communications Channels (DCC) Bytes Message-based Channel for OAM between NEs and NMS RS-DCC – D1 ~ D3 – 192 kbit/s (3X64 kbit/s) MS-DCC – D4 ~ D12 – 576 kbit/s (9X64kbit/s)

Page 64: Synchronous Digital Hierarchy

64

Multiplex Section Overhead – MSOH

B2 B2 B2 K1 K2

D4 D5 D6

D7 D8 D9

D10 D11 D12

S1 M1 E2 X X

X: Bytes reserved for national use

Page 65: Synchronous Digital Hierarchy

65

B2 Bytes

The B1 byte monitors the transmission error of the

complete STM-N frame signal

The B2 bytes monitor the error performance status for

each STM-1 frame within the STM-N frame

There are N*3 B2 bytes in an STM-N frame with

every three B2 bytes corresponding to an STM-1 frame

Page 66: Synchronous Digital Hierarchy

66

B2 BytesB2 Byte Principle

At transmitting end, the BIP-Nx24 is computed over all bits of the STM-N frame except for the first three rows of SOH, and the result is placed in 3 bytes B2 of the preceding frame before scrambling.At receiving end, the BIP- Nx24 is computed over all bits of the frame except for the first three rows of SOH, and then Exclusive OR with the B2 bytes of the later arrived frame.If the value of Exclusive OR operation is zero, there is no bit block error. Any mismatch in result indicates transmission errors.

For example

BIP-N×24 is computed over a frame of signal composed of 9 bytes.

11001100 11001100 11001100

01011101 01011101 01011101

11110000 11110000 11110000BIP24

01100001 01100001 01100001

Page 67: Synchronous Digital Hierarchy

67

K1 and K2 (b1 ~ b5)

Automatic Protection Switching (APS) channel bytes

Used for transmitting APS signaling to implement equipment self-healing function

The K1 byte and K2(b1~b5) are used for automatic switchover to a standby path

Page 68: Synchronous Digital Hierarchy

68

K1 and K2 (b1 ~ b5)

NE-A NE-BWorking path

Standby path

Working path

Standby path

NE-B detects a transmission error on the line and informs NE-A via K1 byte to switchover

NE-A switches to the standby channel

NE-A via K2 byte indicates the switchover in NE-B

NE-B switches to the standby channel

K1

K2

Page 69: Synchronous Digital Hierarchy

S1 Byte

bits 5 ~ 8 Meaning

0000Quality unknown (existing sync. Quality unknown (existing sync.

Network)Network)

0010 G.811 PRCG.811 PRC

0100 G.812 transitG.812 transit

1000 G.812 localG.812 local

1011G.813 SETS (Synchronous Equipment G.813 SETS (Synchronous Equipment

Timing Clock)Timing Clock)

1111 Do not use for sync.Do not use for sync.

Synchronization Status Message Byte (SSMB)Synchronization Status Message Byte (SSMB) This byte is used for This byte is used for synchronizationsynchronization of network of network Bits 5 to 8 of S1 byte indicate the Bits 5 to 8 of S1 byte indicate the quality of the incoming clockquality of the incoming clockThe smaller the value of S1 (b5-b8), the higher the level of clock qualityThe smaller the value of S1 (b5-b8), the higher the level of clock qualityThis helps to determine whether or not to switch the clock source, i.e. This helps to determine whether or not to switch the clock source, i.e.

switch to higher quality clock sourceswitch to higher quality clock source

Page 70: Synchronous Digital Hierarchy

M1 Byte

Tx Rx

Traffic

Multiplex Section Remote Error Indication ( MS-REI ) Byte

This byte is used to report back the number of error blocks detected by the receiver by evaluating three B2 bytes

Tx generate corresponding performance event MS-REI

B2 B2 B2

Report no. of errors detected

Evaluate B2 and detect bit errors

M1

Generate MS-REIMS-REI

Page 71: Synchronous Digital Hierarchy

Path Overheads

J1

B3

C2

G1

F2

H4

F3

K3

N1

123456789

VC-n Path Trace Byte

Path BIP-8

Path Signal Label

Path Status

Path User Channel

TU Multiframe Indication

Path User Channel

AP Switching

Network Operator

Higher Order Path OverheadHigher Order Path Overhead

1 2 3 4 5 6 7 8 9 10

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72

Path Signal Label : C2 Byte

C2 byte is used to indicate the type and composition

of the VC-4 tributary information

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73

Path Status : G1 Byte

Path status byte

This byte is used to report back the fault from path sink to path

source and is set in the POH of the opposite direction

HP-REI HP-RDI Reserved

87654321

HP-REI: High order Path Remote Error Indication

HP-RDI: High order Path Remote Defect Indication

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74

HP-REI and HP-RDI

Higher order Path Remote Error Indication

The SDH NE (sink end) checks B3 bytes

If error blocks are detected, the number of error blocks detected

is sent to the remote terminal in HP-REI signal

The SDH NE (sink end) checks J1 and C2 bytes

Higher order Path Remote Defect Indication

If J1 and C2 fail to be consistent, HP-TIM (Higher order path

Trace Identifier Mismatch) and HP-SLM (Higher order Path

Signal Label Mismatch) alarms are generated

HP-RDI is sent back to the remote end

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75

Multiframe Indication : H4 Byte

This byte indicates the frame

label for a multiframe in the next

VC-4 payload

The value of this byte ranges

from 00H to 03H

Page 76: Synchronous Digital Hierarchy

Path Overheads

V5 J2 N2 K4

VC-12 VC-12 VC-12 VC-12

1

9

1 4

500μs VC-12 multiframe

Low Order Path OverheadLow Order Path Overhead

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Path Status and Signal Label : V5 Byte

BIP-2Parity code of VC-12

LP-REILow order Path Remote Error Indication

LP-REI is set to "1" and returned to teh opposite direction if one or more errors are detected via BIP-2

LP-RFILow order Path Remote Failure Indication

If a defect condition persists beyond the maximum allowed time, it becomes a failure, then LP-RFI is set to "1"

and sent back to the source

Signal LabelIndicates type and composition of VC-12 tributary information

LP-RFILow order Path Remote Defect Indication

If sink end detects a TU-12 AIS, it sets LP-RDI to "1" and sends back to the source

BIP-2 LP-REI LP-RFI Signal Label LP-RDI

87654321

Page 78: Synchronous Digital Hierarchy

POINTERS

Page 79: Synchronous Digital Hierarchy

Pointers

Pointers

AU-PTR TU-PTR

Page 80: Synchronous Digital Hierarchy

AU-PTR

RSOHRSOH

AU-PTRAU-PTR

MSOHMSOH

44

11

99

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81

AU-PTR

Y: Fixed value “1001SS11”

F: Fixed value “11111111”

H3: Additional transmission capacity during negative

justification

H1 and H2: Pointer value is contained in the last ten bits of H1

and H2

H1 Y Y H2 F F H3 H3 H3

87654321 9

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82

AU-PTR

N: New data flag bits

A notification to the receiver about the change in pointer value and pointer

justification operation

AU/TU type:

For AU-4 and TU-3, SS=10

I/D: Increment/Decrement bits

D bits are inverted to decrement next AU-PTR address (-ve justification)

I bits are inverted to increment next AU-PTR address (+ve justification)

N N N N S S I D I D I D I D I D

H1 and H2

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83

TU-PTR

The tributary unit pointer is used to indicate the

specific location of the first byte (V5) of the VC-12

within the TU-12 payload

Page 84: Synchronous Digital Hierarchy

TU-PTR

VC-12 VC-12 VC-12 VC-12

V1 V2 V3 V4

1

9

500μs VC-12 multiframe

TU POINTERSTU POINTERS

Page 85: Synchronous Digital Hierarchy

THANK YOU