ELECRONIC AND CIRCUIT LAB

name-SURAJ KUSHWAHA

scholar no.- 141114037

3rd semester ECE-I

BIPOLAR JUNCTION TRANSISTOR (BJT)

Publication number

US8159048 B2

Publication type

Grant

Application number

US 10/769,571

Publication date

Apr 17, 2012

Filing date Jan 30, 2004

Priority date

Jan 30, 2004

Fee status Paid

Also published as

US20050167747, WO2005074549A2,WO2005074549A3

Inventors Thomas R. Apel, Jeremy R. Middleton

Original Assignee

Triquint Semiconductor, Inc.

Export Citation

BiBTeX, EndNote, RefMan

ABSTRACT

Embodiments of methods, apparatus, devices and/or systems associated with bipolar junction transistor

are disclosed.

BACKGROUND

This disclosure is related to transistors and, more particularly, to bipolar junction transistors.

A variety of factors may affect bipolar junction transistor performance. At least one potential factor is the

particular geometry employed for contacting the semiconductor layers of the transistor. A need, therefore,

continues to exist for bipolar junction transistor geometries that result in improved transistor performance.

  DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a thorough

understanding of the claimed subject matter. However, it will be understood by those skilled in the art that

the claimed subject matter may be practiced without these specific details. In other instances, well-known

methods, procedures, components and/or circuits have not been described in detail so as not to obscure

the claimed subject matter.

As previously indicated, a variety of factors may affect bipolar junction transistor (BJT) performance. At

least one factor is the particular geometry employed. For example, this may refer to the geometry

employed for the semiconductor epitaxial layers and/or the conductive contact layers, typically made of a

metal, for example. In particular, the power gain and power added efficiency performance of a transistor

may be affected by undesirable capacitance between collector and base contacts and by undesirable

extrinsic resistance in series with the base. For example, as explained in more detail hereinafter, for one

embodiment, the particular geometry associated with emitter, base, and collector layers and associated

contact layers may impact this capacitance and this resistance.

LEGAL EVENTS

DateCode

Event Description

Jan 30, 2004 AS Assignment Owner name: TRIQUINT SEMICONDUCTOR, INC., OREGON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:APEL, THOMAS;MEDDLETON, JEREMY R.;REEL/FRAME:014954/0290

DateCode

Event Description

Effective date: 20040130

Owner name: TRIQUINT SEMICONDUCTOR, INC., OREGON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:APEL, THOMAS;MIDDLETON, JEREMY R.;REEL/FRAME:014954/0290

Effective date: 20040130

Sep 10, 2013 CCCertificate of correction

Jun 30, 2015 FPAY Fee payment Year of fee payment: 4

PATENT CITATIONS

Cited PatentFiling date

Publication date

Applicant Title

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Symmetric self-aligned processing

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Reactively compensated power transistors

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Fully walled emitter-base in a bipolar transistor

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Low on resistance high speed off switching device having unipolar transistors

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Transistor layout having a heat dissipative emitter

US20050023643 *

Jul 30, 2003 Feb 3, 2005Innovative Technology Licensing, Llc

Mechanically-stable BJT with reduced base-collector capacitance

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