Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

276 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 2, FEBRUARY 2012

Sub-2-ps, Static Phase Error Calibration TechniqueIncorporating Measurement Uncertainty Cancellation

for Multi-Gigahertz Time-Interleaved T/H CircuitsLingli Xia, Jingguang Wang, Will Beattie, Jacob Postman, Student Member, IEEE, and

Patrick Yin Chiang, Member, IEEE

Abstract—A foreground digital calibration method is pre-sented that calibrates the timing offsets between the multipleT/H (track/hold) circuits of time-interleaved analog-to-digitalconverters and multi-phase serial links. Two quantizer-basedphase detectors sample the outputs of adjacent track/hold circuits,detecting any phase offsets arising from process mismatches inboth the timing verniers and the T/H switches, and store theresulting digital decisions in histogram counters. Measurementinaccuracies resulting from quantizer offset are averaged awaystatistically by a round-robin rotation of the dual samplers, com-pensating for comparator imprecision. Built in a 90-nm CMOSprocess, the proposed calibration technique, after three iterationsof both the phase measurement and subsequent timing vernieradjustment, reduces the static phase offset of each channel to lessthan � � ps in an 8-channel, 8 GS/s time-interleaved system.Further measurements using a T/H circuit as a down-conversionmixer confirm a residual phase error of less than � ps.

Index Terms—Histogram counter, multi-phase, time-inter-leaved, timing error calibration.

I. INTRODUCTION

T IME-INTERLEAVED, multi-phase architectures areenergy-efficient topologies for implementing high-speed

analog-to-digital converters (ADCs) and multi-phase seriallinks [1], [2]. By using multiple phases, lower frequency clockscan relax the front-end track/hold speed, therefore relaxing thebandwidth requirement for the sub-ADCs. Time-interleavingcan also reduce power dissipation in both the clock genera-tion and distribution for the multi-gigahertz ADC. However,mismatches in the offset, gain, and phase spacing among thedifferent sub-channels of the ADC generate undesirable distor-tion, degrading the effective resolution of the ADC.

Manuscript received April 01, 2011; revised May 27, 2011; accepted June20, 2011. Date of current version January 27, 2012. This work was supportedin part by a gift from Intel Circuits Research Laboratory, matching fabricationfunds from SRC, a grant from the NSF-SRC consortium CDADIC and in partfrom a Department of Energy Early Career award. This paper was recommendedby Associate Editor S. Cho.

L. Xia, W. Beattie, J. Postman, P. Y. Chiang are with the School of Elec-trical Engineering and Computer Science, Oregon State University, Corvallis,OR 97331, USA (e-mail: [email protected]; [email protected]).

J. Wang was with the Oregon State University, Corvallis, OR 97331 USA.He is now with the Broadcom Corporation, Irvine, CA 92617 USA (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2011.2162382

A. Previous Methods for Time-Interleaved Calibration

Several methods have been introduced that minimize theoffset and gain mismatch for time-interleaved ADCs [3], [4].However, timing offset is the most critical for multi-gigahertzmulti-phase operation, as these timing offsets result in ADCsampling errors and therefore a reduction in ADC resolution.These sampling errors can arise from several process-inducedmismatches as shown in Fig. 1: timing skew caused by theclock propagation and mismatch in the track and hold (T/H)circuit. In order to calibrate the sub-channel timing mismatchesand phase offsets, a few techniques have been previouslyintroduced. In [1], [5], and [6], digital back-end processingis used to perform fast Fourier transform (FFT), generatingfrequency spurs that can be measured and calibrated. How-ever, this method requires significant hardware and softwareresources those are expensive in regards to silicon area, powerconsumption, and calibration time overhead. Furthermore, thismethod requires a well known input signal, e.g., a pulse trainor sine-wave signal. In [7], a mixed-signal technique com-bining high-resolution ADCs (10-bit) and a digital back-endperforming FFT is presented. Unfortunately, the large power ofthe high-resolution ADCs make this technique impractical forhigh sampling rate TI-ADCs. Furthermore, the sensitivity togain and offset mismatches is also a critical concern. Reference[8] presents a technique that requires neither oversampling ofthe input signal nor an input training signal. However, this tech-nique depends on the input signal characteristics, thus limitingit to digital communication systems. In [9], the sampling-timeerror is corrected by adaptively adjusting a FIR filter accordingto the calculated timing error. Unfortunately, this technique islimited by the precision of the Hilbert filter implementation.Furthermore, the front-end filter banks consume significantpower and chip area. In [10] and [11], multiple phase detectorsand analog feedback loops are used between the various phasesof the multi-phase clock generator. However, these approachesrequire significant area overhead for the large capacitive loopfilters, and are limited by the intrinsic phase offsets in thephase detectors themselves. In [12], code density histogrammeasurements of each phase bin are used. Multiple, redundantquantizers are used for each phase bin, which introduces signif-icant area and power overhead. Although the quantizer with theleast amount of voltage offset is selected as the most optimal,the final phase resolution is limited to the residual offset of thebest-matched quantizer. With continued CMOS scaling, quan-tizer offset and residual offset will continue to worsen, even

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XIA et al.: SUB-2-ps, STATIC PHASE ERROR CALIBRATION TECHNIQUE 277

Fig. 1. Timing error sources in time-interleaved ADC.

after digital comparator calibration is performed [13]. [14], [15]present a zero-crossing detector to measure the phase spacing.However, this technique considers only the timing skew due tomulti-phase clock propagation asymmetries, neglecting timingmismatches introduced by the T/H matching.

B. Novelty of This Proposed Work

In this paper, a new foreground phase error calibrationmethod is introduced that compensates for both multi-phaseclock delay uncertainty, as well as any T/H circuit mismatch-in-troduced timing errors (such as mismatch in the T/Hswitches). Furthermore, any timing uncertainties introduced bythe intrinsic offset of the phase detector circuit itself [12] arestatistically averaged away using the proposed round-robin ro-tation of the quantizers. The measurements show that for eighttime-interleaved channels running at 1 GHz, calibration resultsin less than 0.5-ps residual phase error (measured by bin-sizehistogram), and less than 2 ps (measured by oscilloscope andlimited by equipment precision).

Section II discusses the timing error sources and Section IIIintroduces the systematic architecture of the proposed detectionand calibration method. Section IV presents the details on circuitimplementations. Section V shows the measurement results, andSection VI draws a conclusion.

II. TIMING ERROR SOURCES

As observed in Fig. 1, the sources of static phase error are:1) non-uniform propagation delay between different clock

paths;2) threshold voltage mismatch th in the sampling switch

that introduces an equivalent timing error;3) dimensional size mismatches of both the sampling

switches and the sampling capacitors, causing input signaldelay variation among the interleaved sub-channels.

For a high-frequency input signal, these small variations cancause large sampling voltage errors, resulting in harmonic dis-tortion at the output with a frequency of

(1)

where is the harmonic frequency, is the clock frequencyof each channel, is the input data frequency, and is the

Fig. 2. Spectrum of 8-channel T/H output (a) without timing offset (b) with2-ps timing offset in one channel.

multi-channel number. For example, consider an 8-channel,10 GS/s ADC, with each channel operating at a sampling rateof 1.25 GS/s, with a clock amplitude of 1.2 V and a 3.906 GHzinput signal with a peak-peak amplitude of 800 mV. If there isno mismatch among the 8 channels, the spurious-free dynamicrange (SFDR) at output is approximately 57.5 dB, limited bythe 3rd harmonic, as shown in Fig. 2(a). When 2 ps of timingerror is introduced in one channel, the SFDR is reduced to37.2 dB due to the harmonic distortion [Fig. 2(b)]. That 2 psof timing error in one channel is equivalent to a timing errorstandard deviation in the 8 channels:

(2)

The signal-to-noise and distortion ratio (SNDR) of T/H outputdue to the sampling clock with rms jitter of is given by [8]

(3)

Therefore, with a 0.66 ps rms timing error, the SNDR is limitedto 36.2 dB. Hence, the calculated SNDR using a static timingerror matches the simulation results well. Therefore, the statictiming error and the random clock jitter affect the ADC SNDRequivalently, and thus can be treated as uncorrelated timing errorsources.

Besides the phase delay mismatches in the multi-phase clockdistribution, mismatches between the different T/H channelsalso introduce sampling uncertainty, which can be further sepa-rated into both gain and timing mismatch. Consider a T/H circuitthat typically consists of a NMOS switch and a holding capac-itor. The NMOS threshold voltage Vth mismatch can directlyaffect the switch turn-off time by

(4)

where is the slope of the clock transition edge. Fig. 3(a) showsthe output spectrum when a 60-mV Vth mismatch is added toone channel, using a sampling clock transition time of 40 ps.According to (4), the equivalent timing error is 2 ps for

mV. Fig. 3(b) shows the simulation result when a 2-ps clockdelay is introduced to compensate for this Vth mismatch. As


Fig. 3. Spectrum of 8-channel T/H output. (a) 60-mV Vth mismatch in onechannel. (b) 2-ps timing change to compensate Vth mismatch.

observed, the SFDR increases from 36.6 dB to 50.6 dB aftercompensation, and all the harmonic distortions are reduced tolower than the 3rd harmonic.

The compensated SFDR in Fig. 3(b) is still 7 dB worse thanFig. 2(a) because the Vth mismatch also affects the turn-on re-sistance of the sampling switch, and hence the channel band-width. The channel bandwidth can also be affected by the switchdimension mismatch and holding capacitance mismatch. Band-width mismatch will introduce a signal delay difference and gainerror between the multipath channels. In this paper, only thesignal delay difference is addressed. For high-speed low-reso-lution ADCs, the signal delay difference is more critical thanbandwidth-induced gain error. Consider that the T/H circuit is afirst-order filter. If the group delay of this filter is constant, thetime delay for different input frequencies will be identical, suchthat we can compensate for the delay difference by changing theclock delay. The group delay of a first order filter is

(5)

where is the switch turn on resistance, and is the holding ca-pacitance. If we want to reduce the group delay variation,should be much smaller than 1. Then the group delay variationto DC is

(6)

Therefore, we need to reduce the turn-on resistance and increasethe T/H circuit bandwidth for a high-speed ADC [16]. For ex-ample, with a switch resistance of 100 and holding capaci-tance of 100 fF, the group delay variation is approximately 0.9ps at 5 GHz.

Based on the analysis above, as long as the T/H circuits band-width are satisfactorily large enough, any timing errors intro-duced by both multi-clock phases and T/H mismatches can becompensated by adjusting the multi-phase clock delay.

III. TIMING ERROR DETECTION AND CALIBRATION

This paper extends on previous phase error detection and cal-ibration methods using statistical code density measurements[12], [17] by:

Fig. 4. Code-density based, timing error detection.

1) removing the timing error of any mismatch that results inADC sampling uncertainty, including both clock phase off-sets as well as T/H transistor mismatch;

2) removing measurement circuit timing error (i.e., quantizeroffset) by rotating the dual samplers to all the sub-chan-nels in a round-robin rotation, effectively removing thecomparator dc offset from the measurement calibration,leaving only the phase uncertainty in the time-interleavedmulti-phases.

As shown in Fig. 4, the falling edges of the two phase clocksand , with a timing difference of , are used to sample

the applied input signal. When a transition of the input signaloccurs between these two sampling instances, the combinationof the two samplers’ output is “1”; otherwise the output is “0.” Ifthe frequency of the input signal is asynchronous with the sam-pling clock frequency, the input signal transitions are uniformlydistributed across one signal period . Hence, the timing differ-ence between and can be obtained from the number of“1”s and “0”s after a long measurement time:

number of “ ''number of “0''

(7)

where is the period of the input signal, and is seen onthe numerator because the input signal’s falling and rising tran-sitions are both numbered.

In order to realize the above code density measurement, high-speed samplers and comparators are needed. Fig. 5 shows theproposed timing detection and calibration loop for the time-in-terleaved ADC. The eight-channel, time-interleaved T/H cir-cuits are driven by an eight-phase clock generator, where eachchannel runs at 1 GS/s such that the total ADC sample rate is8 GS/s.

During calibration mode, two adjacent channels, such aschannel-1 and channel-2, will be connected to the two compara-tors, comp1 and comp2, respectively. When the asynchronousinput is sampled by S1 and S2, the XOR output will observea “1” if the input transition edge is located between these twosample instances. The following N-bit histogram counter willcontinue operating for clock cycles, where the bin-size cor-responding the phase spacing between channel-1 and channel-2will be recorded in the counter. After the first phase-bin mea-surement is finished, the same comparators comp1 and comp2are switched to the next two adjacent channels, channel-2 and


Fig. 5. Proposed timing error calibration loop in time-interleaved T/H archi-tecture. (a) Schematic. (b) Comparison sequence.

channel-3, to measure the phase spacing between these twochannels. This measurement will be continued until the phasespacing information for all the channels is obtained.

According to (7), the timing error for each channel can be de-termined by comparing the average bin-size of all eight coun-ters with each individual bin’s counter. The timing differencebetween channel n and channel is

(8)

The counter length and the input signal frequency determinesthe accuracy of the timing error measurement. For example, ifan error detection accuracy of 0.01 ps is required, should beat least 16 for a 1-GHz input signal. Based on the measuredtiming error results, the delay time of each clock is then ad-justed with per-channel phase interpolators. In noisy environ-ments, in order to improve the robustness to noise, more cali-bration rounds of measurement and adjustment are needed untilthe residual timing error is minimized.

As seen in Fig. 5(a), the original time-interleaved T/H cir-cuits of the ADC are also used in the front-end of the timingcalibration loop. Therefore, timing errors caused by T/H circuitmismatches such as th mismatch are also included in the de-tection method and minimized. If the group-delay variation ofthe T/H circuits within the Nyquist bandwidth is small enough,the timing error calibration for one particular input frequencywill be acceptable for the entire signal bandwidth (Fig. 15).Hence, the proposed calibration method for the ADC will bevalid during normal operation for the wideband spectrum of realdata in a communication system.

Fig. 6. Schematic of one channel differential T/H circuit.

The same two comparators are used for all the channels in thephase measurement, using a round-robin rotation. As shown inFig. 5(b), the measured timing error is

(9)

where and is the timing difference betweenchannel n and when real and ideal comparators areemployed, respectively; is the average timingdifference between two adjacent channels when ideal com-parators are used; is the static comparator offset inducedtiming error, which is constant between two adjacent channels.Employing the proposed round-robin rotation results in aver-aging and therefore removal of any comparator offset. This isanalogous to analog chopper stabilization, but done in a digitalmanner and applicable for any number of time-interleavedchannels. Previously, such comparator offsets limited the phasedetector accuracy, requiring a significant amount of calibrationhardware overhead and circuit redundancy [12]. The methodpresented here does not require comparator offset calibration,and is independent of any input-referred offset.

IV. CIRCUIT IMPLEMENTATION

The test-chip contains eight 1 GHz, time-interleaved T/H cir-cuits, exhibiting a front-end sampling rate of 8 GS/s. It alsointegrates current-steering, DAC-controlled phase interpolators[18] that achieve less than 0.5-ps minimum phase step-size.The comparators and 16-bit histogram counters are operating at1 GHz, detecting the timing errors between the eight channels.

A. T/H Circuits

Fig. 6 shows the differential T/H circuit, where NMOS M1and M2 are used as switches while Cs1 and Cs2 are holding ca-pacitors. Dummy transistors M3–M6 with half the size of M1(M2) are used to remove the charge injection of the hold voltageand charge kickback of the input when the switches change from


Fig. 7. Quantizer in the detector. (a) Schematic. (b) Clock sequence.

track to hold mode. M7 (M8) is a copy of M1 (M2) which is em-ployed to compensate for any signal feed-through in hold mode.In order to reduce the bandwidth mismatch introduced gain andphase errors, the bandwidth of each channel is designed up tothe Nyquist frequency of 4 GHz with minimal distortion [2].The R-C time constant of the switch-capacitor should be smallenough to minimize the group delay variation between channels.Here, the switch turn-on resistance is approximately 40 in thedesign, Cs1 (Cs2) is a 100-fF metal capacitor, and the extractedparasitic wire capacitance is approximately 30 fF. Hence, thegroup-delay variation for a 4-GHz bandwidth is about 0.1 ps,which is small enough. Therefore, the signal delay differenceamong different channels can be compensated for by adjustingthe clock delays on each sub-channel.

B. Quantizer

The sensitivity of the quantizer directly affects the accuracyof the phase detector. Input voltage offset and regeneratedsignal kickback are two main factors that limit comparatorsensitivity. Fig. 7(a) is the schematic of the two-stage regen-erative comparator used here for phase detection. A PMOSsource follower is used as a low-to-high level shifter, as thecommon-mode output voltage of the T/H circuit is near GND.The low output impedance of the level shifter helps to preventthe regenerated signal kickback from affecting the T/H holdingcapacitors. The first stage of the quantizer is a Schinkel’slatch [19], which includes a pre-amplifier at the bottom and

Fig. 8. Quantizer offset in Monte Carlo simulation.

Fig. 9. Digital circuits of the detector.

a latch at the top. The pre-amplifier can further reduce theregenerated signal kickback, mitigate comparator hysteresis,and decrease aperture time. Three clocks (CLKP, CLKN, andCK) are generated from one same clock source to control thequantizer operation. Fig. 7(b) shows the timing sequence ofthese three clocks. Minimum transistor length of 100 nm isemployed in the quantizer to increase its bandwidth; however,this introduces a large voltage offset. Fig. 8 shows 100 MonteCarlo runs of the quantizer offset, showing a maximum offsetgreater than mV.

This quantizer offset in the measurement results in phaseuncertainty for the time-interleaved phases. A previous ap-proach used both comparator redundancy and comparatoroffset calibration [12], but this calibration was still limited bythe minimum achievable offset. Furthermore, temperature vari-ations on die will change the quantizer offset over time. In thispaper, offset in the quantizer is eliminated in the measurementby “chopping” the inputs by round-robin rotation, such that thedc offsets can now be removed after sampling and averaging.A second stage latch is added for the purpose of reducingmetastability.

C. Detector

Fig. 9 shows the digital circuits of the detector. After beingamplified to full logic level, the quantized RZ (return-to-zero)signal is converted to NRZ (non-return-to-zero) signal by theR-S latch. Because the two quantizers employ sampling clocksfrom two adjacent channels , D flip-flops are usedto synchronize the output data with the clock . ThenXOR gate combines these two paths data together, resulting in


Fig. 10. Multi-phase clock generator.

Fig. 11. Phase interpolator.

a “1” if the input signal transition happens between two adja-cent phase clocks; otherwise, the XOR output is “0.” Counter-Awith length counts the output of the XOR, in order to ob-tain enough samples. Counter-B whose length is also keepscounting regardless of the XOR output, and once B is full, itstops counter-A. Now the bin size that represents the phasespacing between channel and is read out to the off-chipcomputer for further data processing and timing calibration. Fi-nally, the detector is switched to the next two channels in orderto obtain the phase spacing between channel and channel

.

D. Multi-Phase Clock Generator

The eight-phase 1-GHz clocks are generated from a 4-GHzdifferential input clock (Diff_input) by a divide-by-4 divider,as shown in Fig. 10. The divide-by-4 function is realized bya two-stage, current-mode logic (CML), D-flip-flop based di-vide-by-2 dividers [20]. Instead of using two separate dividersin the second stage, a merged-divider is employed to insure theposition of the multi-phase clocks, for example, ’ is locatedbetween and . The interpolated phases from the gener-ated multi-phase clocks are finely tuned by two differential cur-rent mode phase interpolators (PI), as shown in Fig. 11. TheDAC controlled current-steering employs 6-bit binary-weightedcells and half-fixed cells. The proceeding differential-to-single-ended buffer and two-stage inverter buffers are used to reshape

Fig. 12. Chip photograph and measurement setup.

Fig. 13. Measured phase spacing range and the step size.

the output clock edge and improve the driving ability. An on-dieregulator is used to reduce the supply noise.

V. MEASUREMENT RESULTS

The test-chip is implemented in a 1.2-V, 90-nm CMOS tech-nology, with a die area of 1 mm . The measurement setup isshown in Fig. 12. A PC communicates with the chip through aNI-DAQ scan interface. When timing error detection finishes,the histogram counter data is read out to the PC through a scanchain, and then after comparison, the PC controls the calibrationloop by adjusting the phase interpolator through the scan chain.I-V converters and output buffers are used to drive an oscillo-scope to verify the timing accuracy after calibration.

Fig. 13 shows the measured phase spacing linearity betweenchannel-5 and channel-6 when the 6-bit current-steering inter-polator of channel-5 is swept across its entire range. With thedefault setting (control bits are set to 32), the phase spacing erroron channel 5 is approximately 3 ps. The delay time of each clockcan be shifted a maximum ps, with an average step size of0.43 ps. The largest and smallest step size is 0.7 ps and 0.2 ps,respectively, resulting in a detector accuracy of less than psfor a fixed frequency input. The phase accuracy can be improvedby using a larger histogram counter, and smaller phase step sizein the phase interpolator.

In order to measure the bin-size between two channels, anasynchronous 1137-MHz signal is applied at the ADC input.The measured bin-size between two adjacent channels is shownin Fig. 14(a). According to (8) and the input signal period du-ration, we can calculate the timing error of each channel, alsoshown in Fig. 14(b). The largest measured timing error is 8.4 pson channel-2 before calibration. After calibration, the bin-sizeof each channel exhibiting a residual timing error of 0.5 ps.


Fig. 14. Calibration results. (a) Measured bin-size of each channel. (b) Mea-sured timing error.

Fig. 15. Measured timing error for different input frequencies (Calibrated at1137 MHz).

In order to check the accuracy and the noise immunity of thehistogram result, the bin-size has been measured 5 times withthe same setup, and the largest timing error difference is only0.5 ps.

In order to check the T/H bandwidth effect on the timingdetector accuracy, the timing error of each channel is mea-sured for different input frequencies after calibration with the1137-MHz input signal, as shown in Fig. 15. The residualtiming error is shown to be less than 1 ps for input frequenciesfrom 800 MHz–1800 MHz, resulting in a standard deviation

Fig. 16. Measured eight-channel down-converted outputs.

of phase offset smaller than 0.5 ps. At low input frequencies,the rather small, 16-bit counter size affects the code densityand therefore the measurement accuracy. From these measure-ments, it can be observed that bandwidth variations are minimaland the proposed calibration method is valid for a widebandinput signal.

Because this chip does not include the entire time-interleavedADC, the timing error calibration accuracy through ADC cannotbe verified. An alternative way to check the phase calibrationaccuracy is to use the T/H circuit as a passive down-converter.The output signal of the down-converter is

(10)

where and are the input signal and clock frequency,and are the initial phase of these two signals. The frequencyof the lower side-band signal is the difference between the fre-quency of the clock and the input signal (while the upper side-band signal can be easily removed by a low-pass filter). Inputsignal phase is the same for all the eight channels, so that theclock signal phase can be measured from the down-convertedoutput. More importantly, the frequency of the down-convertedsignal can be much lower than the sampling clock frequency,such that it is much easier to measure the phase of this outputsignal, which represents the phase of the input clock.

Fig. 16 shows the measured eight-channel down-convertedoutputs. With 1-GHz multi-phase clocks and an 1110-MHzinput signal, the output signal is down-converted to 10 MHz,and the eight-channel phase error is within ns. Becauseeach sub-channel clock and down-converted signal has thesame phase error in radians, the corresponding phase errorof the 1 GHz clocks is within ps. This number, however,is conservative, as the output buffers and multiplexers willintroduce some process mismatch and phase variation them-selves. Therefore, in addition to a measured ps phaseerror extrapolated from on-chip histogram bins, we verified andbounded this phase accuracy to within ps.

Amplitude of the input sine-wave has a critical effect onmeasurement accuracy, as a low amplitude results in largersusceptibility to measurement uncertainty due to low gain,


TABLE ISUMMARY OF THE PREVIOUS WORKS AND PROPOSED WORK

Fig. 17. Maximum static phase offset versus input voltage amplitude.

and minimum quantizer sensitivity. For example, with a100-mV pk-pk, 1 GHz sine-wave input, a 1-ps phase errorwill result for only differential amplitude of 0.5 mV into thequantizers. Fortunately, quantizer offset is removed from themeasurement using our statistical averaging approach. Hence,as observed in Fig. 17, measured histogram bin sizes show lessthan 3 ps phase difference between a large VIN (450 mV) anda small VIN (60 mV). Only when the input is set to less than59 mV does the measurement error become excessive.

The ability to integrate this calibration technique on-chipis important for a variety of applications, such as time-digitalconverters (TDCs) in digital PLLs, I/Q phase calibration forRF systems, and multi-phase generators for high-speed seriallinks. A simple way to generate the uncorrelated signal forthe input is to use a free-running ring oscillator on-die, whoseoscillating frequency is unrelated to the sampling clock, suchthat the histogram bins will reflect a uniform distribution ofsamples. Fig. 18 shows the measured results as the uncorrelatedclock frequency input is moved away from the samplingfrequency . When matches , the residual, worst case

Fig. 18. Maximum phase offset versus varying input frequency as � (inputsignal for calibration) moves away from the � (sampling clock).

phase offset across the eight channels is 84 ps, showing that thecalibration algorithm fails for highly correlated frequencies.The same phenomenon exists at multiples of the sampling fre-quency, such as when fs. However, slight deviationsfrom the beat frequency, such as of , shows thatthe offset is calibrated to approximately 1.5 ps. This measure-ment shows the possible flexibility to implement any randomuncorrelated clock as an input source, and still obtain uniformhit distributions across the eight bins. Hence, the hardwareoverhead for implementing this multi-phase calibration can berelatively small and simple.

Table I summarizes the differences between the proposedwork and previous works.

VI. CONCLUSION

A new digital timing error detection and calibration methodhas been implemented on an 8 GS/s, eight-channel, time-inter-


leaved T/H circuit. Timing error sources in the T/H circuits,from clock distribution skew to threshold voltage mismatch, arecalibrated in the calibration loop. In addition, residual phaseerror arising from comparator offset is canceled using statisticalaveraging. Measurement results show that the static timing erroris reduced to less than 2 ps between adjacent sub-channels. Fur-ther improvements in residual phase error can be achieved byusing a larger histogram counter. In conclusion, the proposedtiming error calibration method is effective for multi-gigahertz,time-interleaved ADCs, such that static timing errors will notlimit the ADC system performance.

ACKNOWLEDGMENT

The authors would like to thank MOSIS for help in chipfabrication.

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Lingli Xia received the B.S. degree in electronics sci-ence and technology in 2005 from Huazhong Univer-sity of Science and Technology, Wuhan, China, andthe Ph.D. degree in microelectronics and solid stateelectronics in 2010 from Fudan University, Shanghai,China.

She is currently a Postdoctor in electrical en-gineering at Oregon State University, Corvallis.Her doctoral thesis concerns ultra wideband RFtransceiver design. Her research interests includeRF front-end circuit and digital baseband circuit for

wireless communication systems.

Jingguang Wang received the B.Sc. and M.Sc.degrees in microelectronics from Fudan University,Shanghai, China, in 2003 and 2006, respectively,and the M.Sc. degree in electronic engineering fromOregon State University, Corvallis, OR, in 2008.

From 2006 to 2007, he was an RF/Analog DesignEngineer with RDA microelectronics, Shanghai,China, where he worked on the satellite TV tunerdesign. During the summer of 2008, he internedat Telegent Systems in Sunnyvale, CA, designinga SAR ADC for tuner product. In 2008, he joined

Broadcom Corporation, Irvine, CA, working on the analog front-end forEthernet products.

Will Beattie is currently pursuing the Ph.D. degree inmechanical engineering at Oregon State University,Corvallis.

Jacob Postman (S’10) is currently pursuing thePh.D. degree in electrical and computer engineeringat Oregon State University, Corvallis.

His research interests include energy-efficient andhigh-performance logic and interconnect circuits,micro-architectures, and networks-on-chip.

Patrick Yin Chiang (S’99–M’06) received theB.S. degree in electrical engineering and computersciences from the University of California, Berkeley,in 1998, and the M.S. and Ph.D. degrees in electricalengineering from Stanford University, Stanford, CA,in 2001 and 2007.

He is currently an Assistant Professor of electricaland computer engineering at Oregon State Univer-sity, Corvallis, OR. In 1998, he was with DatapathSystems (now LSI Logic), working on analog fron-tends for DSL chipsets. In 2002, he was a research

intern at Velio Communications (now Rambus) working on 10-GHz clock syn-thesis architectures. In 2004, he was a consultant at startup Telegent Systems,evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006, hewas a Visiting NSF Postdoctoral Researcher at Tsinghua University, Beijing,China, investigating low-power, low-voltage RF transceivers. In summer 2007,he was a Visiting Professor at the Institute of Computing Technology, ChineseAcademy of Sciences, where he collaborated on the design of multi-gigahertzADCs and high-speed serial links. In December 2009, he was a Senior VisitingResearcher at Fudan University, Shanghai, China, researching mixed-signal cir-cuits and systems in the State Key Lab of ASIC and System. His interests areenergy-efficient VLSI interconnect and energy-constrained medical sensors.

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Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits