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Stratix V GT Device Design Guidelines2014.01.07

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Altera’s Stratix® V devices provide four duplex transceiver GT channels, each capable of a serial data rateup to 28.05 Gbps. Stratix V GT devices support chip-to-chip and chip-to-module applications. The GTtransceivers can achieve a very low bit error ratio (BER) of <1e-15 to meet the requirements of high speedserial data applications.

This application note assumes you have experience designing for Altera’s Stratix V GX transceivers. Buildingon the StratixVdesign guidelines (AN625) and theAltera Transceiver PHY IPCoreUserGuide, this documentprovides specific recommendations for designing with the Stratix V GT channels. It discusses channel lossdesign to ensure your Stratix V GT system can meet the low BER, GT channel implementation, timingclosure design consideration, and dynamic reconfiguration.

Related Information

• AN 625: Stratix V Device Design Guidelines

• Altera Transceiver PHY IP Core User Guide

Channel Loss Design and Case StudiesYour system’s performance depends to a large extent on how well your board is designed. For yourStratix V GT system to achieve low BER at 28 Gbps, design the boards so the GT links do not exceed -10 dBof insertion loss. The link loss is determined by the trace length, board material, via structures, AC couplingcapacitors, and any connectors that are part of the link. The board trace impedances must be well matchedand the channel losses minimized. Perform an analysis of your GT links as part of the board design process.

StratixVGT channels can drive four inches of striplineNelco 4000-13 tracewith one connector and additionaltrace at 28 Gbps. This link topology has channel loss comparable to the requirements of the CEI-28G-VSRspecifications. Stratix V GT channels may drive longer traces with higher insertion loss at lower data rates.To ensure your link operates at 28 Gbps, keep the link insertion loss to no more than -10 dB. For additionalmargin, reduce the insertion loss even more to provide optimal performance. The table below shows thedifferent link topologies where Stratix VGT channels successfully demonstrated a BER of < 1e-15 at 28Gbpsusing the Stratix V GT signal integrity board.

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Table 1: Stratix V GT BER Test Link Topologies

Estimated Link Insertion Loss (dB) (1)Link Topology

-5.5Direct external loopback on Megtron 6 microstrip trace +MMPX connectors

-10.54” Nelco 4000-13 stripline trace with connector + MMPXconnectors

-13.68” Megtron 6 microstrip trace + MMPX connectors

-11.36” LC Rogers microstrip trace + MMPX connectors

Each transceiver link needs optimized analog settings to ensure it meets the low BER. Apply signalconditioning techniques such as adjustments to the transmitter pre-emphasis and receiver equalization tofine-tune the links.

Refer to Altera’s board design guidelines—AN 672 and AN 684—for more information about optimizingyour board design for high speed serial links.

Related Information

• AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

• AN 684: Design Guidelines for 100 Gbps - CFP2 Interface

Designing for Stratix V GT ChannelsThe following sections provide recommendations for designing with Stratix V GT channels.

Reference Clock SelectionFor best transmitter jitter performance, use the dedicated reference clocks of the same transceiver bank.

Because each transceiver bank provides two dedicated reference clock sources, you can set different referenceclocks to drive the ATX PLL and the RX CDR, as shown in the following figure.

(1) Insertion loss is estimated and based on layout extraction and VNA measurements.

Stratix V GT Device Design GuidelinesAltera Corporation

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Figure 1: Two Dedicated Reference Clock Sources

CDRStratix V GTReceiverChannel

Receiver

Receiver

Transmitter

Notes:(1) The fractional PLL refclk buffers allow you to segment the reference clock line into multiple segments, such that fractional PLLs in different transceiver banks can drive the same fractional PLL reference clock line.(2) The bottom ATX PLL of a GT transceiver bank provides the serial clock to the GT transmitter channel.(3) The CMU PLL of the GT transmitter channel drives an x1 clock line that can be used by the top and bottom GX transceiver channels in the GT transceiver bank.(4) N equals twice the number of GT channels.

Channel PLLStratix V GXTransceiverChannel

Transmitter

Receiver

Channel PLL

CMU PLL (3)

Stratix V GXTransceiverChannel

Transmitter

ATXPLL

ATXPLL(2)

Fractional PLL

Fractional PLL

N (4)

refclk0

Fractional PLLReference Clock Line

2

2

2

2

2

N

N

N

N

Reference ClockNetwork

2

N

2

Stratix V GTTransmitterChannel

Fractional PLLReference

Clock Buffer (1)


Clock Buffer (1)


Clock Buffer (1)

Reference Clock Network

Clocks or Data

Fractional PLL Reference Clock Line

Dedicated refclk

Unused resource

Dedicatedrefclk 1

/2

Dedicatedrefclk 0

/2

DedicatedReferenceClock forATX PLL

DedicatedReferenceClock forRX CDR

To minimize the number of reference clock sources required, you can also choose one of the two dedicatedreference clocks to drive both the ATX PLL and the RX CDR. In this case, use the dedicated reference clockto drive theATXPLL directly and use the reference clock network to drive the RXCDR for best performance.

Altera CorporationStratix V GT Device Design Guidelines

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Figure 2: One Dedicated Reference Clock Source

CDRStratix V GTReceiverChannel

Receiver

Receiver

Transmitter

Notes:(1) The fractional PLL refclk buffers allow you to segment the reference clock line into multiple segments, such that fractional PLLs in different transceiver banks can drive the same fractional PLL reference clock line.(2) The bottom ATX PLL of a GT transceiver bank provides the serial clock to the GT transmitter channel.(3) The CMU PLL of the GT transmitter channel drives an x1 clock line that can be used by the top and bottom GX transceiver channels in the GT transceiver bank.(4) N equals twice the number of GT channels.

Channel PLLStratix V GXTransceiverChannel

Transmitter

Receiver

Channel PLL

CMU PLL (3)

Stratix V GXTransceiverChannel

Transmitter

ATXPLL

ATXPLL(2)

Fractional PLL

Fractional PLL

N (4)

refclk0

Fractional PLLReference Clock Line

2

2

2

2

2

N

N

N

N

Reference ClockNetwork

2

N

2

Stratix V GTTransmitterChannel


Clock Buffer (1)


Clock Buffer (1)


Clock Buffer (1)

Reference Clock Network

Clocks or Data

Fractional PLL Reference Clock Line

Dedicated refclk

Unused resource

Dedicatedrefclk 1

/2

Dedicatedrefclk 0

/2

DedicatedReferenceClock forATX PLL

ReferenceClock Network

for RX CDR

Low Latency PHY IPEach GT transceiver bank supports one GT channel that can operate as a duplex, TX, or RX channel.Stratix V GT channels are implemented in a physical medium attachment (PMA) direct mode using theAltera transceiver Low Latency PHY IP. Each channel requires its own PHY IP instantiation, which can beeither a duplex or simplex channel.

The following figure shows the transceiver bank locations for Stratix V GT devices.


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Figure 3: Transceiver Bank Locations

6 Ch

6 Ch

6 Ch

6 Ch

3 Ch1 GTB2 GXB

PCIeHardIP

GTB_R3

GTB_R2

GTB_R1

GTB_R0

GXB_L3

GXB_L2

GXB_L1

GXB_L0

Number of ChannelsPer Bank

TransceiverBank Names

Number of ChannelsPer Bank

TransceiverBank Names

Ch 2 GXBCh 1 GTBCh 0 GXB

3 Ch1 GTB2 GXB

3 Ch1 GTB2 GXB

3 Ch1 GTB2 GXB

Notes:1. GT transceiver banks are made up of 1 GT channel and 2 GX channels. The GT channel is the middle channel in the bank.2. GT devices only come with one PCIe HIP block located across GX banks L0 and L1.

The following figures show the MegaWizard Plug-In Manager instantiating a Low Latency PHY IP toimplement a duplex GT channel running at 28 Gbps. Enter the appropriate settings for your specific designrequirements.


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Figure 4: MegaWizard General Tab for Low Latency PHY IP

GT channels have a 128-bit width and require a GT data path and an ATX PLL.


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Figure 5: MegaWizard Additional Options Tab for Low Latency PHY IP


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Figure 6: MegaWizard Reconfiguration Tab for Low Latency PHY IP

The messages in the bottom pane provide information about the reconfiguration interfaces.


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Figure 7: MegaWizard Analog Options Tab for Low Latency PHY IP

The Altera 40G/100G Ethernet PHY IP for CAUI-4 (4x25) will instantiate the GT channelsautomatically.

Note:

If you want to integrate the Low Latency PHY IP into your Qsys design, you must create a Qsys componentfor the Low Latency PHY IP. After the Low Latency PHY IP component is created, you can connect it toother components in your Qsys design. Refer to the Qsys documentation for creating a component.

Related Information

• Creating Qsys Components

• Refer to the "StratixVGTDeviceConfigurations" section of theTransceiverConfigurations in StratixV Devices chapter

Reconfiguration ControllerThe reconfiguration controller provides a number of features that are used for calibrating the transceiverPLLs and for tuning the channels using dynamic reconfiguration.

Every transceiver PHY IP instance must be connected to a transceiver reconfiguration controller. If the GXchannels and the GT channel from the same transceiver bank are used, they must be connected to the samereconfiguration controller. For simplicity, you can connect all the transceiver PHY IP instances, includingthose from other banks, to the same reconfiguration controller.


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In the following figure, the MegaWizard Plug-In Manager is used to connect four duplex GT channels tothe reconfiguration controller. This design requires 12 interfaces because each duplex GT channel consistsof three logical interfaces: RX, TX, and ATX PLL. The interfaces are bundled as four separate groups, onefor eachGT channel. Bundling the interfaces into groupsmakes the connections between the reconfigurationcontroller and the GT channel more straightforward.

The Enable channel/PLL reconfiguration option in the Reconfiguration Features section must be turnedon for the GT channels. This setting enables the MIF mode streamer module, which allows dynamicreconfiguration of the GT channels. The Analog Features section is for the GX channels. Turn on the analogfeatures options that you want to implement for your GX channels.

Figure 8: Transceiver Reconfiguration Controller for GT Channels

Logical Channel MappingThe RX, TX, and ATX PLL of each transceiver PHY IP are each assigned a logical channel address thatuniquely identifies it.

The logical channel address allows you to access a specific channel through the reconfiguration controllerto perform dynamic reconfiguration. This logical mapping is based on the PHY IP instances, such as duplexor simplex, and the order inwhich they are connected to the reconfiguration controller. The following figureshows the fitter report of the logical channelmapping information for a designwith four duplexGT channels.You will need this information when you perform dynamic reconfiguration.


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Figure 9: Logical Channel Mapping Example

Timing ClosureClosing timing ensures your design functions correctly by meeting setup and hold requirements. In general,the Quartus II software can place and route the GT channels and close timing without any special designaccommodation.

The following figure shows the TX and RX parallel recovered clocks and the parallel data bus size for theregister transfer between the PMA and the core. The parallel clocks, tx_clkout and rx_clkout, are invertedin the PMA before they drive the core.


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Figure 10: Stratix V GT Channel PMA and Core Register Transfer

FPGAFabric(Core)

Receiver PMA

CDR

Deserializer

Transmitter PMA

Serializer

ATXPLL

tx_clkout

rx_clkout Parallel ClockSerial Clock

tx_parallel_data

rx_parallel_data

tx_serial_data

rx_serial_data

128

128

Divider

Reg

ister

Reg

ister

Invert parallelclock to providefull clock cycle

You can close timing for the RX PMA to core transfer in a half clock cycle, so no special design accommo-dation is required. However, the core to TX PMA transfer may require an extra half clock cycle because ofthe delay associatedwith the clock and data running in opposite directions. Closing timing can be challengingat these high data rates, especially with the 128-bit data width. A simple approach to provide more time forthe transfer is to invert the tx_clkout before driving it to the core. Applying this design technique providesa full clock cycle for the core to TX PMA register transfer.

Dynamic ReconfigurationDynamic reconfiguration allows you to change the transceiver settings without performing a fullreconfiguration of the device. Accessing the feature is done through the reconfiguration controller, whichhas a set of memory mapped registers.

The following figure shows an example of a system block diagram of the reconfiguration controller and howit interfaces with the transceiver PHY IP.


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Figure 11: System Block Diagram

to and fromEmbeddedController

TX and RXSerial Data

Avalon-MM master interface

TransceiverReconfiguration

ControllerS

M Avalon-MM slave interfaceS

reconfig_to_xcvr[<n>:0]

reconfig_mif_address[31:0]reconfig_mif_read

ReconfigurationManagementInterface

reconfig_mif_readdata[15:0]reconfig_mif_waitrequest

Streaming Data

reconfig_from_xcvr[<n>:0]

Transceiver PHY

Registers toreconfigure

User ApplicationIncluding MAC

Altera V-Series FPGA

.

.

.

.

.

.

SMMaster

M

S

MIFROM

The following figure shows the reconfiguration controller and the various features that are available for thetransceiver channels. For the Stratix VGT channel, dynamic reconfiguration is accessed through the streamermodule, which is enabled by checking theChannel/PLLReconfiguration option during the reconfigurationcontroller IP instantiation.


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Figure 12: Transceiver Reconfiguration Controller

Direct Addressing

Address Offset

0x00

0x13

0x0B

0x1B

0x2B

0x33

0x3B

0x43

0x7F

Transceiver Reconfiguration Controller

Avalon-MM Interfacereconfig_mgmt_*

Avalon-MMRegisters

Signal IntegrityFeatures

DFE

ADCE

ATXTuning

MIFStreamer

PLLReconfig

EyeQ (1)

PMAAnalog

EyeQ (1)

...

DFE

...

PMA

ADCE

...

ATX..

.

Streamer

...

PLL

...

SMEmbeddedController

...

MIF streamer module(mode 3) allowsdynamic reconfigurationof the GT channel

Note:(1) EyeQ for GT channels is available as a demo feature using the Quartus II Transceiver Toolkit. To access EyeQ for GX channels, refer to the

Altera Transceiver PHY IP Core User Guide.

Related InformationAltera Transceiver PHY IP Core User Guide

Streamer ModuleThe following table lists the addresses for the streamer module memory mapped registers and describes thefunctions of each register. For the Stratix V GT channel, dynamic reconfiguration is performed using MIFmode 3, which is different from the regular modes described in the Altera Transceiver PHY IP Core UserGuide. MIFmode 3 gives you direct access to the actual hardware registers. Youmust perform readmodifiedwrite (RMW) operations when using this mode. Select MIF mode 3 by writing 2’b11 to address 0x3A bits[3:2].

Table 2: Streamer Module Register Address

DescriptionR/WBitsPHY

AddressRegister Name

The logical channel number.RW[9:0]7'h38Logical channel number


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DescriptionR/WBitsPHY

AddressRegister Name

The physical channel number. Youmust initiatean indirect read before you can correctly readthe physical channel number.

R[9:0]7'h39Physical channel address

Error flag. Indicates one of following:

• Channel address is invalid,• PHY address is invalid, or• Offset register address is invalid.

R[9]

7'h3AControl and status

Busy flag. Indicates reconfiguration in progress.R[8]

2'b00: MIF file

2'b01: Direct write

2'b10: Reserved

2'b11: MIF mode 3 – direct physical address

RW[3:2]

Read. Initiate an indirect read. Self clear.W[1]

Write. Initiate an indirect write. Self clear.W[0]

Specify the parameter offset address.RW[15:0]7'h3BOffset

Reads back or specifies value of the parameter.RW[31:0]7'h3CData

OffsetsThe transceiver PHY IP (RX, TX, and ATX PLL) contains a set of memory mapped registers, called offsets,which correspond to the different analog parameters.

In the following table, the Offset column lists the transceiver PHY IP offset address for each parameter.Only a subset of the bits for each offset register is defined. For example, the TX VOD offset address is at0x28C and only bits [6:2] are defined for the VOD parameter setting. Some parameters, such as RX DCGain and RX AC Gain, are defined across multiple offsets.

Table 3: Stratix V GT Channel Offsets

CommentOffsetParameter

Fine tune 100 Ω termination0x28B[11:8]TX Termination

0x28B[6:3]TX Common Mode

0x28C[6:2]TX VOD

Switches depend on VOD setting0x28E[9:6]TX Main Tap Switches

0x28E[14:10]TX Pre-Tap

Switches depend on pre-tap setting0x4E9[1:0]TX Pre-Tap Switches


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CommentOffsetParameter

0x28F[6]TX Pre-Tap Invert

0x28F[4:0]TX Post-Tap

Switches depend on post-tap setting0x4E9[3:2]TX Post-Tap Switches

Fine tune 100 Ω termination0x37[9:6]RX Termination

0x37[13:10]RX Common Mode

0x34[7:2],0x34[0]RX DC Gain

0x35[15:0],0x34[15:8]RX AC Gain

0x36[9]RX Eye Enable

0x290[15:10]RX Eye Phase Step

0x36[15:10]RX Eye Vertical Step

When you perform a dynamic reconfiguration, you must perform a read-modify-write operation toan offset register and avoid corrupting other bits. Inadvertently modifying other bits may changethe transceiver setting and render the channel non-functional.

Note:

For a list of the Stratix V GT channel offset addresses and the bit setting values, refer to Appendix A.

Related InformationAppendix A – Offset Addresses on page 20

Switches and Valid SettingsThe Stratix V GT TX channel contains switches for the main tap, pre-tap, and post-tap.

Enabling more switches means more drive current, which requires higher power. Based on the tap settingsin your design, the Quartus II software sets the appropriate number of switches to provide optimalperformance while minimizing power consumption. However, when you perform dynamic reconfigurationto change the main-tap, pre-tap, and the post-tap settings, you must ensure that those combinations andthe number of switches are valid. Invalid combinations of settings and switches may result in overstressingthe TX buffer.

To ensure the device is operating under optimal conditions, adhere to two sets of rules. The first defineshow many switches you must enable to avoid overstressing the TX buffer, as shown in the following figure.By default, theQuartus II software sets the TXVOD (main-tap) to 6mA (600mV)with two switches enabled.The same table applies to the pre-tap and post-tap settings. For example, if the pre-tap or post-tap settingis ≤ 2 mA (a Quartus II setting of 10 or less), only one switch needs to be enabled. If the setting is > 2 mA(a Quartus II setting of 11 or higher), then both switches must be enabled.


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Figure 13: Valid TX VOD Settings

The second set of rules ensures that the combination of TX VOD and pre-emphasis settings are valid. TheVmax and Vmin for the VOD are calculated based on 100 Ω termination.

1. |a| + |b| + |c| ≤ 12 mA2. |b| – |a| – |c| > 1.65 mA3. (Vmax / Vmin – 1)% < 600%

where:

a = Pre-tap setting in mA (in steps of 0.2 mA)

b = TX VOD setting in mA (in steps of 2 mA)

c = Post-tap setting in mA (in steps of 0.2 mA)

Vmax = Rtermination * (|a| + |b| + |c|)

Vmin = Rtermination * (|b| – |a| – |c|)

Example 1. The Quartus II software has the following default settings:

• Pre-tap: a = 0 mA (0 * 0.2 mA)• TX VOD: b = 6 mA (3 * 2 mA)• Post-tap: c = 1 mA (5 * 0.2 mA)

The second set of rules is met as follows:

1. |a| + |b| + |c| = 0 mA + 6 mA + 1 mA = 7mA, which is ≤ 12 mA2. |b| – |a| – |c| = 6 mA - 0 mA – 1 mA = 5 mA, which is > 1.65 mA3. (Vmax / Vmin – 1)% = ((100 Ω * 7 mA) / (100 Ω * 5 mA) – 1)% = 40%, which is < 600%

Example 2. In this example, one of the rules is violated.

• Pre-tap: a = 1 mA (5 * 0.2 mA)• TX VOD: b = 4 mA (2 * 2 mA)• Post-tap: c = 1.6 mA (8 * 0.2 mA)


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The values for the second set of rules are calculated as follows:

1. |a| + |b| + |c| = 1 mA + 4 mA + 1.6 mA = 6.6 mA, which is ≤ 12 mA2. |b| – |a| – |c| = 4 mA – 1 mA – 1.6 mA = 1.4 mA, which is < 1.65 mA [violates rule]3. (Vmax / Vmin – 1)% = ((100 Ω * 6.6 mA) / (100 Ω * 1.4 mA) – 1)% = 371%, which is < 600%

In Example 2, you can reduce the pre-tap or post-tap setting or you can increase the TX VOD setting so therules are met.

When performing dynamic reconfiguration, follow both sets of rules to ensure the GT channel operates atits optimal condition.

Performing Dynamic ReconfigurationTo perform a dynamic reconfiguration of the GT channels, apply a sequence of read and write operationsto the streamer module registers of the reconfiguration controller.

Use the following procedure to change the analog settings of the GT channel:

1. Write logical channel2. Write control/status register to specify MIF mode 33. Write offset register to select parameter4. Initiate indirect read; results stored in data register5. Read current parameter value from data register6. Modify parameter value7. Write data register with new parameter value8. Initiate indirect write9. Read control/status register and check if busy signal (bit 8) is cleared

The following Tcl script examples demonstrate dynamic reconfiguration of the Stratix V GT channel. Onlya portion of the complete code is shown for simplicity. The first example shows how to change the GTchannel TX VOD setting from the default 3 (600 mV) to 2 (400 mV). The second example shows how toenable or disable the reverse serial loopback. Multiple offset addresses are accessed to enable and disable thereverse serial loopbacks.

For the complete Tcl scripts of the two examples that you can run with the system console, refer to AppendixB and Appendix C.

Example 1. Excerpts of Tcl Script to Change Stratix V GT TX VOD Setting to 2

---------------------------------------------------------# Define reconfiguration controller base address, VOD offset# address, mask, start bit, and VOD value 2 (0x3)set ADDR_RECONFIG 0x02000set ADDR_TXVOD 0x28cset MASK_TXVOD 0xffffff83set STARTBIT_TXVOD 2set value 0x3

# Write logical channel; for one duplex channel,# TX logical channel = 1wr32 $ADDR_RECONFIG 0x38 1

# Write control/status register to specify MIF mode 3; 0xc = 4'b1100wr32 $ADDR_RECONFIG 0x3a 0xc

# Write offset register to select parameter; VOD offset is 0x28cwr32 $ADDR_RECONFIG 0x3b $ADDR_TXVOD

# Initiate indirect read, 0xe = 4'b1110; results are stored in


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# data registerwr32 $ADDR_RECONFIG 0x3a 0xe

# Read current parameter value from data register, and modify# parameter valueset curval [rd32 $ADDR_RECONFIG 0x3c]set tmpval [expr $curval & $MASK_TXVOD]set newval [expr $tmpval | ($value << $STARTBIT_TXVOD)]set hexval [format "0x%x" $newval]

# Write data register with new parameter valuewr32 $ADDR_RECONFIG 0x3c $hexval

# Initiate indirect write; 0xd = 4'b1101wr32 $ADDR_RECONFIG 0x3a 0xd

# Read control/status register and check if busy signal (bit 8)# is clearedset busy [rd32 $ADDR_RECONFIG 0x3a]while {($busy & 0x100) == 0x100} {puts "Reconfiguration controller busy."}

---------------------------------------------------------

Example 2. Excerpts of Tcl Script to Enable and Disable Stratix V GT Channel Reverse Serial Loopback

---------------------------------------------------------# Procedure for setting reverse serial loopback; arguments are# physical channel and loopback typeproc setrslpbk {chan setting} {

# Reconfiguration controller base address and reverse serial# loopback offsets and valuesset ADDR_RECONFIG 0x02000set ADDR_RXRSLPBKA 0x28cset ADDR_RXRSLPBKB 0x33set ADDR_TXRSLPBK 0x28bset MASK_RXRSLPBKA 0xffffff5fset MASK_RXRSLPBKB 0xfffffffbset MASK_TXRSLPBK 0xffffcfffset STARTBIT_RXRSLPBKA 5set STARTBIT_RXRSLPBKB 2set STARTBIT_TXRSLPBK 12switch $setting {"postcdr" { set rxvaluea 0x5 set rxvalueb 0x0 set txvalue 0x3 }"precdr" { set rxvaluea 0x0 set rxvalueb 0x1 set txvalue 0x0 }"disable" { set rxvaluea 0x0 set rxvalueb 0x0 set txvalue 0x0 }default { puts "Invalid reverse serial loopback setting (must be \"postcdr\", \"precdr\", or \"disable\")" return }


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}

# Calculate logical channelset rxchan [ expr 3*$chan + 0 ]set txchan [ expr 3*$chan + 1 ]

# Reconfigure transceiver to change reverse serial loopback settingwrite $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKA $MASK_RXRSLPBKA $STARTBIT_RXRSLPBKA $rxvalueawrite $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKB $MASK_RXRSLPBKB $STARTBIT_RXRSLPBKB $rxvaluebwrite $ADDR_RECONFIG $txchan $ADDR_TXRSLPBK $MASK_TXRSLPBK $STARTBIT_TXRSLPBK $txvalue}

---------------------------------------------------------

Appendix A – Offset AddressesThe following tables list the offset address and bit setting values for the Stratix V GT channel. Items in boldare default settings. Refer to the Dynamic Reconfiguration section for further explanations about legalcombination of settings.

Table 4: Loopback Types

Offset Address and Bit SettingLoopback Type

Use PHY management register access to enable/disable serialloopback for PHY IP instance

Offset address: 0x61 (0=disable, 1=enable)

Enabling serial loopback overrides reverse serial loopbacks

Serial loopback

RX: 0x28C[7]=1, 0x28C[5]=1, 0x33[2]=0

TX: 0x28B[13:12]=11

Reverse serial loopback enable (includesCDR)

RX: 0x28C[7]=0, 0x28C[5]=0, 0x33[2]=1

TX: 0x28B[13:12]=00

Reverse serial pre-CDR loopback enable

RX: 0x28C[7]=0, 0x28C[5]=0, 0x33[2]=0

TX: 0x28B[13:12]=00

Disable reverse serial loopbacks

Table 5: TX Termination

The default setting provides 100-Ω termination.Value0x28B[11:8]TX Termination (Quartus II Setting)

R_SETTING_1611110

R_SETTING_1511101

R_SETTING_1411012


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AN-681Appendix A – Offset Addresses20 2014.01.07


Value0x28B[11:8]TX Termination (Quartus II Setting)

R_SETTING_1311003

R_SETTING_1210114

R_SETTING_1110105

R_SETTING_1010016

R_SETTING_910007

R_SETTING_801118

R_SETTING_701109

R_SETTING_6010110

R_SETTING_5010011

R_SETTING_4001112

R_SETTING_3001013

R_SETTING_2000114

R_SETTING_1000015

Table 6: TX Common Mode

0x28B[6:3]TX Common Mode (Quartus II Setting)

0000VOLT_0P80V

0001VOLT_0P75V

0010VOLT_0P70V

0011VOLT_0P65V

0100VOLT_0P60V

0101VOLT_0P55V

0110VOLT_0P50V

0111VOLT_0P35V

Table 7: TX VOD

The actual output voltage depends on the termination resistor setting.Value0x28C[6:2]TX VOD

(Quartus II Setting)

0 mA000000


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21Appendix A – Offset AddressesAN-6812014.01.07


Value0x28C[6:2]TX VOD


2 mA000011

4 mA000112

6 mA001113

8 mA011114

10 mA111115

Table 8: TX Main Tap Switches

0x28E[9:6]TX Main Tap Switches

0000No switches on

0001One switch on

0011Two switches on

0111Three switches on

1111Four switches on

Table 9: TX Pre-Tap Values

Value0x28E[14:10]TX Pre-Tap


0 mA000000

0.2 mA000011

0.4 mA000102

0.6 mA000113

0.8 mA001004

1.0 mA001015

1.2 mA001106

1.4 mA001117

1.6 mA010008

1.8 mA010019

2.0 mA0101010


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Value0x28E[14:10]TX Pre-Tap


2.2 mA0101111

2.4 mA0110012

2.6 mA0110113

2.8 mA0111014

3.0 mA0111115

Table 10: TX Pre-Tap Switches

0x4E9[1:0]TX Pre-Tap Switches

00No switches on

01One switch on

11Two switches on

Table 11: TX Pre-Tap Invert

0x28F[6]TX Pre-Tap Invert (Quartus II Setting)

0Off

1On

Table 12: TX Post-Tap Values

Value0x28F[4:0]TX Post-Tap


Disabled000000

0.2 mA000011

0.4 mA000102

0.6 mA000113

0.8 mA001004

1.0 mA001015

1.2 mA001106

1.4 mA001117

1.6 mA010008


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Value0x28F[4:0]TX Post-Tap


1.8 mA010019

2.0 mA0101010

2.2 mA0101111

2.4 mA0110012

2.6 mA0110113

2.8 mA0111014

3.0 mA0111115

3.2 mA1000016

3.4 mA1000117

3.6 mA1001018

3.8 mA1001119

4.0 mA1010020

4.2 mA1010121

4.4 mA1011022

4.6 mA1011123

4.8 mA1100024

5.0 mA1100125

5.2 mA1101026

5.4 mA1101127

5.6 mA1110028

5.8 mA1110129

6.0 mA1111030

6.2 mA1111131

Table 13: TX Post-Tap Switches

0x4E9[3:2]TX Post-Tap Switches

00No switches on

01One switch on


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0x4E9[3:2]TX Post-Tap Switches

11Two switches on

Table 14: RX Termination Value

The default setting provides 100-Ω termination.Value0x37[9:6]RX Termination (Quartus II Setting)

MIN_RTERM11110

RTERM_111101

RTERM_211012

RTERM_311003

RTERM_410114

RTERM_510105

RTERM_610016

RTERM_710007

DEF_RTERM01118

RTERM_901109

RTERM_10010110

RTERM_11010011

RTERM_12001112

RTERM_13001013

RTERM_14000114

MAX_RTERM000015

Table 15: RX Common Mode

0x37[13:10]RX Common Mode (Quartus II Setting)

0000VTT_0P8V

0001VTT_0P75V

0010VTT_0P7V

0011VTT_0P65V

0100VTT_0P6V

0101VTT_0P55V


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0x37[13:10]RX Common Mode (Quartus II Setting)

0110VTT_0P5V

0111VTT_0P35V

Table 16: RX DC Gain

The DC gains are based on simulation results.Value0x34[7:2],0x34[0]RX DC Gain


-2.1 dB000000,00

-1.3 dB000001,01

-0.7 dB000010,02

-0.2 dB000011,03

0.6 dB000111,04

1.2 dB001011,05

1.7 dB001111,06

2.5 dB011111,07

3.1 dB101111,08

3.6 dB111111,09

5.6 dB000000,110

5.9 dB000001,111

6.1 dB000010,112

6.3 dB000011,113

6.5 dB000111,114

6.7 dB001011,115

6.9 dB001111,116

7.2 dB011111,117

7.4 dB101111,118

7.6 dB111111,119


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Table 17: RX AC Gain

The AC gains are based on simulation results.Value

(at 9.5 GHz)

0x35[15:0],0x34[15:8]RX AC Gain


11.1 dB0000000000000000,000000000

11.8 dB0000000011110000,000011111

12.1 dB0000000011110000,000000002

12.4 dB0000111111110000,111111113

12.6 dB0000111111110000,000011114

12.9 dB0000111111110000,000000005

13.1 dB1111111111111111,111111116

13.4 dB1111111111110000,111111117

13.9 dB1111111111110000,000000008

Table 18: RX Eye Enable

0x36[9]RX Eye Enable

0Disable

1Enable

Table 19: RX Eye Phase Step

Value0x290[15:10]RX Eye Phase Step

STEP11110000

STEP21110011

STEP31110112

STEP41110103

STEP51111104

STEP61111115

STEP71111016

STEP81111007

STEP91101008

STEP101101019


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STEP1111011110

STEP1211011011

STEP1311001012

STEP1411001113

STEP1511000114

STEP1611000015

STEP1701000016

STEP1801000117

STEP1901001118

STEP2001001019

STEP2101011020

STEP2201011121

STEP2301010122

STEP2401010023

STEP2501110024

STEP2601110125

STEP2701111126

STEP2801111027

STEP2901101028

STEP3001101129

STEP3101100130

STEP3201100031

STEP3300100032

STEP3400100133

STEP3500101134

STEP3600101035

STEP3700111036

STEP3800111137


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STEP3900110138

STEP4000110039

STEP4100010040

STEP4200010141

STEP4300011142

STEP4400011043

STEP4500001044

STEP4600001145

STEP4700000146

STEP4800000047

STEP4910000048

STEP5010000149

STEP5110001150

STEP5210001051

STEP5310011052

STEP5410011153

STEP5510010154

STEP5610010055

STEP5710110056

STEP5810110157

STEP5910111158

STEP6010111059

STEP6110101060

STEP6210101161

STEP6310100162

STEP6410100063


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Table 20: RX Eye Vertical Step

Value0x36[15:10]RX Eye Vertical Step

VERT_0MV0000000

VERT_10MV0000011

VERT_20MV0000102

VERT_30MV0000113

VERT_40MV0001004

VERT_50MV0001015

VERT_60MV0001106

VERT_70MV0001117

VERT_80MV0010008

VERT_90MV0010019

VERT_100MV00101010

VERT_110MV00101111

VERT_120MV00110012

VERT_130MV00110113

VERT_140MV00111014

VERT_150MV00111115

VERT_160MV01000016

VERT_170MV01000117

VERT_180MV01001018

VERT_190MV01001119

VERT_200MV01010020

VERT_210MV01010121

VERT_220MV01011022

VERT_230MV01011123

VERT_240MV01100024

VERT_250MV01100125

VERT_260MV01101026


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VERT_270MV01101127

VERT_280MV01110028

VERT_290MV01110129

VERT_300MV01111030

VERT_310MV01111131

VERT_320MV10000032

VERT_330MV10000133

VERT_340MV10001034

VERT_350MV10001135

VERT_360MV10010036

VERT_370MV10010137

VERT_380MV10011038

VERT_390MV10011139

VERT_400MV10100040

VERT_410MV10100141

VERT_420MV10101042

VERT_430MV10101143

VERT_440MV10110044

VERT_450MV10110145

VERT_460MV10111046

VERT_470MV10111147

VERT_480MV11000048

VERT_490MV11000149

VERT_500MV11001050

VERT_510MV11001151

VERT_520MV11010052

VERT_530MV11010153

VERT_540MV11011054


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VERT_550MV11011155

VERT_560MV11100056

VERT_570MV11100157

VERT_580MV11101058

VERT_590MV11101159

VERT_600MV11110060

VERT_610MV11110161

VERT_620MV11111062

VERT_630MV11111163

Related InformationDynamic Reconfiguration on page 12

Appendix B – Example 1Example 1 provides an executable system console Tcl script that applies dynamic reconfiguration to changethe Stratix V GT channel TX VOD setting from the default value 3 (600 mV) to 2 (400 mV).

-----------------------------------------------# Procedure to open JTAG connectionproc open_jtag {} {set path [ lindex [ get_service_paths master ] 0 ]open_service master $path}

# Procedure to close JTAG connectionproc close_jtag {} {set path [ lindex [ get_service_paths master ] 0 ]close_service master $path}

# Procedure to read from Avalon memory mapped registerproc rd32 {base offset} {set path [ lindex [ get_service_paths master ] 0 ]set address [format "0x%x" [expr $base + ($offset<<2)]]set val [ master_read_32 $path $address 1 ]puts "Reading address = $offset ($address); value = $val"return $val }

# Procedure to write to Avalon memory mapped registerproc wr32 {base offset value} {set path [ lindex [ get_service_paths master ] 0 ]set address [format "0x%x" [expr $base + ($offset<<2)]]set val [format "0x%x" $value]puts "Writing address = $offset ($address); value = $val"master_write_32 $path $address $val }


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AN-681Appendix B – Example 132 2014.01.07


# Define reconfiguration controller base address, VOD offset # address, mask, start bit, and VOD value 2 (0x3)set ADDR_RECONFIG 0x02000set ADDR_TXVOD 0x28cset MASK_TXVOD 0xffffff83set STARTBIT_TXVOD 2set value 0x3

# Write logical channel; for one duplex channel, # TX logical channel = 1 wr32 $ADDR_RECONFIG 0x38 1

# Write control/status register to specify MIF mode 3; 0xc = 4'b1100wr32 $ADDR_RECONFIG 0x3a 0xc

# Write offset register to select parameter; VOD offset is 0x28cwr32 $ADDR_RECONFIG 0x3b $ADDR_TXVOD

# Initiate indirect read, 0xe = 4'b1110; results are stored in# data registerwr32 $ADDR_RECONFIG 0x3a 0xe

# Read current parameter value from data register, and modify # parameter valueset curval [rd32 $ADDR_RECONFIG 0x3c]set tmpval [expr $curval & $MASK_TXVOD]set newval [expr $tmpval | ($value << $STARTBIT_TXVOD)]set hexval [format "0x%x" $newval]

# Write data register with new parameter valuewr32 $ADDR_RECONFIG 0x3c $hexval

# Initiate indirect write; 0xd = 4'b1101wr32 $ADDR_RECONFIG 0x3a 0xd

# Read control/status register and check if busy signal (bit 8)# is clearedset busy [rd32 $ADDR_RECONFIG 0x3a]while {($busy & 0x100) == 0x100} {puts "Reconfiguration controller busy."}

Appendix C – Example 2Example 2 provides an executable system console Tcl script that applies dynamic reconfiguration to enableand disable the Stratix V GT Channel reverse serial loopbacks. After executing the Tcl script in the systemconsole, run any of the following commands to enable or disable the loopbacks. Replace the<physical_channel> with the appropriate channel number.

setrslpbk <physical_channel> postcdr

setrslpbk <physical_channel> precdr

setrslpbk <physical_channel> disable

-----------------------------------------------# Procedure to open JTAG connectionproc open_jtag {} {set path [ lindex [ get_service_paths master ] 0 ]open_service master $path}


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33Appendix C – Example 2AN-6812014.01.07


# Procedure to close JTAG connectionproc close_jtag {} {set path [ lindex [ get_service_paths master ] 0 ]close_service master $path}

# Procedure to read from Avalon memory mapped registerproc rd32 {base offset} {set path [ lindex [ get_service_paths master ] 0 ]set address [format "0x%x" [expr $base + ($offset<<2)]]set val [ master_read_32 $path $address 1 ]puts "Reading address = $offset ($address); value = $val"return $val}

# Procedure to write to Avalon memory mapped registerproc wr32 {base offset value} {set path [ lindex [ get_service_paths master ] 0 ]set address [format "0x%x" [expr $base + ($offset<<2)]]set val [format "0x%x" $value]puts "Writing address = $offset ($address); value = $val"master_write_32 $path $address $val}

# Procedure for writing to reconfiguration controller to perform# dynamic reconfigurationproc write {base chan offset mask startbit value} {open_jtagwr32 $base 0x38 $chanwr32 $base 0x3a 0xcwr32 $base 0x3b $offsetwr32 $base 0x3a 0xeset curval [rd32 $base 0x3c]set tmpval [expr $curval & $mask]set newval [expr $tmpval | ($value << $startbit)]set hexval [format "0x%x" $newval]wr32 $base 0x3c $hexvalwr32 $base 0x3a 0xdset busy [rd32 $base 0x3a]while {($busy & 0x100) == 0x100} { puts "Reconfiguration controller busy." }close_jtag}

# Procedure for reading from PHY IP through the reconfiguration # controllerproc read {base chan offset mask startbit} {open_jtagwr32 $base 0x38 $chanwr32 $base 0x3a 0xcwr32 $base 0x3b $offsetwr32 $base 0x3a 0xeset busy [rd32 $base 0x3a]while {($busy & 0x100) == 0x100} { puts "Reconfiguration controller busy." }set tmpmask [expr $mask ^ 0xffffffff]set curval [rd32 $base 0x3c]set tmpval [expr ($tmpmask & $curval) >> $startbit]set hexval [format "0x%x" $tmpval]close_jtagreturn $hexval}


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AN-681Appendix C – Example 234 2014.01.07


# Procedure for setting reverse serial loopback; arguments are# physical channel and loopback typeproc setrslpbk {chan setting} {

# Reconfiguration controller base address and reverse serial# loopback offsets and valuesset ADDR_RECONFIG 0x02000set ADDR_RXRSLPBKA 0x28cset ADDR_RXRSLPBKB 0x33set ADDR_TXRSLPBK 0x28bset MASK_RXRSLPBKA 0xffffff5fset MASK_RXRSLPBKB 0xfffffffbset MASK_TXRSLPBK 0xffffcfffset STARTBIT_RXRSLPBKA 5set STARTBIT_RXRSLPBKB 2set STARTBIT_TXRSLPBK 12switch $setting {"postcdr" { set rxvaluea 0x5 set rxvalueb 0x0 set txvalue 0x3 }"precdr" { set rxvaluea 0x0 set rxvalueb 0x1 set txvalue 0x0 }"disable" { set rxvaluea 0x0 set rxvalueb 0x0 set txvalue 0x0 }default { puts "Invalid reverse serial loopback setting (must be \"postcdr\", \"precdr\", or \"disable\")" return }}

# Calculate logical channelset rxchan [ expr 3*$chan + 0 ]set txchan [ expr 3*$chan + 1 ]

# Reconfigure transceiver to change reverse serial loopback settingwrite $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKA $MASK_RXRSLPBKA $STARTBIT_RXRSLPBKA $rxvalueawrite $ADDR_RECONFIG $rxchan $ADDR_RXRSLPBKB $MASK_RXRSLPBKB $STARTBIT_RXRSLPBKB $rxvaluebwrite $ADDR_RECONFIG $txchan $ADDR_TXRSLPBK $MASK_TXRSLPBK $STARTBIT_TXRSLPBK $txvalue}

Document Revision History

Table 21: Document Revision History

ChangesVersionDate

• Added note to Figure 12.• Removed "EyeQ for Stratix V GT Channels" section.

2014.01.07January 2014


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35Document Revision HistoryAN-6812014.01.07


ChangesVersionDate

Initial release.2013.03.29March 2013


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AN-681Document Revision History36 2014.01.07


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Stratix V GT Device Design Guidelines - Altera · design to ensure your Stratix V GT system can meet the low BER, ... Stratix V GT Device Design Guidelines Altera Corporation Send