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SPEED-INDEPENDENT FLOATING POINT COPROCESSOR
Stepchenkov Yuri, Zakharov Victor, Rogdestvenski Yuri, Diachenko Yuri, Morozov Nickolai, Stepchenkov
Dmitri
Institute of Informatics Problems, Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences, IPI RAS, Moscow, Russian Federation
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Contents
Why Speed-Independent circuits? Structure chart of SI-Coprocessor Ternary ST-coding Simplified indication SI-coprocessor’s pipeline SI-coprocessor’s features Conclusions
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Why Speed-Independent circuits?
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They reduce power consumption due to removing both clock generator, and "clock tree" out of a circuit
They have wide workability range on power supply and temperature
Divider & Square Rooter, 0.18
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MOPS
Die, mm2
ΔUdd*ΔT
Consumption, %Synchron, “SRT-4” Synchron, “Newton” Quasi-SI, “SRT-2”
ParameterVariant
Maximum performance at any environment
Extended workability range
Constant faults detection
Average power consumption
Minimum noise level
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Projected part of SI-logic (ITRS)
Usa
ge o
f S
I-ne
ts in
a d
esig
n,
%
Years
Structure chart of SI-FPC
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Booth multiplier
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Ternary ST-coding
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Synchronous redundant code
Self-Timed redundant (ternary) code
State Binary code
State ST ternary code
A B Ap Am An
+1 1 0 +1 1 0 0
0 0 0 0 0 0 1
–1 0 1 –1 0 1 0
N/A 1 1 spacer 0 0 0
Ternary SI-adder
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Ternary SI-adder
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Indication subcircuit
Dual-rail SI-adder
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Dual-rail SI-adder
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Dual-rail Wallace tree
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1700 transistors, 7 stages
Ternary Wallace tree
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2190 transistors, 4 stages
Simplified indication
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Bitwise indicators
Full indication only in spacer phase
Pipeline organization: Top view
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Pipeline organization:One stage
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One bit of input register
InpR
SI FPC’s parameters
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Parameter ValueComplexity, transistors 315 000
Die size, mm2 0.47
Performance, Gflops 0.54
Latency, ns 1.9
Power consumption, mW/Gflops
450
Testing SI-Coprocessor
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SI FPC
First result
Compa-rator
OK
Data
Conclusions At first time in the world, really SI-
FPC unit performing FMA operation was implemented
Usage of ternary ST-code provided best performance of the Wallace tree
Simplified indication allowed for reducing both the complexity and work phase time
Two-stage pipeline sufficiently decreased hardware cost at minimal drop of performance
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Thanks!
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Contacts Director: academician Sokolov I.A. Address: Institute of Informatics Problems
of the Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences (IPI RAS), Moscow, Russian Federation, 119333, Vavilova str., 44, b.2
Tel: +7 (495) 137 34 94 Fax: +7 (495) 930 45 05 E-mail: [email protected] Stepchenkov Y.A., tel. +7 (495) 671 15 20,
[email protected] RAS EWDTS-2015 22
