4
Statistics • 1670 components • 5839 solder joints • 4 routing layers • 6 power planes • 1858 vias • total trace length 35 m • dimensions 220 x 233.35 mm • 3 FPGA’s (1 P/N, 2 designs) ARM board (1/14/2011)

Statistics 1670 components 5839 solder joints 4 routing layers 6 power planes 1858 vias total trace length 35 m dimensions 220 x 233.35 mm 3 FPGA’s (1

Embed Size (px)

Citation preview

Page 1: Statistics 1670 components 5839 solder joints 4 routing layers 6 power planes 1858 vias total trace length 35 m dimensions 220 x 233.35 mm 3 FPGA’s (1

Statistics

• 1670 components

• 5839 solder joints

• 4 routing layers

• 6 power planes

• 1858 vias

• total trace length 35 m

• dimensions 220 x 233.35 mm

• 3 FPGA’s (1 P/N, 2 designs)

ARM board (1/14/2011)

Page 2: Statistics 1670 components 5839 solder joints 4 routing layers 6 power planes 1858 vias total trace length 35 m dimensions 220 x 233.35 mm 3 FPGA’s (1

ARM board (1/14/2011)

“Design” is ~finished but a few practical technicalities remain:• setup gerber output• QFN (ADC) pad/paste/via design, then 3 traces to route through it• some plane segmentation needs improvement• a few clearance violations and overlap errors (line vertex slightly off-location) need to be fixed• double-check CPCI connector footprint & other critical mechanical features• plugged via specification (add a new drawing layer & segregate via types)• fab drawing• check line widths; check via usage (3 sizes, maybe some wrong types to catch)• ANY FEEDBACK? CHANGES REQUESTED? QUESTIONS?• complete “skeleton” FPGA designs and verify pinout is ok (is 90% done for FE)• final design checks and gerber prep• → RFQ [ 1/17/2011 ] and order boards (probably 18 boards, Sierra)• component value cleanup (can happen after fab submission)• order remaining components• need to change component values in cable equalization circuit (1 day)• → RFQ [ 1/24/2011 ] and order assembly (3 boards, Sierra)

Page 3: Statistics 1670 components 5839 solder joints 4 routing layers 6 power planes 1858 vias total trace length 35 m dimensions 220 x 233.35 mm 3 FPGA’s (1

ARC status (1/14/2011)

Initial checkout of the board continues at ANL• Have made some progress on the microcontroller/FPGA interface, however there are some delays due to another engineer who is needed to help with this, being called off to another project• Lab computer setup delayed by remote access issues for Tonko. GV points out preliminary checkout of the SIU link can happen with old DDL software. This hasn’t happened yet, but I think the point is now understood.• Nevertheless, just heard from Hal that Tonko has access since yesterday to the computer and could set it up. (Of course, just now is run 11 setup, not great timing.)• ARM-ARC interface document being finalized by John. Some changes to the interface based on ARC and ARM design experience.• Expected shipment of first ARC from ANL to IU today or Monday. Board only, firmware to follow at a later date.

Page 4: Statistics 1670 components 5839 solder joints 4 routing layers 6 power planes 1858 vias total trace length 35 m dimensions 220 x 233.35 mm 3 FPGA’s (1

ABC status (1/14/2011)

ABC = “ARM Back-of-Crate” (cable connector board)• Bob Abruzzio is doing this. Need an update (at meeting I hope).• Layout is nearly complete when I last saw it, gave a few small change requests to him. Should be done by now if he has been able to work on this. I don’t know what other tasks may conflict.