State of Chisel - GitHub › chisel-lang › ccc... · Chisel 3.0, FIRRTL, and Beyond Chisel Community Conference China 2019 (CCC19 China) Presented by Edward Wang Slides by Adam

CCC19 Shanghai: Edward Wang, Adam Izraelevitz

Chisel 3.0, FIRRTL, and BeyondChisel Community Conference China 2019 (CCC19 China)

Presented by Edward WangSlides by Adam Izraelevitz

State of Chisel



HDL Wars: A New Hope● In 2010, the HW industry was in a difficult place

○ Dennard Scaling had ended○ Moore’s Law was on its way out

● Demand for computation kept growing○ New applications○ More performance for less power/area○ Only option was to design more complicated, specialized hardware

● Designing hardware was so difficult○ Billions of transistors○ Design complexity

● Meanwhile, in a small lab in Berkeley, a solution was brewing....

3


Instead of writing multiple RTL instances, write one instance generator that uses meta-programming for powerful parameterization

Type-Safety

Hardware Generators: Type-Safe Meta-Programming for RTL

Design Reuse Powerful Language Features4


No Loss of Expressibility: “Verilog-like” Chisel

FIR (Finite Impulse Response) Filter - 3-point moving average

What about >3 points?What about weighted averages?

We want a generic FIR filter! 5


FIR Filter - Parameterized by bitwidth and coeffients with no loss of expressibility or performance.

Meta-programming enables powerful parameterization.

Massive Increase in Parameterizability: “Software-like” Chisel

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FIR Filter - Parameterized by bitwidth and coeffients with no loss of expressibility or performance.

Meta-programming enables powerful parameterization.

Massive Increase in Parameterizability: “Software-like” Chisel

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Hired Jonathan Bachrach (2010)

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By the End of ParLab (2013), We Learned....

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12 Grad Students Chisel Chips


And so, in late 2013, the problem of designing hardware was forever solved.

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Just kidding.

11


Improving RTL Design ≠ Solving The Hardware Design Loop

* from “How to Draw Chip and Dale booklet”. (Walt Disney, 1955) 12


What had to change?

Hardware Design Ecosystem External CollaborationsStable and User-Friendly API

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Platform-Specific or Application-Specific RTL Changes

IBM 45nm SOI

ST 28nm FDSOI

Zynq FPGA

Chip RTL+ scan interface+ snapshotting+ interactive debug + clock-generators

+ SRAMs with init+ specialized layout

+ SRAM macros+ modified module hierarchy+ specialized layout

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Platform-Specific or Application-Specific RTL Changes

IBM 45nm SOI

ST 28nm FDSOI

Zynq FPGA

Chip RTL+ scan interface+ snapshotting+ interactive debug + clock-generators

+ SRAMs with init+ specialized layout

+ SRAM macros+ modified module hierarchy+ specialized layout

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Realization: We need a software stack, but for hardware

libraries

language

compiler

platforms

projects

x86 ARM RISC-Vtransforms

clang

HwachaRocketBOOM

rocketchip chisel-utils

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FIRRTLChisel Frontend


For an ecosystem, we needed a hardware compiler infrastructure

FPGA Snapshotting

FPGA Assertions

FPGA FAME-1

ChiselVerilog Other languages

FIRRTLASIC SRAMs

Floorplanning Hints

RetimingC++Verilog Scala

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BIST/JTAG Stitching Early Area Estimation


Developing, Porting, Code Reviews, Testing, and so forth

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Spring 2015

Summer 2015

Fall 2015

Winter 2015

Spring 2016

Summer 2016

Fall 2016

Winter 2016

Spring 2017

Summer 2017

Fall 2017

Designed FIRRTL Compiler

Designed Chisel 3 Frontend

Ported RocketChip

Ported Chisel Testers

Added Fixed-Point Type

Added Analog Type

Added multi-clock

Released Chisel 3.0.0

Released FIRRTL 1.0.0


What had to change?


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Chisel 3.0.0Reg(UInt(3.W))RegNext(3.U)RegInit(3.U)Reg(chiselTypeOf(3.U))

Emphasis on Clarity

1. Register of type UInt, width of 32. Register whose next cycle’s value is 33. Register whose initial value is 34. Register no initial value and width of 2

20

Reg(UInt(3))

Chisel 2.0.01. Register of type UInt, width of 32. Register whose next cycle’s value is 33. Register whose initial value is 34. Register no initial value and width of 2


Chisel 3.0.0Reg(UInt(3.W))RegNext(3.U)RegInit(3.U)Reg(chiselTypeOf(3.U))

Emphasis on Clarity

1. Register of type UInt, width of 32. Register whose next cycle’s value is 33. Register whose initial value is 34. Register no initial value and width of 2

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Reg(UInt(3))

Chisel 2.0.01. Register of type UInt, width of 32. Register whose next cycle’s value is 33. Register whose initial value is 34. Register no initial value and width of 2


What had to change?


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Documentation, Documentation, Documentation

23


Bootc

amps

and T

utoria

ls

24


Bootc

amps

and T

utoria

ls

25


Open-Development via Github Issues/Pull Requests

26


Stack Overflow!

27


Academic Impact: 338 citations (as of 2019)

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Active Users (That We Know Of)

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Looking Forward

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Chisel3 Github Stars

Where is Chisel headed?

31

Githu

b Star

s

Time


Future Areas of Growth

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Diversify and Strengthen Community

Develop Needed Features and Provide Timely Support

Formalize Governance for Ecosystem Stability

In-Person Meetups

Open Dev Meetings

Commercial Collaboration

Enable Passionate Individuals

Standardize Verification Infra

Generating Hardware Collateral

Preserve Backwards Compatibility

Advanced Circuit Transformations

CHIPS Alliance Partnership

Constitution and Member Rights

Communicate Direction/Roadmap

Closer Commercial Partnerships


Future Areas of Growth

33

Diversify and Strengthen Community

Develop Needed Features and Provide Timely Support

Formalize Governance for Ecosystem Stability

In-Person Meetups

Open Dev Meetings

Commercial Collaboration

Enable Passionate Individuals

Standardize Verification Infra

Generating Hardware Collateral

Preserve Backwards Compatibility

Advanced Circuit Transformations

CHIPS Alliance Partnership

Constitution and Member Rights

Communicate Direction/Roadmap

Closer Commercial Partnerships


Excited? Intrigued? Skeptical?

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35


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Shoutout to Chiselers out there! (And many more!!)

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Documents

State of Chisel - GitHub › chisel-lang › ccc... · Chisel 3.0, FIRRTL, and Beyond Chisel Community Conference China 2019 (CCC19 China) Presented by Edward Wang Slides by Adam