Digital Electronics 2: Introduction

Martin Schoeberl

Technical University of DenmarkEmbedded Systems Engineering

February 6, 2020

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Overview

I Motivation and the digital abstractionI Course organizationI Languages for digital hardware designI A first round of ChiselI Tools and tool setup

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A BIG Chip

I https://singularityhub.com/2019/08/26/this-giant-ai-chip-is-the-size-of-an-ipad-and-holds-1-2-trillion-transistors/

I 1.2 × 1012 transistorsI If you design 1 gate (= 4 transistors) per second

I It takes you 10 thousand years!I This calls for some abstraction

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Digital Systems are Everywhere

I Digital systems are all over in our liveI No more analog mediaI CD, mobile phone, TV, DVD,... all digital nowI Analog circuits only at the edgeI The rest is processed in digitalI If performance allows, functions are moved to softwareI But processor speedup has slowed downI Algorithms are moved back into hardware

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FPGAs in the Cloud

I High performance algorithm in an FPGAI An FPGA in the cloudI Intel offers FPGAs for servers

I There was some reason why Intel bought AlteraI We need digital designers to make this workI A good time to be a digital designer

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The Digital Abstraction

I Just two values: 0 and 1,or low and hight

I Represented as voltageI Digital signals tolerate

noiseI Digital Systems are simple,

just:I Combinational circuits

andI Registers

AND

OR

ba

clogic

D Q

clock

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Hardware Design in DK

I Demant (former Oticon)I WidexI GN ReSoundI MicrosemiI Intel (former Altera) DenmarkI probably some more...I

I They are all hiring

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Example Design from Microsemi DK

A picture of the board with the $50k Xilinx FPGA. This is a newboard and is developed for ASIC prototyping in order to dopre-silicon validation as well as SW development. We have onthe board currently mapped our current project: 8port industrialgigabit Ethernet switch with full TSN, CPU system ARM A7 withDDR, USB, PCIe and hardware security engines (SHA, AES)for secure boot of Linux and on the fly DRAM encryption. Wescale and map all the digital logic to the FPGA.I Show the picture

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Digital Design within an EE Master

I Not an obvious choice, as there is no specialization indigital systems

I Select some of the following coursesI 02155: Computer Architecture and EngineeringI 02203: Design of Digital SystemsI 02211: Advanced Computer ArchitectureI 02205: VLSI DesignI 02217: Design of Arithmetic ProcessorsI 02204: Design of Asynchronous CircuitsI 02209: Test of Digital Systems

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Computer Engineering Education at DTU

I On the border between hardware and softwareI Very well payed jobs :-)I Not an easy choice at DTU as well

I No BSc availableI Between EE and CS

I Start with Bsc. in EEI Specialization in Indlejrede systemer og programmering

I 02155: Computer Architecture and EngineeringI 02105: Algoritmer og datastrukturer

I Continue as MSc. in Computer Science and EngineeringI Specialization in

I Digital SystemsI Embedded and Distributed Systems

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Web Resources

I DTU InsideI Vending machine documentI Project report hand in

I Course websiteI General information, starting point

I Lab websiteI Lab material on GitHub

I Chisel book websiteI Download the free PDF

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Organization and Workload

I Usually 2 hours lectures and 2 hours supervised labI 5 ECTS is equivalent to 9 hours per weekI That means 5 hours work on your own

I Do some reading, prepare for the lecture and labI Get the tools installed on your laptopI You have an FPGA board, experiment with it

I You will learn a lot in this course, it will make you a better:I engineerI hardware designerI programmer, andI computer user in general

I Try to have fun with building stuff that is real!

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Communication and Getting Help

I Several sources of information:I The Internet, Google, and StackoverflowI Your fellow students (e.g., via Slack)I The TAs: Simon, Kasper, and AnthonI Me

I We will use Slack for easy communication (if ok for you)I https://de2019.slack.com/

I You can always just knock on my door or shoot me anemail

I There is also anonymous feedback

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Anonymous Feedback

I Inbox available at: Anonymous InboxI Simple Google form without revealing your identityI I will get notified by an emailI Use when you want to complain, give feedback, but also

when you like something ;-)I Even when frustrated, please be polite, a human is reading

this

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Cheating and Plagiarism

I It is ok and good practice to discuss problems andsolutions with your fellow students

I But you need to hand in your own solutionI Copying stuff or offering stuff for copying is cheatingI Copying material from somewhere is plagiarism and

copyright violationI Cheating is handled quite rigorous at DTU, you might get

expelledI Using source code control (GitHub) is good practiceI However, keep it private. Otherwise you might contribute to

cheating

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This is an Open-Access/Open-Source Course

I Almost all material is public visibleI Slides are open accessI Lab material is open accessI Hosted on GitHub

I You can contribute with a pull requestI Becoming an author of this course :-)

I The Chisel book is freely available

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Lab Work

I Some paper and pencil exercisesI Most work on designing digital circuits with a hardware

description languageI Builds up to the final project: a vending machineI The vending machine and the report are graded

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A Vending Machine from 1952

Source: Minnesota Historical Society, CC BY-SA 2.0

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The Vending Machine

I Final project is a vending machineI Inputs: coins, buyI Display: price and current ammountI Output: release can or errorI Small challenge to multiplex the displayI State machine with data path is the brain of the VMI Will be guided step by step over several weeksI More details next weekI VM in hardware versus VM in software

I This is an exercise that you can solve with reasonable effort

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Motivating Example for Chisel:Lipsi: Probably the Smallest Processor in the World

I Tiny processorI Simple instruction setI Shall be small

I Around 200 logic cells, one FPGA memory blockI Hardware described in ChiselI Available at https://github.com/schoeberl/lipsiI Usage

I Utility processor for small stuffI Could be used for your vending machineI In teaching for introduction to computer architecture

I The design took place on the island Lipsi

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The Design of Lipsi on Lipsi

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Lipsi Implementation

I Hardware described in ChiselI Tester in ChiselI Assembler in Scala

I Core case statement about 20 linesI Reference design of Lipsi as software simulator in ScalaI Testing:

I Self testing assembler programsI Comparing hardware with a software simulator

I All in a single programming language!I All in a single programI How much work is this?

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Chisel is Productive

I All coded and tested in less than 14 hours!

I The hardware in ChiselI Assembler in ScalaI Some assembler programs (blinking LED)I Simulation in ScalaI Two testers

I BUT, this does not include the design (done on paper)

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Motivating Example: Lipsi, a Tiny Processor

I Show in IntelliJ (if beamer allows)

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The Slides are Online

I http://www2.imm.dtu.dk/courses/02139/

I https://github.com/schoeberl/chisel-book/tree/master/slides

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Why Chisel Instead of VHDL/Verilog/SystemVerilog?

I Company O does Verilog, company W does VHDLI Why Chisel?

I We learn principles of digital design, not toolsI We pick a language that is modern and productive

I When knowing principles, switching the language is amatter of a week

I You are the future engineers and shall learn new toolsI You may then bring Chisel into the company

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More on Chisel Success Stories

I Last week at CCC 2020 in silicon valleyI 90 participantsI More than 30 different chip companies presentI Several companies are looking into ChiselI IBM did an open-source PowerPCI SiFive is a RISC-V startup success

I High productivity with ChiselI Open-source Rocket chip

I Esperanto uses the BOOM processor in ChiselI Google did a machine learning processorI Intel is looking at ChiselI Chisel is open-source, if there is a bug you can fix it

I You can even contribute to the Chisel ecosystem :-)

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Introduction to Chisel

I Get an idea what Chisel isI Will show you code snippets

I Basic hardware constructs in ChiselI Pointers to more informationI Have your first Chisel design running in an FPGA!

I From 0 to 100 in one afternoon

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Chisel

I A hardware construction languageI Constructing Hardware In a Scala Embedded LanguageI If it compiles, it is synthesisable hardwareI Say goodby to your unintended latches

I Chisel is not a high-level synthesis languageI Single source for two targets

I Cycle accurate simulation (testing)I Verilog for synthesis

I Embedded in ScalaI Full power of Scala availableI But to start with, no Scala knowledge needed

I Developed at UC Berkeley

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The C Language Family

C

Verilog

SystemVerilog

C++

SystemC

Java

Scala

Chisel

C#

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Other Language Families

Algol 68

Ada

VHDL

Python

MyHDL

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Some Notes on Scala

I Object orientedI FunctionalI Strongly typed

I With very good type inferenceI Could be seen as Java++I Compiled to the JVMI Good Java interoperability

I Many libraries availableI You can write your testing code in Java

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Chisel vs. Scala

I A Chisel hardware description is a Scala programI Chisel is a Scala libraryI When the program is executed it generates hardwareI Chisel is a so-called embedded domain-specific language

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A Small Language

I Chisel is a small languageI On purposeI Not many constructs to rememberI The Chisel Cheatsheet fits on two pagesI The power comes with Scala for circuit generatorsI With Scala, Chisel can grow with you

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Tool Flow for Chisel Defined Hardware

Hello.scala

scalac

Hello.class

ChiselJVM

Hello.fir

scala.libchisel3.lib

Verilog Emitter

JVMTreadle

JVM

Hello.vHello.vcd

FIRRTLJVM

Chisel TesterJVM

good/bad

GTKWave CircuitSynthesis

Hello.bit

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Signal Types

I All types in hardware are a collection of bitsI The base type in Chisel is BitsI UInt represents an unsigned integerI SInt represents a signed integer (in two’s complement)

Bits(8.W)

UInt(8.W)

SInt(10.W)

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Number of Bits: n.W

I A collection of bits has a widthI The width is the number of bitsI Is written as number followed by .WI Following example shows the width of n

n.W

Bits(n.W)

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Constants

I Constants can represent signed or unsigned numbersI We use .U and .S to distinguish

0.U // defines a UInt constant of 0

-3.S // defines a SInt constant of -3

I Constants can also be specified with a width

8.U(4.W) // An 4-bit constant of 8

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Hexadecimal and Binary Representation

I We can specify constants with a different baseI May come handy sometimes

"hff".U // hexadecimal representation of

255

"o377".U // octal representation of 255

"b1111_1111".U // binary representation of 255

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Boolean Values

I Type for logical valuesI Can be true or falseI Almost exchangeable with UInt(1.W)I Sometimes a signal, such as valid, may be better

represented by a Boolean type

Bool()

true.B

false.B

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Combinational Circuits

I Chisel uses Boolean operators, similar to C or JavaI & is the AND operator and | is the OR operatorI The following code is the same as the schematicsI val logic gives the circuit/expression the name logicI That name can be used in following expressions

AND

OR

ba

clogic

val logic = (a & b) | c

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Standard Logic Operations

val and = a & b // bitwise and

val or = a | b // bitwise or

val xor = a ˆ b // bitwise xor

val not = ˜a // bitwise negation

I Note that we do not need to define the width of the valuesI Note also that this is hardwareI All expressions are evaluated in parallelI Order does not matter

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Arithmetic Operations

I Same as in Java or CI The width of the result is automatically computedI E.g., the width of the multiplication is the sum of the width

of a and the width of b

val add = a + b // addition

val sub = a - b // subtraction

val neg = -a // negate

val mul = a * b // multiplication

val div = a / b // division

val mod = a % b // modulo operation

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Wires

I A signal (or wire) can be first definedI And later assigned an expression with :=

val w = Wire(UInt())

w := a & b

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Chisel Defined Hardware Operators

Operator Description Data types

* / % multiplication, division, modulus UInt, SInt+ - addition, subtraction UInt, SInt=== =/= equal, not equal UInt, SInt, returns Bool> >= < <= comparison UInt, SInt, returns Bool<< >> shift left, shift right (sign extend on SInt) UInt, SInt˜ NOT UInt, SInt, Bool& | ˆ AND, OR, XOR UInt, SInt, Bool! logical NOT Bool&& || logical AND, OR Bool

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Subfields and Concatenation

A single bit can be extracted as follows:

val sign = x(31)

A subfield can be extracted from end to start position:

val lowByte = largeWord(7, 0)

Bit fields are concatenated with Cat:

val word = Cat(highByte, lowByte)

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A Multiplexer

ay

sel

b

I A Multiplexer selects between alternativesI So common that Chisel provides a construct for itI Selects a when sel is true.B otherwise b

val result = Mux(sel, a, b)

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Conditional Update

I With when we can express a conditional updateI The resulting circuit is a multiplexerI In contrast to the Mux component, we can have several

assignments in the when blockI The rule is the the last enabled assignment counts

I Here the order of statements has a meaning

val w = Wire(UInt())

w := 0.U

when (cond) {

w := 3.U

}

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The World of Combinational Logic

I With the shown operations (logic, arithmetic, Mux) allpossible combinational circuits can be described

I Even the Mux is already syntactic sugarI A Mux is basically: (a & sel) | (b & !sel)

I But Chisel provides further constructs for more elegantdescription of circuits

I Stay tuned!

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Register

I A register is a collection of flip-flopsI Updated on the rising edge of the clockI May be set to a value on resetI Clock and reset are implicitly connected to the registerI A register can be any Chisel type that can be represented

as a collection of bits

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A Register with Reset

D Q

reset

d

0 q

clock

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A Register with Reset

Following code defines an 8-bit register, initialized with 0 atreset:

val reg = RegInit(0.U(8.W))

An input is connected to the register with the := updateoperator and the output of the register can be used just with thename in an expression:

reg := d

val q = reg

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Hello World in Chisel

class Hello extends Module {

val io = IO(new Bundle {

val led = Output(UInt(1.W))

})

val CNT_MAX = (50000000 / 2 - 1).U;

val cntReg = RegInit(0.U(32.W))

val blkReg = RegInit(0.U(1.W))

cntReg := cntReg + 1.U

when(cntReg === CNT_MAX) {

cntReg := 0.U

blkReg := ˜blkReg

}

io.led := blkReg

}

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Chisel is a Hardware Construction Language

I The code I showed you looks much like Java codeI But it is not a program in the usual senseI It represents a circuitI The “program” constructs the circuitI All statements are “executed” in parallelI Statement order has mostly no meaning

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Free Tools for Chisel and FPGA Design

I Java OpenJDK 8 already installed for Java courseI sbt, the Scala (and Java) build toolI IntelliJ (the free Community version)I GTKWaveI Vivado WebPACK already installed from DE1I Nice to have:

I make, git

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Tool Setup for Different OSs

I WindowsI Use the installers from the websites

I macOSI brew install sbtI For the rest, use the installer from the websitesI Use an Ubuntu VM to run Vivado

I Linux/UbuntuI sudo apt install openjdk-8-jdk git make gtkwaveI Install sbt, see https://github.com/schoeberl/chisel-lab/blob/master/Setup.md

I IntelliJ as from the websiteI If setup fails, we have you covered with the databar PCs

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Virtual Machine Setup for Chisel

I Ubuntu basedI Ubuntu VM with Quartus uid: patmos, pwd: patmosI Ubuntu VM with Vivado uid: de2lab, pwd: de2lab

I But this is VERY large (40 GB for the .zip file)I Use the VMWare Workstation Player (free for Linux and

Windows)

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An IDE for Chisel

I IntelliJI Scala pluginI For IntelliJ: File - New - Project from Existing Sources...,

open build.sbtI Show it (down to the Basys3)

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A Chisel Book

I Available in open access (as PDF)I Optimized for reading on a tablet (size, hyper links)

I Amazon can do the printout59 / 63

Further Information

I https://www.chisel-lang.org/

I https://github.com/freechipsproject/chisel-cheatsheet/

releases/latest/download/chisel_cheatsheet.pdf

I https://github.com/ucb-bar/chisel-tutorial

I https://github.com/ucb-bar/generator-bootcamp

I http://groups.google.com/group/chisel-users

I https://github.com/schoeberl/chisel-book

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Lab Time: Hello World in Chisel

I Get a blinking LED working on your FPGA boardI Clone or download the repository from:

I https://github.com/schoeberl/chisel-labI Follow the instructions from the lab page

I Start IntelliJ and follow the instructions from the lab pageI sbt runI Create a Vivado projectI Synthesize with the Play buttonI Configure the FPGA with the Programmer button

I You have your first Chisel design running in an FPGA!

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Change the Design

I Use IntelliJ, gedit, or the editor you like mostI Source is in .../src/main/scala/Hello.scalaI Change blinking frequencyI Rerun the exampleI Optional:

I Change to an asymmetric blinking, e.g., 200 ms on everysecond

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Summary

I The world is digitalI Processors do not get much faster – we need to design

custom hardwareI We need a modern language for hardware/systems design

for efficient/fast developmentI Chisel builds on the power of object-oriented and

functional Scala

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