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STANDARD I/O INTERFACES

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There are several designs for the bus of a computer.This makes I/O devices suitable for use in onecomputer to be unusable with other computers. Adifferent interface may have to be designed for everycombination of I/O device and computer, resulting in

many different interfaces. The most practical solutionis to develop standard interface signals and protocols.

STANDARD I/O INTERFACES

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The motherboard houses the ff.:Processor chip

Main memory

I/O interfaces

Connectors for additional interfaces

Motherboard

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Processor busExpansion bus

Bridge

BUSES ON THE MOTHERBOARD

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PCI (Peripheral Component Interconnect)

SCSI (Small Computer System Interface)

USB (Universal Serial Bus)

Bus STANDARDS

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ProcessorMain

Memory

Bridge

AdditionalMemory

SCSIcontroller

Ethernetinterface

USBcontroller

ISAinterface

Diskcontroller

CD-ROMcontroller

CD-ROM

Disk 1 Disk 2

Vide0

Keyboard Game

IDEdisk

Figure 4.38 An example of a computer system using different interface standards

Processor bus

PCI bus

SCSI bus

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Supports the functions found on a processor bus butin a standardized format that is independent of anyparticular processor. Device connected to the PCI busappear to the processor as if they were connecteddirectly to the processor bus.

PERIPHERAL COMPONENT INTERCONNECT

(PCI) BUS

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The PCI pioneered plug-and-play capability forconnecting I/O devices.

In today's computers, most memory transfers involvea burst of data rather than just one word. The PCI is

designed primarily to support this mode of operation.

PERIPHERAL COMPONENT INTERCONNECT

(PCI) BUS

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Supports three independent address spaces Memory address space

I/O address space

Configuration space

PERIPHERAL COMPONENT INTERCONNECT

(PCI) BUS

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Table 4.3 Data transfer signals on the PCI bus

Name Functions

CLK A 33-MHz or 66MHz clock

FRAME# Sent by the initiator to indicate the duration of a transaction

AD 32 address/data lines, which may be optionally increased to 64C/BE# 4 command/byte-enable lines (8 for 64-bit bus)

IRDY#, TRDY# Initiator-ready and Target-ready signals

DEVSEL# A response from the device indicating that is has recognized itsaddress and is ready for a data transfer transaction

IDSEL# Initialization Device Select

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A device that is the bus master has the right to initiate data

transfers by issuing read and write commands. A master is calledan initiator.

The addressed device that responds to read and writecommands is called a target.

A complete transfer operation on the bus, involving an addressand burst of data, is called a transaction.

Individual word transfers within a transaction are called phases.

PCI terminology

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Data TransferThe processor reads four 32-bit words from the memory

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

Figur 4.40 A r ad op ration on th PCI bus

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

1) Fra # - B ginning of transaction. C/BE# - r ad op ration, us s ory addr ss spac

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

2) AD: Addr ss is r ov d by th proc ssor. Proc ssor disconn cts its driv rs fro AD lin s.

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

2) Targ t nabl s its driv rs on th AD lin s, ass rts DEVSEL# and f tch s data.2) Initiator ass rts all four C/BE# lin s.

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

3) Both IRDY# AND TRDY# is ass rt d. Targ t s nds a word of data. Initiator loads it into itsinput buff r.

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

98

Figur 4.41 A r ad op ration showing th rol of IRDY#/TRDY#

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

98

5) Initiator is not r ady to r c iv data. Targ t aintains data on th AD lin s until IRDY#is ass rt d again.

Data Transf r

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1 2 3 4 5 6 7

CLK

Fra #

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

Adr ss #1 #2 #3 #4

C nd Byt nabl

98

7) Targ t is not r ady to s nd data.8) Targ t is now r ady to s nd data.

Data Transf r

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Device Configuration

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Configuration ROM memory contains: Various device options and characteristics

Parameters such as device interrupt priority