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CS623

CAD for VLSI

Lecture 31 : Static Timing Analysis

Shankar Balachandran

Dept. of Computer Science and Engineering

Indian Institute of Technology Madras

[email protected]


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2007

Timing Analysis

Identify the potential performance of a circuit

Many variations in timing

Rise time vs Fall time

Setup, Hold violations

Gate delays and interconnect delays

Exponential number of paths

Clock skew and jitter


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Dynamic Timing Analysis

Give test vectors at inputs

Observe the changes in all gates

Follow it through to the outputs

Find the worst case time

Not a simple problem :

Order of inputs matter

Simulation is tedious

Mixes logic and timing, which failed and why is difficult

to discern


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A Simplified Model

Assume rise and fall times are similar

Gate delays are characterized ahead of time

Many good models for predicting interconnect

delay

Assume clock skew = 0


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A Simple Problem?

Lets ignore interconnect delays for now

What do we need to do :

Perform timing analysis between all flops to flops

Find the worst case delay in each sequential stage

Assign clock accordingly

Design algorithms

Does not solve the inputs and the order of supply

though


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A Nave Algorithm

Enumerate all paths

Calculate delay on each path

Find the worst case delay

Problem?Exponential Number of Paths

Exponential algorithm

Why is this bad?

Timing analysis done many times during synthesis,

place and route


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Static Timing Analysis

Done without specifying vectors

A very powerful technique, widely used

A big turn in the EDA industry

Hitchcocks Algorithm

Exhaustive without specifying vectors

Linear in number of gates

Not edges, not paths


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2007

Basic Sketch

Find when outputs are required at the different

gates

Find out when they are actually arriving

If the signals arrive at every gate before they are

required in every single gate, we are done

Circuit is safe

Else

Pick better gates

Restructure the circuit


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Arrival Time

1 4 6 5

3 6 6 7

1 4 5 4

0 1 713 18

0 39 15 22

0 1 7 1418


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Required Time

1 4 6 5

3 6 6 7

1 4 5 4

22

4

0

8

5

3

9

9

9

15

13

15

15

18

22

22


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Which Nodes are Critical?

Any node where signals arrive just in time

Simply put

Required Time (i) = Arrival Time (i)

Not every node is critical

A path with all nodes that are critical is called the

critical path


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Which Are Critical?

1 4 6 5

3 6 6 7

1 4 5 4

0 1 713 18

0 3 9 1522

0 1 7 1418

22

4

0

8

5

3

9

9

9

13

15

15

18

22

22


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Definitions

Arrival Time

AT(i) = max [AT(j)] + delay (i) where j fanin(i)

Required Time

RT(i) = min [RT(j)) delay (j)] where j fanout(i)

Remember that delay (j) is subtracted here

Also, notice that min encompasses subtraction

Define Slack

Slack(i) = RT(i) AT(i)

Slack == 0 => Node is critical

A path whose nodes all have slack 0 = critical path


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Slacks

4 4 22 4

0 0 0 0 0

8 8 4 46

1 4 6 5

3 6 6 7

1 4 5 4


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Lets Change Required Time

1 4 6 5

3 6 6 7

1 4 5 4

2

-2

6

3

1

7

7

7

13

11

13

13

16

20

20

Arrive in

the past?

0 1 713 18

0 3 9 15

0 17

1418

22

20


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Lets Redo Slacks

2 2 00 2

-2 -2 -2 -2 -2

6 6 2 24

1 4 6 5

3 6 6 7

1 4 5 4

Critical Edges

Failing Path


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Specifying Required Time

Run as fast as you can

First case

Pick the max(AT) as RT(outputs)

Can the circuit run as fast as T

Second case

Fix RT(outputs) = T

Calculate Arrival Times as before

Calculate slacks as before

Check if there are paths that are violating timing


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Observations on Slacks

For a circuit to run safely

All slacksWhen slacks are less than 0

Relax the constraints

Pick gates with lesser delaysThe model ignores interconnect delay

Easily extendable for interconnect delay

More discussion later

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