SS7 Technicals

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Technical White Paper for

clock over Ethernet

Huawei Technologies Co., Ltd.


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Technical White Paper for Clock over Ethernet

Copyright 2007 Huawei Technologies Co., Ltd. All Rights Reserved i

Table of Contents

1 Forewords ...............................................................................................................................1

1.1 Background of clock...................................................................................................... 1

1.1.1 The basic concept of synchronization........................................................................ 1

1.1.2 The traditional service of voice over E1 link.............................................................. 2

1.1.3 Wireless application...................................................................................................... 2

1.1.4 The requirement for BITS ............................................................................................ 3

1.2 Introduction of the clock recovery over Ethernet ........................................................... 3

2 Clock recovery over the Ethernet.............................................................................................. 3

2.1 Self-adaptive clock recovery ......................................................................................... 3

2.1.1 Principal description...................................................................................................... 3

2.1.2 Test result....................................................................................................................... 5

2.2 Synchronous Ethernet................................................................................................... 6

2.2.1

Principal description...................................................................................................... 6

2.2.2 Test result....................................................................................................................... 7

2.3 Summary....................................................................................................................... 8

3 Typical Applications.................................................................................................................. 9

3.1 Scenario of ACR ...........................................................................................................9

3.2 Scenario of synchronous Ethernet ................................................................................ 9

4 Closing Remarks ...................................................................................................................... 9

Appendix A References ................................................................................................................ 10

Appendix B Abbreviations............................................................................................................. 11

http://datacomm.huawei.com


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Copyright 2007 Huawei Technologies Co., Ltd. All Rights Reserved 1

Technical White Paper for clock over Ethernet

Abstract: Although the trend for telecom is to build an all-IP network, there are still many difficult for

the carrier to migrate their traditional service, such as ATM or TDM, to the next generation of

IP based network. The key issue, maybe the most challenge one, is how to deliver the clock

over a packet based network. This paper provides information about the synchronization

over the Ethernet by Huawei CX series production.

Key words:PSN, TDM, ATM, PWE3, Synchronous Ethernet, ACR

1 Forewords

Since the Ethernet was never originally conceived as a real-time transport medium for voice

and video services, new rules are evolving to ensure that applications which rely critically on

the relative time and timing of data arrival can now be transported without degradation to

quality. The big challenge is to provide a precise timing signal to synchronies the bit rate for

the enabling of traditional time division multiplex (TDM) services over Ethernet.

This paper provides information about how to deliver the clock over the Ethernet by Huawei

CX series production.

1.1 Background of clock

1.1.1 The basic concept of synchronization

Synchronization refers that signal is locking strictly to a reference clock source in frequency or

phase and the valid moment occurs at the same rate. Phase synchronization means that the

time of the two watches is the same, for example, one is 19:00, and another is 19:00.

Frequency synchronization does not need the time is the same, but the rate of the time is the

same. For example, at the first time, watch A is 19:00 and watch B is 20:00; that is ok.

Sometimes later, on the point that the watch A is 20:00, the watch B should be 21:00 exactly.



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All devices in the communication network should be running at the same rate otherwise slip

might occur. A slip is a disruption in data flow caused by an overflow or an underflow of a buffer

in the communication system due to variations in the writing and reading rates.

There are many types of service in the communication system and the requirements for the

different service are different also.

1.1.2 The traditional service of voice over E1 link

Traditionally, the TDM service is carried by SDH/PDH network. If the clock is not the same,

whatever how small it is, the difference will be accumulated and eventually cause a slip. The

equipment that used for this scenario should meet the requirement of Traffic interface defined

in ITUT G.823.

1.1.3 Wireless application

A more stringent requirement of synchronization is for the wireless application where the base

station located in different areas must keep the same radio frequency. If the frequency

difference is larger than 50ppb (50 E-9), call dropping will occur during the Inter-cell Handover.

Today there are so many wireless standards that the timing requirements are also different.

Wireless standards Frequency accuracy Phase accuracy

GSM 50ppb NA

WCDMA 50ppb NA

TD-SCDMA 50ppb 3s



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Wireless standards Frequency accuracy Phase accuracy

CDMA2000 50ppb 3s

WiMax FDD 50ppb NA

WiMax TDD 50ppb 1us

LTE 50ppb TBD

Currently, precise phase synchronization for CDMA can be achieved by GPS only and there is

no extra synchronization requirement to the transformation network. Due to the high cost, it is

not recommended for GSM/WCDMA to keep synchronization by GPS. Instead,

synchronization is usually achieved by line (PDH/SDH) today and in the future synchronization

over the Ethernet is expected.

For the wireless application, criterion for the traffic interface defined in G.823 together with the

clock accuracy of 50ppb is the key requirement. A criterion dedicated for wireless may be

added in the final version of in G.8261.

1.1.4 The requirement for BITS

There exists a dedicated network for delivering clock to BITS equipment. For this application,

the criterion of timing interface defined in G.823 should be compliant.

1.2 Introduction of the clock recovery over Ethernet

Currently, Huawei CX series recommends two mechanisms to deliver the clock across the

PSN. The first is ACR (Adaptive clock recovery), the second is synchronous Ethernet. Both of

them can meet the requirement of the frequency accuracy of 50ppb.

2 Clock recovery over the Ethernet

2.1 Self-adaptive clock recovery

2.1.1 Principal description

Self-adaptive clock recovery is a mechanism for deriving a synchronous clock from an

asynchronous packet stream.



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As shown above, two IWFs (Inter-Working Function) are located between master clock and the

slave clock. TDM steam is encapsulated into packets by IWF and transferred across a PSN

network to the IWF on the other side. The packets will be first stored in a queue, hereafter

referred to as jitter buffer, and then de-encapsulated into TDM steam.

The key point is that if the recovered clock is not equal to the master clock, the depth of the

jitter buffer must change. So the clock rate can be recovered by adjusting the output clock

according to the depth of the jitter buffer. If the depth of the queue is above the high watermark,

we will know that the output frequency is slower than the master clock and should be tune up; if

the depth of the queue is below the low watermark, we will know that the output frequency is

faster than the master clock and should be tune down. These adjustments are something like

the conventional PLL arrangements and the output frequency will be the same as the master

clock in a long-tem view.

A

As the figure shown left, water comes from a tag and is stored in the bucket

and then leaked out from another tag. We can then adjust the second tag

according to the water level of the bucket. If the water level is below the low

water mark, we can tune the tag to let less water leak out; if the water level is

above the high water mark, we can tune the tag to let more water leak out.

Finally, we will find that the average rate that the water leak out of the bucket

is the same as the rate that water come from the first tag.

In fact, it is not necessary to use the actual data packet arrival rate, since it could be equally

well performed on out of band packets transmitted with timing information related to the same



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master clock. This means that the first IWF could transmit dedicated clock packets to the

remote end only. The packets contain a timestamp (TS1) that records the exactly time when

the packet left the first IWF. The remote IWF measures the exactly time when the packets

arrive and records it as TS2. Then the time difference (TD) between the two IWFs can bederived from the equation TD = TS2-TS1.

The point is that if the recovered clock is not equal to the master clock, the time difference

between the two IWFs must change. If the time difference is continually increasing, the output

frequency should be tune up; if the time difference is continually decreasing, the output

frequency should be tune down.

2.1.2 Test result

A joint test is conduct by Huawei CX together with Huawei GSM to demonstrate the clock

accuracy across the Ethernet. As shown above, up to 10 LAN switches are concatenated

together via FE link to simulate a real metro Ethernet network. BTS 3002C is connected to

CX300-A via E1 interface and BSC32 is connected to CX300-B via E1 interface. A rubidium

clock is connected to BSC32 to provide a high accuracy source clock. BSC32 lock to the

rubidium clock and then send it to CX300-B by E1 link. CX300-B packetizes the TDM traffic

and sends the TDM packet to CX300-A across the Ethernet network. The CX300-A

de-packetize the TDM packets to the original TDM traffic and at the same time, recover the

clock from the packets. The BTS lock the clock from the E1 link from CX300-A. The recovered

clock is monitored by a frequency meter. The frequency meter shares the same rubidium clock

source. The recovered clock is recorded by the frequency meter every 10s.

If there is no background traffic, the result over 12 hours shows below:



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We can also assert heavy background traffic to simulate the congestion of the Ethernet

network to see how the recovered clock changed. The result show below:

Under the condition that 95% background traffic with 64-9600 random packet length, the

recovered clock degrades but still meet the frequency accuracy of 50ppb.

2.2 Synchronous Ethernet

2.2.1 Principal description

As we know, native Ethernet can not deliver clock, but why? The requirement for the clock

accuracy of Ethernet is 100ppm, but it does not mean that Ethernet can not provide a better

clock. It just means that Ethernet can work well in the condition of 100ppm.

In fact, Ethernet PHYs have the ability of clock recovery that can meet the requirement of

50ppb. It is done by hardware and the technique is the same with SDH. As the figure above,

the Ethernet PHY on the right can inject the high accuracy clock from BITS into Ethernetstream and then the PHY on the left can recover the both the data and the clock from the



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Ethernet series traffic. The Ethernet traffic is encoded with 8B/10B coding with the benefit

that there will never be successive 1 or 0. It is a more reliable coding than SONET/SDH

where a scrambling mechanism is used and principally can not avoid successive 1 or 0.

The only problem for native Ethernet is that there is no mechanism to associate the inputclock to the output clock, in another word, that the better clock recovered from an interface

can not shared by the other interfaces.

As shown in above, the synchronous Ethernet can be regards as a native Ethernet together

with a clock system. The clock system can be the same with the SDH/SONET equipment.

The clocks recovered by the PHYs on each line card will be sent to the clock system, the

clock system will choose the best clock, de-jitter, and then send it as the reference clock to

all the line cards. In this way, the clock with accuracy of 50ppb can be recovered from one

interface and then delivered to all the other interface and then to all the equipments connect

to the interfaces. All the equipments of the network will work with a common system clock.This is the main principle of synchronous Ethernet.

2.2.2 Test result

The test environment is mostly the same as that for ACR. The only difference is that the

native FE link is replaced by a synchronous fast-Ethernet link. The result is shown below and

the frequency accuracy is less than 2 ppb and is much better than ACR.



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2.3 Summary

There are two mechanisms for clock recovery from Ethernet that Huawei CX supports.

The advantage of ACR is that the function is performed in the both edge of the Ethernet

network and there is no extra requirement for the switches and routers which are already

deployed. The disadvantage of ACR is the frequency accuracy may degrade during the

traffic congestion.

The synchronous Ethernet has a reliable hardware-based clock recovery mechanism and

the frequency accuracy is much better than ACR. Unfortunately, it will be a big problem to

deploy it because all the switches or routers in the network must be upgrade to support

synchronous Ethernet function.

Both the ACR and Synchronous Ethernet are defined in G.8261.

Scenario standards Key criterion Mechanism

TDM tandem G.823 Criterion for Traffic interfaceACR or Synchronous

Ethernet

Wireless

applicationG.8261

Criterion for Traffic interface

together with a 50 ppb

frequency accurary

ACR or Synchronous

Ethernet

BITS G.823 Criterion for timing interface Synchronous Ethernet



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3 Typical Applications

3.1 Scenario of ACR

As the figure shown above, the RNC and the NodeB are connect with a metro network via

Ethernet interface. At the same time, clock from RNC can be recovered by the CX on the

other side and send it to NodeB.

3.2 Scenario of synchronous Ethernet

Also in wireless application, the CX on the RNC side can receive clock from BITS equipment

and inject it into the Ethernet link. The other CX can recover the clock from the synchronous

Ethernet link and send it to the CX on downstream. The CX on the base station side can

receive the clock from the synchronous Ethernet link and send it to base station via E1 link.

4 Closing Remarks

Although the trend for telecom is to build an all-IP network, there are still many difficult for the

carrier to migrate their traditional service, such as ATM or TDM, to the next generation of IP

based network. The key issue, maybe the most challenge one, is how to deliver the clock

over a packet based network. Currently Huawei CX has two mechanism of clock recovery,

one is ACR, and another is synchronous. Both of them have their unique value and can not

be replaced by the other.



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In the scenario where the frequency accuracy is more concerned about, the synchronous

Ethernet is only choice. On the other hand, ACR is recommended.

Appendix A References

1) ITUT G.823 TRANSMISSION SYSTEMS AND MEDIA, DIGITAL SYSTEMS

AND NETWORKS

2) ITUT G.8261

3) Digital networks Quality and availability targets

4) RFC 3916, Requirements for Pseudo-Wire Emulation Edge-to-Edge

(PWE3),IETF

5) RFC 3985, Pseudo Wire Emulation Edge-to-Edge (PWE3) Architecture,IETF

6) RFC 4197, Requirements for Edge-to-Edge Emulation of Time Division

Multiplexed(TDM) Circuits over Packet Switching Networks,IETF

7) RFC 4553, Structure-Agnostic Time Division Multiplexing (TDM) over Packet

(SAToP), IETF

8) Internet Draft, draft-ietf-pwe3-cesopsn-07, IETF

9) MEF8.0 , Metro Ethernet Forum

10) MFA 8.0.0, Emulation of TDM Circuits over MPLS Using Raw Encapsulation

Implementation Agreement, MFA



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Technical White Paper for clock over Ethernet



Appendix B Abbreviations

Abbreviation Full name

ACR Adaptive Clock Recovery

PSN Packet Switched Networks

TDM Time Division Multiplex

PDH Plesiochronous Digital Hierarchy

SDH Synchronous Digital Hierarchy

SONET Synchronous Optical NETwork

IETF Internet Engineering Task Force

PSTN Public Switched Telephone Network

SAToP Structure-Agnostic TDM over PacketCESoPSN Circuit Emulation Services over Packet Switch Network

CAS Channel Associated Signaling

CCS Common Channel Signaling

MEF Metro Ethernet Forum

MFA

MPLS Forum

Frame Relay Forum

The ATM Forum

ITU-TInternational Telecommunication Union - Telecommunication

Standardization Sector

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