SRAM Leakage Suppression by SRAM Leakage Suppression by

Minimizing Standby Supply Voltage Minimizing Standby Supply Voltage

Huifang Qin, Yu (Kevin) Cao, Dejan Markovic, Huifang Qin, Yu (Kevin) Cao, Dejan Markovic,

Andrei Vladimirescu, and Jan RabaeyAndrei Vladimirescu, and Jan Rabaey

Berkeley Wireless Research Center,

University of California, Berkeley

- 2 -ISQED 2004 H. Qin

Outline

Motivations– SRAM leakage suppression for ultra-low power applications– Exploring Ultra-Low Voltage (ULV) SRAM operation capability

Modeling– The SRAM Data Retention Voltage (DRV)

Design and Implementation– Dual-rail leakage suppression scheme with ultra-low standby Vdd

Measurement Results and Analysis– To Minimize the SRAM DRV

Conclusion and Future Work

- 3 -ISQED 2004 H. Qin

Target application:Ultra-Low Power (ULP) wireless sensor network

Motivation I: Leakage Suppression of Embedded SRAM

Nowadays the embedded SRAM circuits in a microprocessor system typically consumes:– 90% of the total processor transistor count– 60% of the chip area– 20% ~ 50% of chip power

Power-efficient design is critical for portable electronics – To extend battery life requires maximum power savings. Even more

demanding is to enable energy scavenging

– 100% of ULP system leakage power?

- 4 -ISQED 2004 H. Qin

Motivation I: Leakage Suppression of Embedded SRAM

Leakage of 1K byte SRAM Module

Leakage (A)0.13um Technology

0.18um Technology

Vdd (V)

The situation is further exaggerated by scaling– 7.5X leakage increase for each technology generation

– The ever-increasing process variations make things even worse.

Embedded memory leakage suppression is both crucial and effective for deep sub-micron ultra low power, low duty cycle system design.

- 5 -ISQED 2004 H. Qin

Motivation II: Exploring Low Voltage SRAM Operation

(Figure courtesy of Intel)

• Technology driven

• Effectively reduces design power consumption

Vdd scaling: most effective approach in achieving ultra-low power design. Question: What is

the SRAM capability for ULV operation?

- 6 -ISQED 2004 H. Qin

(1V)

(?)

The Simple Scheme: SRAM in Ultra-Low Vdd Standby

Goal of the Scheme

• Minimize standby leakage power • Robust preservation of memory content

More to find out

– What is the Data Retention Voltage (DRV) of SRAM?– How to model DRV from process parameters?– Any effective way to do DRV-optimized design?

- 7 -ISQED 2004 H. Qin

Look Around: Existing Approaches for Low Leakage SRAM

Circuit level: – Dynamic control of Gate-Source and Substrate-Source Vbias

• Large design and area overhead• Limited saving on leakage power

Micro-architectural level: – Vdd gating off for idle memory sections

• Ineffective for caches with large utilization ratio

– Drowsy cache: put inactive cache lines in a low voltage standby mode

• Achieves over 70% leakage energy saving in a data cache• Question to be answered: how deep a snap can it be?

- 8 -ISQED 2004 H. Qin

Look Around: What is Unique in This Work

A thorough study of ULV SRAM data retention behavior

An effective leakage suppression standby scheme for ULP applications– The whole SRAM is put in standby mode– Maximum leakage saving and minimum design

overhead

- 9 -ISQED 2004 H. Qin

The Data-Retention Voltage (DRV) of SRAM

DRVV when , DD

inverterRight 2

1

inverterLeft 2

1

V

V

V

V

VDD

V1

M4

M3

M6M5

M2

M1

Leakagecurrent

V2

Leakagecurrent

VDDVDD

0 0

0 0.1 0.2 0.3 0.40

0.1

0.2

0.3

0.4

V1 (V)

V2 (

V)

VTC1

VTC2

VDD

=0.18V

VDD

=0.4V

VTC of SRAM cell inverters

V2

(V)

When Vdd scales down to DRV, the Voltage Transfer Curves (VTC) of the internal inverters degrade to such a level that Static Noise Margin (SNM) of the SRAM cell reduces to zero.

DRV Condition:

- 10 -ISQED 2004 H. Qin

Modeling SRAM DRV

• Coefficients extracted from transistor characterizations, such as Vthi, ni, I0i.

• Model can be used for DRV-aware SRAM design optimizations

Modeled and simulated DRV as a function of transistor width scaling.

0i

i i thii ii

SDRV DRV a b V c T

S

DRV analytical model:

where DRV0 is the nominal value at 27ºC

- 11 -ISQED 2004 H. Qin

Design of Dual-Rail SRAM Standby Scheme

VDD

4k BytesSRAM

Stby

5:1

SCConv VDDstandby

Standby Vdd noise margin: – 100mV Guard band over DRV

gives 55mV W.C. SNM

Delay overhead– A 200μm wide PMOS power

switch wakes up the memory in within 10ns

Wake up power overhead: – Minimum standby time for positive

power saving estimated to be around tens of μs.

Designed for ULP system:

- 12 -ISQED 2004 H. Qin

Switch Capacitor (SC) Converter Design

C

C

C

C

C Rmem

1V

C Rmem

CCCC

Clk

Equalizing phase Charging phase

Clk

Clk

Clk

Clk

(b) Operation phases

(a) SC Conv design

0.66

Rmem

0.66 0.50 0.50 0.50

0.240.24 0.35 0.350.24 0.350.24 0.35

10 pF 10 pF10 pF 10 pF 10 pF

(numbers indicate transistor w idth in microns)

Compared to magnetic-based voltage regulators

– Higher efficiency– Smaller current ripple– Easier on-chip integration

Optimized SC converter design achieves 85% power efficiency with 1V input and estimated output load

- 13 -ISQED 2004 H. Qin

4KB SRAM Leakage Control Scheme Test Chip

Standby supply voltage regulator designTest chip in 0.13um technology

1.4 mm

1.4 mm

IP Module of 4kB SRAM

- 14 -ISQED 2004 H. Qin

SRAM DRV Measurement

Waveform of DRV measurement

(a) DRV = 190mV in SRAM cell 1 with state “1” (b) DRV = 180mV in SRAM cell 2 with state “0”

SRAM supply

End of standby

t1

Data output

(a) (b)

t1 t2t2State “1”restored

End of standby

State “0”restored

SRAM supply

End of standby

t1

Data output

(a) (b)

t1 t2t2State “1”restored

End of standby

State “0”restored

SRAM DRV test suite

- 15 -ISQED 2004 H. Qin

• Measured DRV: 80mV ~ 250mV

(0.13 m CMOS, 300mV Vth)

SRAM Measurement Results

0 0.2 0.4 0.6 0.8 10

10

20

30

40

50

60

Supply Voltage (V)

Leakage Current (μA)

MeasuredDRV range

• More than 90% reduction in leakage power with 350mV standby Vdd (100mV guard band).

Storage requirement sets Vdd lower limit at 250mV without error tolerant design

50 150 250 350 450 0

2000

4000

6000

DRV (mV)

His

togr

am o

f 32K

SR

AM

cel

ls

- 16 -ISQED 2004 H. Qin

Analysis: What affects SRAM DRV

Process variation (ΔL, ΔVth)

Chip temperature

SRAM cell sizing

- 17 -ISQED 2004 H. Qin

Resize SRAM Cell: for Optimum DRV

DRV vs. Transistor size Tuning

VDD

V1

M4

M3

M6M5

M2

M1

Leakagecurrent

V2

Leakagecurrent

VDDVDD

0 0

Current sizing – Performance optimized– Provides poor DRV

To optimize for DRV– Change P/N ratio– Smaller NMOS– Larger PMOS

- 18 -ISQED 2004 H. Qin

DRV-Aware SRAM Cell Sizing Optimization (NMOS)

By sizing NMOS (W/L) smaller, DRV mean value can be reduced by 20~30mV.

Area vs. Performance: already best traded off

Leakage power vs. Performance: best at 20% higher delay.

(30% delay increase = 50% leakage power reduction)

- 19 -ISQED 2004 H. Qin

Conclusions and Current Work

SRAM DRV modeled and silicon-verified– DRV from 80mV to 250mV for 0.13μm technology, 300mV Vth.– DRV model facilitates optimization for ULP SRAM design

Dual-rail standby scheme saves over 90% P leakage

– Effective and low-cost approach for ULP applications

DRV can be minimized by:– Effective control on process variations (***)– Avoid high temperature operation (*)– SRAM cell sizing optimization at tradeoffs with speed and area (**)

Can we further bring down the SRAM Vdd?– A fix at the architecture level may be more effective – use error

correction schemes to tolerate ULV errors