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8/15/2019 Spring 2010 Final CS302Printed
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FINALTERM EXAMINATIONSpring 2010
CS302- Digital Logic Deign !Seion - "#Ti$e% &0 $in
Mar'% ()
For Teac*er+ ,e Onl
QNo.
1 2 3 4 5 6 7 8 Total
Marks
Q No. 9 10 11 12 13 14 15 16
Marks
Q No. 17 18 19 20 21 22 23 24
Marks
Q No. 25 26 27 28 29 30 31 32
Marks
Q No. 33 34 35 36
Marks
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./etion No% 1 ! Mar'% 1 # - leae c*ooe one The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point formatfor binar n!mbers"
# $-bit # %&-bit 32-it # &4-bit ./etion No% 2 ! Mar'% 1 # - leae c*ooe one The decimal '%7( in )*+ ,ill be reresented as _________
# %%%.% # %%.%% 10111
# %%%%. ./etion No% 3 ! Mar'% 1 # - leae c*ooe one The basic b!ilding bloc for a logical circ!it is _______
# A Fli-Flo A Logical ate # An Adder # None of gi0en otions ./etion No% " ! Mar'% 1 # - leae c*ooe one
The o!t!t of the e1ression F2A")"* ,ill be 3ogic ________ ,hen A2% )2.*2%"
# ndefined # 6ne 4ero # No 6!t!t as in!t is in0alid" ./etion No% ( ! Mar'% 1 # - leae c*ooe one ________ is in0alid n!mber of cells in a single gro! formed b the adacent cells in 8-
ma
# 9 # $ 12 # %&
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./etion No% 5 ! Mar'% 1 # - leae c*ooe one The P:6; consists of a fi1ed non-rogrammable ____________
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# &&&& 1101
# '&''# ''''
./etion No% 12 ! Mar'% 1 # - leae c*ooe one In a state diagram the transition from a c!rrent state to the ne1t state is determined b
C/rrent tate an9 t*e inp/t # *!rrent state and o!t!ts # Pre0io!s state and in!ts # Pre0io!s state and o!t!ts ./etion No% 13 ! Mar'% 1 # - leae c*ooe one
________ is !sed to minimi@e the ossible no" of states of a circ!it"
State aign$ent # State red!ction
# Ne1t state table # State diagram ./etion No% 1" ! Mar'% 1 # - leae c*ooe one ________ is !sed to simlif the circ!it that determines the ne1t state"
State 9iagra$ # Ne1t state table # State red!ction
# State assignment
./etion No% 1( ! Mar'% 1 # - leae c*ooe one he %est state assi/nment ten"s to ___________. # ;a1imi@es the n!mber of state 0ariables that dont change in a gro! of relatedstates
Mini$i:e t*e n/$er o; tate
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1 # & # 0 #
./etion No% 16 ! Mar'% 1 # - leae c*ooe one 0 1-%it serial in # parallel out shift re/ister contains the 2alue +1, _____ cloc3 si/nal(s)$ill %e re4uire" to shift the 2alue completely out of the re/ister.
# ' # 5
# 6 8
./etion No% 1) ! Mar'% 1 # - leae c*ooe one 5-bit Cohnson co!nter seB!ences thro!gh ____ states
# 7 # %. # D9
2(
./etion No% 1& ! Mar'% 1 # - leae c*ooe one
A/$e t*at a "-it erial in@erial o/t *i;t regiter i initiall clear? e 8i* to tore t*enile 1100? *at 8ill e t*e "-it pattern a;ter t*e econ9 cloc' p/leB !Rig*t-$ot it;irt?#
# ''&& # &&''
0000# ''''
./etion No% 20 ! Mar'% 1 # - leae c*ooe one T! a""r!ss #ro$ %i& t! "ata is r!a"' is pro(i"!" )* +++++++
# D!p!n"s on &ir&uitr*
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# Non! o# ,i(!n options # M # Mi&ropro&!ssor ./etion No% 21 ! Mar'% 1 # - leae c*ooe one
FIF6 is an acronm for __________
Firt In7 Firt O/t
# Fl in Fl 6!t # Fast in Fast 6!t # None of gi0en otions ./etion No% 22 ! Mar'% 1 # - leae c*ooe one 3T is acronm for _________
Loo' ,p Tale # 3ocal ser Terminal # 3east er Time Period # None of gi0en otions
./etion No% 23 ! Mar'% 1 # - leae c*ooe one The 0oltage gain of the In0erting Amlifier is gi0en b the relation ________
o/t @ in - R; @ Ri# o!t / :f 2 - in / :i
# :f / in 2 - :i / o!t # :f / in 2 :i / o!t ./etion No% 2" ! Mar'% 1 # - leae c*ooe one ______ of a +/A con0erter is determined b comaring the act!al o!t!t of a +/Acon0erter ,ith the e1ected o!t!t"
# :esol!tion Acc/rac # !anti@ation
# ;issing *ode ./etion No% 2( ! Mar'% 1 # - leae c*ooe one
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0%o2e is the circuit "ia/ram of _______.
# 0synchronous up-counter # 0synchronous "o$n-counter
/*n&ronous up-&ount!r # !ynchronous "o$n-counter
./etion No% 25 ! Mar'% 1 # - leae c*ooe one The seB!ence of states that are imlemented b a n-bit Cohnson co!nter is
# nG9 >n l!s 9? 2n !n $/ltiplie9 2# # 9n >9 raise to o,er n? # n9 >n raise to o,er 9? ./etion No% 26 ! Mar'% 2 #
Dra8 t*e Tr/t*-Tale o; NOR ae9 S-R Latc*
inp/t o/tp/t
S R .T 10 0 .T0 1 0
1 0 1
1 1 INALID
./etion No% 2) ! Mar'% 2 #
T%o stat! assi,n$!nts ar! ,i(!n in t! ta)l! )!lo%. "!nti#* %i& stat! assi,n$!ntis )!st an" %*
/tat!s /tat! assi,n$!nt 1 /tat! assi,n$!nt 2
00 00
01 01
11 10
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D 10 11
ns
!tate assi/nment 5 is %est assi/nment7 it 8inimi9es the num%er of state 2aria%les that "on:t
chan/e in a /roup of relate" states.
./etion No% 2& ! Mar'% 2 #
rite 9o8n at leat t8o ;/nction o; a regiter?
An%
%" Re/isters are operatin/ as a coherent unit to hol" an" /enerate "ata.9" re/isters functions also inclu"e confi/uration an" start-up of certain features
especially "urin/ initiali9ation %uffer storage e./. 2i"eo memory for /raphicscar"s input#output (I#;) of "ifferent 3in"s
./etion No% 30 ! Mar'% 2 #De;ine /anti:ation proce?
An%The rocess b ,hich ,e can con0ert an analog!e signal into digital signal >code? is no,n asB!anti@ation rocess"
./etion No% 31 ! Mar'% 3 #
o% &an %! &al&ulat! t! #r!u!n&* o# an unkno%n si,nal
ns
he fre4uency of a particular e2ent is accomplishe" %y countin/ the num%er of times thate2ent occurs $ithin a specific time inter2al then "i2i"in/ the count %y the len/th of thetime inter2al.
./etion No% 32 ! Mar'% 3 #i
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./etion No% 33 ! Mar'% 3 #EJplain 9na$ic RAM in o/r o8n 8or9?
An%+ram !se latch to store a single bit of information"the main dra,bac of it id the dischargeof caacitor o0er a eriod of time"here fo!r gates are !sed in maing a singlelatch" Interms of transistors 4 to & transistors are reB!ired to imlement a single storage cell" Inorder to b!ild memories ,ith higher densities a single transistor is !sed to store a binar0al!e" A single transistor can not store a binar 0al!e ho,e0er it is !sed to charge anddischarge a caacitor" The caacitor can not retain the charge therefore it has to beeriodicall chargedthro!gh a refresh ccle"
./etion No% 3" ! Mar'% ( #
ou ar! ,i(!n t! N!t-stat! ta)l! o# a $oor $a&in!' usin, tis in#or$ation "ra%t! stat! "ia,ra$ o# t! $a&in!.
Present State Ne1t State
9 % . 9 % .. % % % % %
% % % . . %
. . % . % .
. % . % . .
% . . % % .
% % . . % %
./etion No% 3( ! Mar'% ( #EJplain Me$or Select or Enale Signal
Me$or Select or Enale Signal% There are more than one memor chis to store rogram
Information in dail !se com!ters" read or ,rite oeration is carried o!t on a singleaddressable location instantaneo!sl "
The !niB!e location is accessed in one of the se0eral memor chis so single memorchis is selected before a read or ,rite oeration can be carried o!t" All memor chisha0e a chi enable or chi select signal ,hich has to be acti0ated before the memor canbe accessed"
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./etion No% 35 ! Mar'% ( #
er;or$ance c*aracteritic o; D@A con