SPICE Modeling of Power Devices - MOS-AK

Copyright © 2019 Silvaco Inc.

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FROM ATOMS TO SYSTEMS

SPICE Modeling of Power Devices

Bogdan Tudor

December 2019

Copyright © 2019 Silvaco Inc. Copyright © 2019 Silvaco Inc.

Agenda

• Power MOSFET capacitances

• Capacitance modeling of symmetric GaN HEMT

• Asymmetric GaN HEMT example

• Advantages of TCAD-based SPICE modeling

• Other TCAD-based SPICE modeling examples: VDMOS, IGBT

• Power MOSFET macromodeling in Utmost IV and SmartSpice

• Conclusion


MOSFET Capacitance Modeling

• 4-terminal MOSFET gate capacitance characterization

• Symmetric devices: Cgs and Cgd are often characterized together as Cgc = Cgs + Cgd.

• Cgc: the LCR “low” terminal connects to both s and d.

• Cgg = Cgs + Cgd + Cgb: LCR “low” terminal connected to s, d and b.

• Capacitances are measured with Vgs swept from negative to positive, at Vds = 0.


Specific Power MOSFET Capacitances

• 3-terminal MOSFET• The b and s nodes are always connected together

• Main bias sweep is Vds

• Typical capacitances to measure:• Crss = Cgd

• Coss = Cgd + Cds

• Ciss = Cgs + Cgd


Symmetric GaN HEMT Device

• Symmetric GaN HEMT structure study, presented at MOS-AK 2018

• 3 device structures: L = 1mm, 2mm and 3mm, respectively


Symmetric GaN HEMT Capacitances

• MVSG HEMT model: Coss and Crss vs. Vds


Asymmetric GaN HEMT Device Structure

• TCAD device structure calibrated based on published data

• P-type doped GaN gate resulting in Vth > 0 (“normally-off” device)


Asymmetric GaN Device Structure: Challenges

• “Floating” GaN Buffer: SOI-like structure.

• Need to consider the gate current.

• Existing compact models are not based on this structure: may have to deal with unexpected device effects.


Unusual Subthreshold Region Behavior

• Unusual behavior observed in the subthreshold region of Id(Vgs).


Unusual Subthreshold Region Behavior

• The effect is due to carrier accumulation inside the GaNbuffer layer.

• A current path is formed through the GaN buffer’s inner region.

• This is different from the channel current of the main device.

• This appears to be a parasitic FET, in parallel with the main device, having a much lower effective mobility.


Confirmation and SPICE Modeling

• The “parasitic FET” device is confirmed from the Id(Vds) characteristics at Vgs < 0.5V.

• The effect can be modeled by adding a GaN FET device in parallel with the main one, in the Utmost IV Netlist.


Two FET SPICE Model Validation

• After extracting the linear region Id(Vgs) parameters, the modified netlist is confirmed.

Single FET netlist Netlist with added parasitic FET


Unusual Behavior of the Cgs and CgdCapacitances

• The issue appears for Vgs > 1.6V.• Similar to the HVMOS LDD-related Cgs and Cgd behavior.

• May be modeled by an extra resistor in series with the drain of the two FET devices.


Validation of the SPICE Macromodel

Netlist without the extra drain resistor Netlist with added drain resistor


Gate Current Effect on gm

Gate current disabled Gate current enabled


Asymmetric GaN HEMT: Macromodel Results

• Id(Vgs), gm(Vgs) and Ig(Vgs), at various Vds from 0.1V to 20V.

• Id(Vds) at Vgs < 0.5V (parasitic FET).

• Cgs(Vgs), Cgd(Vgs)

• Id(Vgs) at various temperatures

• Id(Vds) at Vgs >= 1V (self-heating)


• TCAD simulations allows a separation of physical effects, not easy to achieve in real life (e.g., disabling self-heating).

TCAD-based SPICE Modeling:Unique Advantages


TCAD-based SPICE Modeling:Unique Advantages (cont.)

• Model development: identifying specific device effects or parasitics and adding them to a SPICE macromodel, as extra circuit elements.

• Essential feature of Power MOSFET SPICE (macro)modeling.


VDMOS Example: TCAD Structure


VDMOS SPICE Modeling

• HiSIM_HV2 SPICE model using TCAD data


IGBT SPICE Modeling

• HiSIM-IGBT SPICE model using TCAD data


Power MOSFET Macromodel Example

• Power MOSFET typical macromodel, netlist definition and model cards in Utmost IV


Power MOSFET MacromodelI-V and C-V Parameter Extraction

• Global I-V and C-V parameter optimization using Utmost IV


Dynamic Characterization

• Gate charge test circuit and waveforms [1, 2]

• Reverse recovery time of the body diode [1]


Gate Charge Parameters Tuning

• Using SmartSpice Rubberband with transient analysis

• Gate charge parameters

• Miller Plateau parameter tuning


Reverse Recovery Parameter Tuning

• Reverse recovery time and charge (trr, Qrr) parameters


Conclusion

• Symmetric GaN HEMT capacitance modeling

• Macromodel for Asymmetric GaN HEMT developed in Utmost IV using TCAD information

• TCAD-based SPICE modeling carries unique advantages

• Power Device modeling examples based on the HiSIM SPICE model family: VDMOS, IGBT

• Combining the capabilities of TCAD, Utmost IV and SmartSpice enables a complete modeling methodology of Power devices, including dynamic characterization

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References

1. *** “Power MOSFET Electrical Characteristics”, Toshiba Corporation, November 2016.

2. *** “Power MOSFET Basics”, Alpha & Omega Semiconductor, Application Note (http://www.aosmd.com/res/application_notes/mosfets/Power_MOSFET_Basics.pdf).

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http://www.aosmd.com/res/application_notes/mosfets/Power_MOSFET_Basics.pdf


Thank you!

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SPICE Modeling of Power Devices - MOS-AK