P01 Yoshizaki MOS-AK

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    RF Modeling of Sub-100 nm

    CMOS

    S.Yoshizaki1, M.Nakagawa1, W.Y.Chong1, Y.Nara2,

    M.Yasuhira2*

    , F.Ohtsuka2

    , T.Arikado2**

    , K.Nakamura2

    ,K.Kakushima1, K.Tsutsui1 H.Aoki1, H.Iwai1

    1 Tokyo Institute of Technology2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan* Current affiliation : Matsushita Electric Industrial Co., Ltd., Japan** Current affiliation : Tokyo Electron Ltd., Japan

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    0%

    20%

    40%

    60%

    80%

    100%

    2004 2005 2006 2007 2008 2009

    Fig.1 4-th Generation mobile

    Center Research Laboratory,Hitachi Ltd.

    Spread of the cellular phone and thewireless LAN.

    The age of Digital information appliances

    RF technologies serve the rapidlygrowing wireless communication markets.

    Background ~RF Technology~

    Accurate RF Modeling become

    important to more than before.

    But

    ITRS2004update, 2004

    Fig.2 Technology-development costreduction (due to TCAD)

    In RF, some parasiticelements effect more severe.

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    MeritLow cost compared with

    compound semiconductors

    Consolidation with logic

    circuits

    Low operation voltage with

    scaling

    ScalingandCircuit

    technologies improvefT and fmax

    Feature in RFCMOS

    Demerit

    SN ratio degradation

    Fig.3 Application Spectrum ITRS2004, 2004

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    Degradation of dielectric constant with dielectric relaxation.

    RF characteristic deterioration with degrading mobility.

    Increase interface state density Increase Low-frequencynoise and thus Phase noise.

    The concern about High-k

    MOSFET in RF

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    Motivation

    There are little reports about RF

    performance evaluation and modeling with

    High-k MOSFETs.

    Comparison HfSiON with SiON.

    RF Modeling of Sub-100 nm High-k MOSFET

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    Device EOT = 1.5nm (HfSiON & SiON)

    Gate lengthHfSiON (Lg= 64nm), SiON (Lg= 51nm)

    The number of finger = 12 W=5m

    Fig.4 HfSiON MOSFET structure

    silicide

    HfSiON SiN

    Si

    silicide

    SiON SiN

    Si

    Fig.5 SiON MOSFET structureG G G G G

    S S SD D

    M1

    STI

    VIA1

    63.9nm 61.7nm 62.3nm 65.5nm 65.3nm

    S S

    S S

    G

    D

    S

    D

    Increase gate width with increasing number of

    fingers, the gate resistance become small.

    23

    1

    f

    totshG

    LN

    WRR Nf

    : The number of finger

    Fig.6 Section of HfSiON MOSFET

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    DC Measurement and Simulation

    HfSiON

    0.00E+00

    1.00E-04

    2.00E-04

    3.00E-04

    4.00E-04

    5.00E-04

    6.00E-04

    0 0.5 1 1.5

    Vd[V]

    Id/

    [

    Fig.7 Measured and simulated Ids-Vds

    HfSiON

    Vgs=0, 0.6, 0.9, 1.2, 1.5V Measured

    Simulated

    0.00E+00

    1.00E-04

    2.00E-04

    3.00E-04

    4.00E-04

    5.00E-04

    6.00E-04

    7.00E-04

    0 0.5 1 1.5

    Vd[V]

    Id/

    [A

    Fig.8 Measured Ids-Vds SiON

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    To de-embed parasitic elements including wires

    and pads is important that could obtain the realdevice parameters.

    RgLg

    Cg

    Rgp

    Cgd Rgdp

    Ld RdCd

    Rdp

    Rs

    Ls

    DUTDrain

    SHORT

    De-embedding

    BSIM4

    OPEN

    Gate

    DrainGate

    Gate

    Drain

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    Measured and Simulated fT, fmaxHfSiON

    fT,HfSiON = 189.9[GHz]fmax,HfSiON = 59.9[GHz]

    GS

    mT

    C

    gf

    2

    )2)((2

    max

    GDGTSGds

    t

    CRfRRg

    ff

    Fig.9 H21 and GAmax vs. Frequency HfSiON

    Fig.10 Equivalent circuit model

    Rg

    CGD

    CGS

    LD

    RD

    BSIM4

    0

    10

    20

    30

    40

    50

    0.1 1 10 100 1000

    Frequency[GHz]

    2

    1,

    ax[d

    Measured GAmax

    Simulated GAmax

    Measured H21

    Simulated H21

    Vg=1.2V, Vd=1.5V

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    Measured S-parameter and

    Predicted fT, fmax SiON

    0

    10

    20

    30

    40

    50

    60

    0.1 1 10 100 1000

    Frequency[GHz]

    21,

    ax[d

    fT,SiON = 236[GHz]

    fmax,SiON = 74[GHz]

    Fig.11 H21 and GAmax vs. Frequency SiON

    Measured GAmax

    Extrapolated GAmax

    Measured H21

    Extrapolated H21

    Vg=1.2V, Vd=1.5V

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    RF Characterization~ fT & gm Comparison HfSiON with SiON~

    gm peak

    0

    50

    100

    150

    200

    250

    0.01 0.1 1 10 100

    Id[A]

    f

    [

    z

    0

    10

    20

    30

    40

    50

    60

    70

    80

    90

    100

    g

    [

    S

    fTSiON

    fTHfSiON

    gmSiON

    gmHfSiON

    Cross SiON andHfSiON characteristics

    Fig.12 fT and gm vs. Id

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    Position of this device

    0

    50

    100

    150

    200

    250

    300

    0.01 0.1 1

    [m ]

    ft

    [GH

    z

    nmos

    pmos

    SiON

    HfSiON

    0

    50

    100

    150

    200

    250

    300

    0.01 0.1 1

    [m ]

    fmax[G

    Hz]

    nmos

    pmos

    Gate Length [um] Gate Length [um]

    Fig.13 fT and fmaxIEDM, VLSI 1995 2004

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    We measured and simulated High-k MOSFET RF

    characteristics.

    Measured from 500MHz to 40GHz, there is no dielectricrelaxation.

    Simulated fT and fmax in HfSiON, we obtained good fT

    (189.9GHz) relatively.

    SiON is expected much more high performance thanHfSiON. I guess this is because of mobility degradation.

    Summary

    This work was partially supported by Special Coordination

    Funds for Promoting Science and Technology by Ministry of

    Education, Culture, Sports, Science and Technology, Japan.

    Acknowledgement

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    nmos

    1.00E-19

    1.00E-18

    1.00E-171.00E-16

    1.00E-15

    1.00E-14

    0.01 0.1 1 10 100Frequency[kHz]

    Sid[A^2

    /Hz]

    SiON

    HfSiON

    Id=1mA / Vd=0.1V

    Appendix A

    ~Flicker noise~

    Fig.14 Flicker noise

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    15/158 inch wafer 40 GHz

    Appendix B

    ~RF CMOS Evaluation Equipment~