Speedster22i HD FPGA Family

I

Highlights• Advanced highest‐density and highest‐bandwidth

FPGA

Over 1.7 million effective look‐up‐tables

Abundant embedded hard IP for communica‐tions applications

Fully reprogrammable, SRAM based

Synchronous core and I/O

Built on Intel’s advanced 22‐nm 3‐D Tri‐Gateprocess technology

• Large capacity

Up to 1.7 million effective look‐up‐tables

Up to 138 Mb of Block RAM

80 Kb block RAMs running at 750 MHz

640 bit logic RAM (LRAM) running at750 MHz

• Industry‐standard register transfer level (RTL)synthesis support:

Synplify‐Pro from Synopsys

Precision Synthesis from Mentor Graphics

Rapid timing closure yielding significant time‐to‐market advantages

• Embedded (Hard IP)

10/40/100 gigabit Ethernet MAC

PCI Express Gen 1/2/3, x1, x4, x8 with DMAengine

DDR 1/2/3 72 bits wide

Interlaken

• Up to 64 channels of embedded 12.75 Gbps SerDesand 16 channels of embedded 28 Gbps SerDes sup‐porting protocols including:

PCI Express Gen 1/2/3

10/40/100 gigabit Ethernet (XFI, XAUI, XLAUI,CAUI)

Interlaken

Fibre Channel

SATA/SAS

OC48

CEI‐6 SR/LR, CEI‐11 SR

GPON/EPON

CPRI/OBSAI

Product Tablex

Speedster22i HD FPGA FamilyDS004 Rev. 1.8– Sept 24, 2012 Advance

Table 1: Speedster22i HD FPGA Family Members

Features HD210 HD680 HD1000 HD1500

Logic Capacity inc. embedded IP (effective 4-input LUTs) 265,000 660,000 1,045,000 1,725,000

Programmable LUTs 100,000 400,000 700,000 1,100,000

Number of Block RAMs (80 Kb) 200 600 1,026 1,728

Block RAM (total Kb) 16,000 48,000 82,080 138,240

Distributed RAM (total Kb) 256 1,024 3,940 6,636

Multiplier/Accumulators (BMACs) 110 240 756 864

SerDes Lanes 12.75 Gb/s 24 32 64 64

SerDes Lanes 28 Gb/s - 4 - 16

10G Ethernet MAC 12 24 24 48



Interlaken LLC 1 1 2 4

PCI Express LLC 2 2 2 2

DDR3/DDR2 Controller 2 4 6 6

Number of PLLs 16 16 16 16

User (Programmable) I/Os 372 684 996 996

DS004 Rev. 1.8– Sept 24, 2012 www.achronix.com PAGE 1

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Packaging Options Speedster22i HD FPGA Family

Packaging OptionsSpeedster22i FPGAs are available in a variety of package options. Most adjacent family members are available inthe same package and are pin‐compatible, allowing migration between the members without a board layoutchange.

The package options are listed in Table 2.

Table 2: Speedster22i FPGA Packaging

Package OptionsAvailable SerDes and I/O

(12.75 Gbps SerDes, 28 Gbps SerDes, User I/O)

HD210 HD680 HD1000 HD1500

FBGA2597 (52.5-mm x 52.5-mm, 1-mm ball pitch) 64, 0, 996 48, 16, 996

FBGA1936 (45-mm x 45-mm, 1-mm ball pitch) 32, 4, 684 32, 0, 684 20, 4, 684

FBGA2597 (45-mm x 45-mm, 0.82-mm ball pitch) 32, 4, 684 64, 0, 996 64, 16, 996

FBGA2597 (52.5-mm x 52.5-mm, 1-mm ball pitch) 24, 0, 372 12, 4, 684

FBGA2597 (52.5-mm x 52.5-mm, 1-mm ball pitch) 24, 0, 372

PAGE 2 www.achronix.com DS004 Rev. 1.8– Sept 24, 2012

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Speedster22i HD FPGA Family Device Overview

Device OverviewSpeedster22i® HD devices run at a maximum rate of750 MHz and have effective densities of up to 1.7Million LUTs. Based on the Intel 22nm process,Speedster22i HD devices are SRAM based and fullyreconfigurable. Logic resources are provided usingstandard, synchronous, 4‐input Look Up Tables (LUT).A reconfigurable logic block (RLB) contains ten LUTs,and has ten registers. Speedster22i HD devices alsocontain block RAMs. Each block RAM is 80 kbit in sizeand allows true dual port access.

The I/O Frame contains embedded controller IP,configurable I/Os, SerDes, clock generator blocks withphase lock loops (PLLs), and the device configurationlogic. Speedster22i FPGAs contain up to sixty fourlanes of 12.75 Gbps SerDes, up to sixteen lanes of 28Gbps SerDes and up to an additional 996 high‐speed

reconfigurable I/Os. Additional dedicated hard IPincludes up to six DDR1/2/3 PHY and controllers, up toforty eight 10 Gb Ethernet controllers, up to twelve 40GEthernet controllers and up to four 100G Ethernetcontrollers. There are also are up to four Interlakencontrollers and two PCI Express controllers, allavailable as embedded hard IP and therefore use noneof the reconfigurable logic fabric and achievemaximum performance without the need for timingclosure/optimization.

There are also dedicated I/Os for the embeddedprogramming and configuration logic (CFG) designedto support a variety of programming options.Dedicated clock I/O pins are located near the corners ofeach Speedster device. Figure 1 gives an overview ofSpeedster22i Devices

Figure 1: Speedster22i HD Device Overview

PLLs PLLsSerDes

Interlaken LLC (×6, ×8, ×10, ×12)

PCI Express LLC(×1, ×4, ×8)

& DMA Controller

10/40/100G EthernetPCS & MAC

PLLs PLLsSerDes


& DMA Controller

Interlaken LLC

Configuration Logic

DD

R1/2

/3 P

HY a

ndCo

ntro

ller

DD

R1/2

/3 P

HY a

ndCo

ntro

ller

DD

R1/2

/3 P

HY a

ndCo

ntro

ller

GPIO

DD

R1/2

/3 P

HY a

ndCo

ntro

ller

DD

R1/2

/3 P

HY a

ndCo

ntro

ller

DD

R1/2

/3 P

HY a

ndCo

ntro

ller

GPIO

Programmable Core:Logic (RLBs)Block RAMs (BRAMs)Local RAMs (LRAMs)Block Multipliers (BMULTs)

D100001 v1.0Not drawn to scale



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FPGA Core Speedster22i HD FPGA Family

FPGA CoreThe core of an Achronix Speedster22i HD FPGAcontains columns of Logic, Memory andMultiplier/Accumulators (BMACs) connected with aglobal interconnect as shown in figure 2 below.Columns of Reconfigurable Logic Blocks (RLBs) are

interspersed with Columns of Block RAMs (BRAMs)and Local Rams (LRAMs) and BMACs. The core alsoincludes global and local clock networks as well asreset networks. The columns of Logic resources areshown in Figure 2:

Figure 2: Programmable Core ‐ Columns of RLBs, BRAMs, LRAMs and BMACs

PLLs PLLsSerDes

Interlaken LLC (×6, ×8, ×10, ×12)


& DMA Controller


PLLs PLLsSerDes


& DMA Controller

Interlaken LLC10/40/100G Ethernet

PCS & MACConfiguration Logic

DD

R1/2

/3 P

HY

and

Cont

rolle

rD

DR1

/2/3

PH

Y an

dCo

ntro

ller

DD

R1/2

/3 P

HY

and

Cont

rolle

r

GPI

O

DD

R1/2

/3 P

HY

and

Cont

rolle

rD

DR1

/2/3

PH

Y an

dCo

ntro

ller

DD

R1/2

/3 P

HY

and

Cont

rolle

r

GPI

O


RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

RLB

Colu

mn

BRA

M C

olum

n

LRA

M C

olum

n

BRA

M C

olum

n

BMAC

Col

umn

BMAC

Col

umn


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Speedster22i HD FPGA Family FPGA Core

Global Interconnect

The RLBs, BRAMs, LRAMs and BMACs are connectedby a uniform global interconnect. This enables therouting of signals between core elements. Switch Boxesmake the connection points between vertical and

horizontal routing tracks. Inputs to and Outputs fromeach RLB/BRAM/LRAM/BMAC connect to the globalinterconnect. An example of an RLB with 8 used inputsand 2 outputs is shown in Figure 3.

Figure 3: Global Interconnect Routing (Conceptual)

RLB RLB

RLBRLB

RLBRLB

BRAM

BRAM

BRAM

SwitchBox

SwitchBox

SwitchBox

SwitchBox



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The Reconfigurable Logic Block (RLB)

The Reconfigurable Logic Block (RLB), is comprised offive Logic Clusters, each of which contains two LUTsand two registers. This gives a total of ten, 4‐inputLUTs in a single RLB.

There are two types of Logic Cluster, the Light LogicCluster (LLC) and the Heavy Logic Cluster (HLC).Each RLB has three LLCs and two HLCs. The HLC is a

super‐set of the LLC, as it includes an advanced carrychain not present in the LLC.

The RLB is illustrated in Figure 4. Essentially, an RLBconsists of five pairs of Logic Clusters, two pairs with acarry chain. This carry chain has its own RLB input andoutput to allow chaining to be cascaded throughmultiple RLBs.

Efficient RLB Feedback

There are several feedback mechanisms within the RLBto allow efficient feedback, i.e feedback signals thatstay within the RLB instead of having to use externalrouting resources.

A single signal matrix exists in the RLB. Thismultiplexes:

• Inputs – Routes the RLB inputs and Internal Feed‐back signals to the Logic Clusters

• Outputs – Routes the Logic Cluster outputs (regis‐tered and unregistered) to the RLB outputs and

also back to the Input Matrix where feedback isrequired

Figure 4: The Reconfigurable Logic Block

LLC

LLC

Carry In

HLC

HLC

LLC

D100001 v1.0

Switch Matrix

Switch Matrix

Carry Out

From Global Interconnect

To Global Interconnect

Internal Loopback


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Speedster22i HD FPGA Family FPGA Core

The details of internal RLB feedback paths are shownin Figure 5:

Both Registered and unregistered outputs from eachLUT can also be routed from the output matrix backinto the input matrix without leaving the RLB.

The outputs from the RLB can also be routed back intothe inputs via the external Routing if needed (notshown).

The Light Logic Cluster

The Light Logic Cluster (LLC) is illustrated in Figure 6.

The standard 4‐input LUT is the fundamental logicbuilding block of the fabric. Each LUT has four inputsand a single output, and can be configured to make theoutput reflect any combinatorial (truth table) functionof the inputs. The two four‐input LUTs can implementa single five‐input LUT function with the utilization ofthe MUX2. The MUX2 also enables the implementationof certain six, seven, eight and nine‐input functions.

Multiplexing blocks (shown in Figure 5) provide flexibleaccess to the two register outputs.

Figure 5: The Reconfigurable Logic Block

LUT

LUT

LUT

LUT

LUT

SwitchBox

D100004 v1.0


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The Heavy Logic Cluster

The Heavy Logic Cluster (HLC) is illustrated inFigure 7. All functionality possible with the LightLogic Cluster can also be implemented in a HLC. Inaddition, each cluster has a 2‐bit adder as well as the

logic needed for generation of an arithmetic carrysignal and propagation to the HLC to the north basedon the RLB inputs and the carry in signal from itsneighbor to the south

Figure 6: The Light Logic Cluster

LUTB

LUTA

B4

B3

B2

B1

B0

A0

A1

A2

A3

A4

Shift In

Shift Out

OUTL[0]

OUTL[1]

OUT[0]

OUT[1]

D100005 v1.0

Figure 7: Heavy Logic Cluster

LUTB

LUTA

B4

B3

B2

B1

B0

A0

A1

A2

A3

Shift In

Shift Out

OUTL[0]

OUTL[1]

OUT[0]

OUT[1]

D100005 v1.0

10

Carry Out

Carry In

A4

ADD2

b0b1d1load

a0a1d0

s1s0

co

ci


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Speedster22i HD FPGA Family Memory Resources

Memory ResourcesBlock RAMs (BRAM)

The Block RAM (BRAM) contained within theSpeedster22i is an 80Kbit, true dual port memory (2independent read/write ports). The BRAM providessupport for write‐through and no‐change modes (nosupport for read‐first mode).

The key features (per Block RAM) are summarized inTable 3, and illustrated in Figure 8

Organization

The organization of each block RAM port can beindependently configured (the available organizationsare listed in Table 3).

NOTE: Access from opposite ports are not required to havethe same organization; however, the number of total memorybits on each port must be the same.

Operation

The read and write operations are both synchronous. Forhigher performance operation, an addition outputregister can be enabled. Enabling the output register willadd an additional cycle of read latency.

Write Enable (wea/web) controls provide 10‐bit enablecontrol for port widths of 20 or 40 bit.

The initial value of the memory contents may be specifiedby the user from either parameters or a memoryinitialization file. The initial/reset values of the outputregisters may also be specified by the user. The resetvalues are independent of the initial (power‐up) values.(They donʹt need to match.)

The porta_write_mode/portb_write_mode parametersdefine the behavior of the output data port during a write

operation. When porta_write_mode/portb_write_mode isset to write_first, the douta/doutb is set to the value be‐ingwritten on the dina/dinb port during a write operation.Setting porta_write_mode/ portb_write_mode tono_change keeps the douta/ doutb port unchanged duringa write operation to porta/portb.

Built in FIFO Controller

Each BRAM has a FIFO controlled built into it. EachFIFO is capable of operating with two independentports and asynchronous or synchronous access.

Error Correction

The 40‐bit bus width provides an 8 bit overhead foruser implementation of parity or Error CorrectionCodes (ECC), on a 32‐bit wide data bus. Of course,these overhead bits can be used for other purposes aswell: tagging, various control functions, etc.

Initialization and Reset

Initial content of the block RAMs is loaded duringdevice configuration. On reset, the RAM contents areunchanged.

The initial state of the RAM read outputs is also loadedduring device configuration. Unlike the RAM content,this default output state is restored on reset.

Table 3: Block RAM Key Features

Feature Value

Block RAM Size 80 Kb

Organization 2k x 40, 2k x 36, 2k x 32, 4k x 20, 4k x 18, 4k x 16, 8k x 10, 8k x 9, 8k x 8, 16k x 5, 16k x 4, 32k x 2, 64k x 1

Performance 750 MHz

PhysicalImplementation

Columns throughout device

Number of Ports Dual port (independent read and write)

Port Access Synchronous

Figure 8: Block RAM I/O

BRAM80K

addra[15:0]dina[31:0]dinpa[3:0]

dinpxa[3:0]wea[3:0]

pearstlatcha

outregceaclka

douta[31:0]doutpa[3:0]

doutpxa[3:0]

addrb[15:0]dinb[31:0]dinpb[3:0]dinpxb[3:0]web[3:0]pebrstlatchboutregcebclkb

doutb[31:0]doutpb[3:0]doutpxb[3:0]

D100007 v1.0


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Memory Resources Speedster22i HD FPGA Family

Logic RAM (LRAM)

The Local RAM (LRAM640) implements a 640‐bitmemory block with one write port and one read port.LRAMs are included in dedicated columns spreadthroughout the device. Each LRAM is a single 640‐bitblock of dedicated memory. A summary of LRAMfeatures is shown in Table 4.

The LRAM ports are shown in Figure 9.

Organization

The LRAM640 can be configured as either a 64x10simple dual‐port (1 write port, 1 read port) RAM or a64x10 single port (1 read/write port) RAM.

Initialization and Reset

By default, the contents of the LRAM640 memory areundefined. If the user wants the initial contents to bedefined, he may assign them from either a file pointedto by the mem_init_file parameter or assign them fromthe value of the mem_init parameter.

Operation

The LRAM640 has a synchronous write port. The readport can be configured for either asynchronous orsynchronous read operations. The read port output hasa register that can be bypassed.

The memory is organized as little‐endian with bit 0mapped to bit zero of parameter mem_init and bit 639mapped to bit 639 of parameter mem_init.

Table 4: Logic RAM Key Features

Feature Value

Logic RAM size 640 bits

Organization 64 x 10

Performance 750 MHz

Physical Implementation Dedicated Columns

Number of Ports Simple dual port (one read, one write), or Single port (one read/write port)

Port Access Synchronous writes, Asynchronous or Synchronous Reads

Figure 9: Logic RAM I/O

LRAM640

waddr[5:0]din[9:0]

wrendinpxa[3:0]

wclk

rdaddr[5:0]rstregn

outregcerdclk

dout[9:0]

D100008 v1.0


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Speedster22i HD FPGA Family Multipliers / BMAC56

Multipliers / BMAC56The Multiplier / Accumulator (BMACC56) blockimplements a signed 28x28 multiplier followed by anoptional accumulator block. The multiplier produces a56‐bit result which is fed into (or bypasses) the 56‐bitaccumulator. The key features are summarized inTable 5.

Multiplication and Accumulation is an important part ofreal‐time digital signal processing (DSP) applicationsranging from digital filtering to image processing.Speedster 22i HD devices have numerous BMACC56instances arranged in columns. Each BMACC56 blockhas a 56‐bit cascaded path interconnecting adjacent(north/south) BMACC56 blocks.

The BMAC I/O are illustrated in Figure 10.

The internal block diagram is shown in Figure 11

Table 5: Multiplier Features

Feature Value

Arithmetic Type Two's complement (signed)

Performance 750 MHz

Multiplier Size 28 X 28

Accumulate Size 56bits

Cascade Size 56bits

Figure 10: BMAC I/O

a[27:0]ce_arst_a

b[27:0]ce_brst_b

mask_addace_mask_addarst_mask_adda

subce_subrst_sub

cince_cinrst_cin

cascade_in[55:0]

cascade_out[55:0]

clk

dout[55:0]

cout

ce_doutrst_dout

BMACC56

Figure 11: BMAC Block Diagram

qced

r

5656

1cascade_in[55:0]

qced

r

qced

r

qced

r

qced

r

28

28

a[27:0]:b[27:0]

01

qced

r

qced

r

cout

dout[55:0]

cascade_out[55:0]

mask_addace_mask_adda

rst_mask_adda

a[27:0]ce_a

rst_a

b[27:0]ce_b

rst_b

subce_sub

rst_sub

cince_cin

rst_cin

ce_doutrst_dout

Signedadd/sub

adda

addb

sub

cin

dout

cout

multout[55:0]

mult[55:0]

qd

01


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Clocking and Reset Resources Speedster22i HD FPGA Family

Clocking and Reset ResourcesGlobal Clock Network

Speedster22i FPGAs have a hierarchical global clocknetwork. Input clock sources are channeled to theClock Hub, located in the center of the device. Theseinputs include ‐ direct clock input pins, PLL outputs,Byte lane Clocks from the I/O and recovered SerDesinput clocks. The north and south side of the ClockHub have separate inputs and outputs, but the hub

itself can multiplex signals between the twogeographies. Each clock input bus (north, south) is 104bits wide. Each clock output bus from the Clock Hub is32bits wide. The global clock routing structures ensurevery low skew occurs from the Clock Hub to the ClockRegion inputs. The global clock network is shown inFigure 12.

Figure 12: Global Clock DistributionD100001 v1.0

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Region

Clock Hub

Clock Region

PLL

GCGs

PLLPLLs

SerDes

SerDes

32

32

I/O Bank

I/O Bank

Byt

e La

nes

Byt

e La

nes

Byt

e L

ane

sB

yte

La

nes

Byt

e L

anes

Byt

e L

anes

Byt

e La

nes

Byt

e L

anes

I/O Bank

I/O Bank

Byt

e La

nes

Byt

e La

nes

Byt

e L

ane

sB

yte

La

nes

Byt

e La

nes

Byt

e La

nes

Byt

e L

ane

sB

yte

La

nes

PLLs

PLLs

Clock Buffers

32

32

12

20

166

South Clock Tree

North Clock Tree

PLL

GCGs

PLLPLLsClock

Buffers 166

20

PLLs

32

32

32

PLLsPLL

GCGs

PLLPLLs Clock Buffers

16

6 PLL

GCGs

PLLPLLsClock

Buffers 6

16

2020


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Speedster22i HD FPGA Family Clocking and Reset Resources

Clock Regions

Each Clock Region can select 12 inputs from the 32supplied by the associated global clock network (Northor South).

A clock region comprises of 135 columns of logicfabric. Each column has either 36 RLBs, or 6 BRAMs, or36 LRAMs or 6 BMACs depending on the columncontents.

The total resources for a Clock Region are:

• 4320 RLBs (43K LUTs)

• 120 80Kbit BRAMs

• 4320 LRAMs

• 120 28x28 BMACs.

Each Clock Region has 12 internal clocks. These 12 aremuxed in from the 32 Global Clocks delivered by thelow skew global clock network. The Region ClockManager (RCM) provides the ability to dynamicallyclock gate the region, as well as dynamically selectamong the 32 global clocks for routing into the localClock Region

Figure 13 below shows an example Clock Region.

Global Clock I/O buffer

As shown in Figure 12, page 12, each corner of aSpeedster22i FPGA has eight Global Clock I/O buffers(CBs). These buffers can be used as either fourdifferential I/Os or eight single‐ended I/Os. If theseinputs are not used as clock buffers, they can be usedas generic inputs.

Global Clock Generator

Each corner of a Speedster22i FPGA has four GlobalClock Generators (GCGs), consisting of a PLL withprogrammable clock synthesizers at the output. Eachof four outputs (Figure 14, page 15) can pick any of the

eight phases of the output clock. Each PLL output canalso dynamically step through the phases sequentially.

One of the four outputs from each PLL in a corner can berouted to any of the eight I/Os of the clock bank in thatcorner. Hence, the output from the PLL can be sent outdirectly through any I/O of the clock bank in that corner.

Note: This output has a unique pin designation in the macro library element for the PLL.

The Clock Generator PLL performance specificationsare listed in Table 6, page 14.

Each PLL output has an additional programmableOutput Synthesizer (OS) which can be bypassed. TheOS output frequency can be a divided version of the

Figure 13: Clock Regions

Low Skew Clock Network

3212

Clock Region

RLBsBRAMsMULTs RLBsRLBsBRAMsMULTs LRAMs

RLBsBRAMsMULTs RLBs

RLBsBRAMsMULTs RLBs

RLBsBRAMsMULTs LRAMs


RLBsBRAMsMULTs RLBs

RLBsBRAMsMULTs RLBs



RLBsBRAMsMULTs RLBsRLBsBRAMsMULTs LRAMs

RCM

Dynamic Gating

Dynamic Switching


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input from 1 (bypassed) to 2,046. There areindependent 10‐bit count settings available to controlthe pulse width for the high and low cycle of the clockoutput. The sum of these two counter settingsdetermines the frequency divisor. In addition, the highcycle on the clock can optionally be extended by onehalf cycle. This feature is useful when a 50% duty cycleoutput is desired for an odd divisor.

Each output has an Output Gate (OG) circuit. The OGcircuit synchronizes the clock enable (clken) input fromthe FGPA logic fabric with the clock output from theOS. This synchronized signal can enable or disable theclock output. This capability can be selectively enabledor disabled individually for each output in theconfiguration of the Global Clock Generator. Theoutput clock and input of the OS will be phase aligned.The input clock of the Global Clock Generator cancome from:

• Global Clock I/O buffer

• Other Global Clock Generator

The feedback input of a Global Clock Generator (Figure 15) receives its inputs from Global Clock Networkendpoints, Global Clock Input Buffers and from its own output.

Table 6: Clock Generator PLL Performance Specifications

Performance SpecificationsReference clock frequency range

30 MHz – 400 MHz

Divide by 1 output frequency range(VCO output internally divided by 2 for 50% DC)

200 MHz – 1 GHz

Reference divider values 1–64Feedback divider values 8 (2 to 255)

In fractional mode, only supports 8 to 254

External feedback divider values

1

Output divider values 1–8

Number of adjustable phase outputs

4

Number of internal phases 16Internal phase separation 6.25% output cycleInternal phase accuracy ±2.5% output cycle at

1 GHzDivide by 1 output multiples of div. reference

2–512

Bandwidth adjustment div. range

1–4096

Feedback signal delay (max)

Output duty cycle(nominal tolerance)

50%, ±2%

Static phase error (max) ±1% div. reference cyclePeriod jitter (P-P) (max) ±2.5% output cycleInput-to-output jitter (P-P) (max)

±1.25% div. reference cycle

Power dissipation (nom) 5 mA at 500 MHz (Divide by 1 output)

Reset pulse width (min) 5 usReset divide by 1 output frequency range

10 MHz – 100 MHz

Lock time (min allowed) 500 div. reference cyclesFrequency overshoot (full-~/half-~) (max)

40%/50%

Reference input jitter (long-term P-P, max)

2% div. reference cycle

Reference/feedback pulse width (min)

190 ps

Supply voltage (VDD, VDDA) (nominal tolerance)

1.0 V ±10%

Table 6: Clock Generator PLL Performance Specifications

Performance Specifications

1.51GHz FREF

--------------------------------------


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Speedster22i HD FPGA Family Clocking and Reset Resources

Figure 14: PLL Block Diagram

ReferenceClock

FeedbackClock

NF÷

(1 - 256)

NR÷

(1 - 64)

OD÷

(1 - 8)

OD÷

(1 - 8)

OD÷

(1 - 8)

OD÷

(1 - 8)

PhaseFrequencyDetector

VoltageControlledOscillator

PLL_CLKOUT[0]

PLL_CLKOUT[1]

PLL_CLKOUT[2]

PLL_CLKOUT[3]

ds001_31_v03

Figure 15: Global Clock Generator

PLL

clkout[0]

clkout[1]

clkout[2]

clkout[3]

OS

OS

OS

OS

readyclken

fbclk

refclk

OG

OG

OG

OG

ds001_35_v02


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Byte-Lane Clock Networks

Separate from the Global Clock Network, each I/OBank in a Speedster22i FPGA has an independent Byte‐Lane Clock Network designed for source‐synchronousinterfaces.

A byte lane in a Speedster22i FPGA consists of 12 I/Obuffers. Two of these I/O Buffers are clock capable andcan be used to receive or send a clock. These bufferscan be used as one differential pair for a clock or as twosingle‐ended buffers for two clocks. Each of thesereceived clocks can optionally be delayed using a DLL.

The Byte‐Lane Clock Network supports four byte lanesin a repeating fashion. For example, there are threeByte‐Lane Clock Networks in an I/O Bank with 12bytes: byte 0 to 3, byte 4 to 7, and byte 8 to 11.

Each Byte‐Lane Clock Network can function as follows:

• Eight by‐9 clock networks

• Four by‐18 clock network

• One by‐36 clock network

Speedster22i Reset Resources

Reset Input Block

Each corner of a Speedster22i FPGA has an individualReset Input Block. This block receives external resetinputs as well as inputs generated internally within thedevice. External reset inputs are driven by dedicatedclock pads. Internal reset inputs are driven using adedicated reset network within the logic fabric and canbe driven into the Reset Input Blocks.

The inputs to the Reset Input Block generated eitherexternally or internally are required to be active‐Low andglitch free. The input resets can be either asynchronous orsynchronous. An asynchronous reset is synchronized forde‐assertion to each and every clock domain where it isutilized. A synchronous reset does not need to besynchronized to the same clock domain but issynchronized when used in any other clock domain notsynchronous with the current clock domain.

Each reset output generated by the Input Reset Block issynchronized to a selectable clock domain by a resetsynchronizer. The clock domain is selected by a clockmultiplexer located within a bank physically close tothe Input Reset Block, ensuring that the synchronouselements in the device have balanced latency for boththe clock and associated reset.

The input to the reset synchronizer is driven by aninput reset multiplexer, allowing selection of one of theinputs from the Input Reset Block

Reset Network

The reset outputs of the Input Reset Blocks aredistributed to each of the I/O banks and major blocks ofthe device using a hierarchical reset distribution network.A balanced reset assertion and, more importantly, de‐assertion latency is required across the entire device,made possible by pipelining the reset distribution usingthe clock to which the reset is synchronized. The resetnetwork consists of two hierarchies:

• Global Reset Network

• Bank Reset Network

Global Reset Network

Each side of the device has two groups of reset signalsrunning in opposite directions. Each group consists ofeight reset signals each, spanning the entire edge of thedevice in a pipelined manner. The two groups of resetsignals are tapped at each I/O bank or logic blocks(such as DDR controller, SERDES, etc.), using aconfigurable pipeline multiplexer with configurablepipelined latency. The configuration is set for eachmultiplexer individually to balance the latency for eachreset signal across the entire device. The outputs of thepipeline multiplexer are subsequently distributed tothe bank reset network.

Bank Reset Network

Each I/O bank receives the outputs of the pipelinemultiplexers. For example, the I/O bank at the bottomleft of the device (BSW) receives 16 reset inputs, eightfrom the reset group driven North and eight from thereset group driven South. The 16 reset inputs aredistributed across the entire bank and are received byreset multiplexers associated with each clockmultiplexer. The reset multiplexers then select theappropriate reset associated with the clock inputselected by the corresponding clock multiplexer. Thereare two‐pipeline multiplexers for each reset line todrive across the I/O bank. Each logic block similarlyreceives the outputs of the pipeline multiplexers andfeeds the reset signals into a reset multiplexer presentfor each clock multiplexer within the block.


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Speedster22i HD FPGA Family Embedded (Hard) IP

Embedded (Hard) IPSpeedster22i HD devices include several embedded(Hard) IP blocks. These implement the followingprotocols:

• DDR 1/2/3

• PCI Express Gen 1/2/3, x1, x4, x8

• 10/40/100Gbit Ethernet

• Interlaken ‐ up to 12 lanes (two cores can be com‐bined to make a single 24 lane interface)

• DMA engine for PCIe

This section provides an overview of the capabilities ofthese IP blocks and their connectivity to the fabric forthe user to interface to.

The following diagram shows the quantity andlocation of the IP blocks on the HD1000.

Figure 16: Speedster Device Overview

PLLs PLLsSerDes

Interlaken LLC(×6, ×8, ×10, ×12)

PCI Express LLC(×1, ×4, ×)8

& DMA Controller

10/40/100G Ethernet PCS & MAC

PLLs PLLsSerDes


& DMA Controller

Interlaken LLC


Configuration Logic

DD

R1/2

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and

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rD

DR1

/2/3

PH

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DD

R1/2

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and

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r

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R1/2

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OProgrammable Core



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Embedded (Hard) IP Speedster22i HD FPGA Family

DDR Controller

Speedster22i HD devices contain up to 6 embeddedDDR1/2/3 controllers which can be used to interfacewith and control off‐chip DDR3 memory devices or

DIMMs. Each of the DDR3 controllers supports up to72 bits wide data up to 2133 Mbps (1066MHz DDR).

The DDR3 controller supports both “auto” and“custom” modes. When in the “auto” mode, functionssuch as (but not limited to) activating/prechargingbanks/rows, running calibration algorithms, andinitialization sequences are handled transparently tothe user (by the DDR Core logic) in the embeddedDDR Controller. The mapping of byte lanes to pins ishandled transparently by the embedded DDR PHY.

When in “custom” mode the user has the option tomanually override functions such as automated refreshand initialization engines/sequences

Features:

• 2133 Mbps data rate

The controller and PHY runs up to 1066MHz.To achieve 2133Mbps data rate a 2X Clock set‐ting must be enabled, allowing the logic fabricto operate at half rate (533MHz). The 2X clock

setting can be enabled regardless of the datarate, allowing the interface to the fabric to runat half the rate of the Hard IP controller

• 8:1 DQ:DQS ratio

The controller support 8 DQ signals for everyDQS.

A 4:1 ratio can be used at the cost of half theavailable memory space

• 4 Chip Selects (Ranks) per controller

The external memory connected to each con‐troller can comprise of up to 4 ranks (either 4single‐rank DIMMs or 2 dual‐rank DIMM)

• Registered DIMM and Unbuffered DIMM support

Each controller can independently supporteither rDIMMs or uDIMMs

• Address mirroring is supported. This feature istypically required for dual‐rank uDIMMs

Figure 17: Embedded DDR 1/2/3 Controller

PLLs PLLsSerDes

Interlaken LLC(×6, ×8, ×10, ×12)

PCI Express LLC (×1, ×4, ×8)

& DMA Controller

10/40/100G Ethernet PCS & MAC

PLLs PLLsSerDes


& DMA Controller

Interlaken LLC


Configuration Logic

DDR1

/2/3

PHY

and

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rolle

rDD

R1/2

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DDR1

/2/3

PHY

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PHY

and

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DDR1

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PHY

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Programmable Core


NW

WC

SW

NE

EC

SW


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• Multi‐Burst Mode

Each controller supports multi‐burst mode, upto a burst length of 252 (DDR2) / 254 (DDR) /248(DDR3). This allows the embedded control‐ler to automatically issue up to 252 cascadedread or write commands and automaticallyincrement addresses based on a single com‐mand from the Core Fabric.

• Backwards‐Compatible

The embedded DDR controllers can supportDDR3 (up to 2133 Mbps), DDR2 (up to 800Mbps) and DDR protocols.

• Bypassable

If the user does not require all 6 DDR control‐lers, any (or all) can be bypassed to leverageuse of the designated I/Os for other purposes.

If the user does not require all 72 bits of thedata bus, unused bits are available for generalpurpose I/O.

• Minimal LUT use

The DDR controllers are embedded, and assuch do not use any of the LUTs in the CoreFabric

LUTs are required to drive the DDR Control‐lers; this driving logic is user‐defined, andminimal in size.

DDR Control logic

Speedster22i HD devices contain six embedded (HardIP) DDR Controller instances. Each instance iscomprised of a DDR1/2/3 Controller and a DDR1/2/3PHY, and is controlled using dedicated DDR Corelogic.

The DDR3 Controller IP interfaces are illustrated in theFigure 18.

Figure 18: The Embedded DDR 1/2/3 Controller

Read/WriteShared Interface

Write Interface

Read Interface

General MemoryControl Interface

Manual RefreshControl Interface

ControlInterface

DDR Driver Logic DDR Control LogicDDR

Memory(off-chip)l_busy_align

l_busyl_addr[33:0]l_b_size[7:0]l_w_reql_d_reql_d_req_earlyl_d_req_alignl_d_req_early_alignl_data_in[287:0]l_dm_in[17:0]l_r_reql_data_out[287:0]l_r_validl_r_valid_earlyl_r_valid_alignl_r_valid_early_alignl_auto_pchl_self_refresh[1:0]l_power_down[1:0]l_ref_reql_zq_cal_req[1:0]l_ref_ackl_zq_cal_ackInit_ackInit_wlvl_done

reset_ddr_nreset_n

clk_ddrACX_PLL

ACX

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R Co

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DD

R PH

Y

sd_clk_out[2:0]

sd_clk_out_n[2:0]

sd_reset_n

sd_cas_n

sd_ras_n

sd_we_n

sd_a[15:0]

sd_ba[2:0]

sd_cs_n[1:0]

sd_odt[1:0]

sd_cke[1:0]

sd_dq[71:0]

sd_dqs[8:0]

sd_dqs_n[8:0]

sd_dm[8:0]

sd_dummy[8:0](NC)

sd_pad(NC)

D100011 v1.0


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The embedded DDR1/2/3 controller performs thefollowing:

• All required initialization sequences such as theprogramming of AL and CL values based on user‐defined parameters

• All required calibration algorithms including writelevelization

• DQS Enable (to control read‐write turnaround ofDQ/DQS bi‐directional busses)

• DQS Delay (to skew the DQS by 90 degrees rela‐tive to the corresponding DQ, such that the lattercan be sampled in the middle of the bit transition)

• Translation of READ and WRITE requests receivedfrom the DDR driver into DDR protocol i.e. RAS,CAS and WE.

• Translation between SDR and DDR

• Maintains integrity of memory contents by issuingperiodic auto‐refresh and zqcal commands

• Manages the activating and pre‐charging of mem‐ory banks and rows, as required.

• Manages the driving of the memory address pins(with column or row information, as well as A10function (precharge‐all, auto‐precharge, etc).

• Provides a data request signal (‘l_d_req’) to theDDR driver logic, some number of cycles after acorresponding write transaction request isreceived. This ensures that CAS latency, additivelatency and burst length are all managed internallyto the ACX DDR controller. It also provides earlydata request signal (‘l_d_req_early’) which can beused if more time is required to generate data.

• Provides data request signal (‘l_d_req_align’) andearly data request signal (‘l_d_req_early_align’) if2x mode is selected for 2133Mbps.

• Providing a read data valid signal (‘l_r_valid’) toaccompany read data in response to a read request.This ensures that the round‐trip latency to (andthrough) the memory is managed internally to theACX DDR controller. It also provides early datavalid signal (‘l_r_valid_early’) which can be usedto latch read data.

• Provides data request signal (‘l_r_valid_align’) andearly data valid signal (‘l_r_valid_early_align’) if2X Clock mode is selected for 2133Mbps.

• Provides signal (‘l_busy’) to DDR Driver logic toindicate that the DDR3 Controller is busy and isnot acceptiong new requests.


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PCI Express

The Speedster22i PCI Express hard IP core implementsall three layers (Physical, Data Link, and Transaction)defined by the PCI Express standard.

Key features

• PCI Express Base Specification Revision 3.0 version0.9 compliant; backward compatible with PCIExpress 2.1/2.0/1.1/1.0a

• x1, x4 or x8 PCI Express Lanes

• 8.0GT/s, 5.0 GT/s,and 2.5 GT/s line rate support

• Operates as Endpoint only

• PIPE‐Compatible PHY interface for easy connec‐tion to PIPE PHY

• Support for Autonomous and Software‐ControlledEqualization

• Flexible Equalization methods (Algorithm, Preset,User‐Table)

• Transaction Layer Bypass option

• Selectable Data Widths

32‐bit (x1, x4)

64‐bit (x2, x8)

128‐bit (x4, x8)

256‐bit (x8,)

• Complete error‐handling support

• Flexible core options allow for design complex‐ity/feature tradeoffs:

AER (Advanced Error Reporting Capability)

ECRC (End‐End CRC)

MSI‐X and Multi‐Vector MSI

• Supports Lane Reversal

• Implements Type 0 Configuration Registers inEndpoint Mode

The PCI Express 3.0 Core implements all three layersdefined by the PCI Express Specification: Transaction,Data Link, and Physical.

User‐side interfaces include a Transmit Interface(VC0_TX), a Receive Interface (VC0_RX), aManagement Interface (MGMT), a Message Interface

(MSG), and a Configuration Register ExpansionInterface (CFG_EXP).

The Transmit and Receive Interfaces are intuitivepacket‐based interfaces that are used to transfer databetween the PCI Express 3.0 Core and the user’sapplication logic.

Figure 19: PCI Express Block Diagram

PCI Express Core

TXPHYLayer

TXDataLink

Layer

TXTrans.Layer

RXPHYLayer

RXDataLink

Layer

RXTrans.Layer

PH

Y(I

nteg

rate

dor

Dis

cret

e)

PH

Y In

terfa

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CLK, Configuration, AndManagement

ConfigurationRegisters

Serial TX

Serial RX

PHYTX

PHYRX

Status/ErrorInfo

VC0_TX

VC0_RX

MSG

MGMT

CFG_EXP

PC

I Exp

ress

(×1

, ×4,

or

×8)

Loca

l Int

erfa

ce

D100012 v1.0


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The Table below shows the internal interfacewidth/speed options available with the EmbeddedPCIe Controllers.

In addition, there is an Achronix provided shim for useto widen the bus for a lower bus speed.

Table 7: PCI Express core interface width and speed

Standard PCIE width Internal data width and Speed

PCIe 3.x (8GT/s per lane)

x8256bit at 250 MHz

128 bits at 500 MHz

x4128 bits at 250 MHz

64 bits at 500 MHz

x1 32 bits at 250 MHz

PCIe 2.x (5GT/s per lane)

x8

256bit at 125 MHz

128 bits at 250 MHz

64 bits at 500 MHz

x4

128 bits at 125 MHz

64 bits at 250 MHz

32 bits at 500 MHz

x1 32 bits at 125 MHz

PCIe 1.x (2.5GT/s per lane)

x8

256bit at 62.5 MHz

128 bits at 125 MHz

64 bits at 250 MHz

x4

128 bits at 62.5 MHz

64 bits at 125 MHz

32 bits at250 MHz

x1 32 bits at 62.5 MHz


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10/40/100G Ethernet MAC

The 10 / 40 / 100 Gigabit Ethernet MAC and PCS Coreis designed to comply with the IEEE P802.3ba Speci‐fication Draft 2.2. The Core can be used in either NIC(Network Interface Card) or Ethernet Switchingapplications. A set of configuration registers isavailable to dynamically set the Core to terminate andform MAC frames (NIC application) or to pass MACframes without modification to the User application orto the Ethernet line (Switching application). Whenused in NIC or Switching applications, the Coreprovides support for IEEE managed objects, IETF MIB‐II and RMON for management applications (e.g.SNMP).

The Channelized MAC and PCS Core can beconfigured to support either one of the following 5configurations:

• 1‐12 x 10 Gigabit Ethernet Channels

• 1 x 100 Gigabit, 1‐2 x 10 Gigabit Ethernet Channels

• 1‐3 x 40 Gigabit Ethernet Channels

• 1‐4 x 10 Gigabit, 1‐2 x 40 Gigabit Ethernet Channels

• 1‐8 x 10 Gigabit, 1 x 40 Gigabit Ethernet Channels

Figure 20 shows a high level block diagram of the10/40/100G Ethernet core and its main interfaces.

FIFO Interface

The 10 / 40 / 100 Gigabit Ethernet MAC and PCS Coreimplements a flexible FIFO interface that is connectedto the internal FPGA fabric. This interface isdecoupled, and therefore asynchronous to the Ethernetcore. The transmit and receive FIFOs are alsodecoupled and therefore can operate at completelyunrelated frequencies.

In order to allow for the start of frame to always bealigned on lane 0, the transmit and receive interfaceclocks have to run faster than the nominal required

clock frequency (100Gbps/384b = 260.42 MHz). In 100Gmode of operation, worst case are 97‐byte packets,which consume only 117 bytes (97‐byte packet + 8‐bytepreamble + 12‐byte IPG) on the Ethernet line, butrequire 3 x 48‐byte words in the FIFO. Therefore theminimum required transmit and receive interface clockspeed is 144/117 x 260.42 MHz = 320.51 MHz.

All transfers to/from the user application are handledindependently of the Core operation, and the Coreprovides a simple interface to user applications basedon a credit scheme. Figure 21 shows the 10/40/100GEthernet core FIFO interface.

Figure 20: The Embedded10/40/100G Ethernet Controller

MAC PCS

ChannelizedTx MAC

ChannelizedRx MAC

ChannelizedTx PCS

ChannelizedRx PCS

Configuration/control/statisticsMDIOMaster

Tran

smitt

er F

IFO

Inte

rface

Rec

eive

FIF

OIn

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Register Interface PriorityFlow Control

Statistic CounterTriggers

Pm

at T

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mit

Inte

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Pm

a R

ecei

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HY

Man

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D100017 V1.0


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Figure 21: The Embedded10/40/100G Ethernet FIFO Interface

MACTx

RS

MACRx

RS

App

licat

ion

Inte

rfac

e FI

FO

384+64

384+64

66 66 20Buffer Gearbox



66 66 20Buffer GearboxGT

PMA/PCS

PMA_clk

PMA

Ref_clk

MLDReference Clock(min. 650 MHz)

MAC/RS/PCS

PCS MLD

66 66 20Block Sync GearboxDeskew Buf




PCS

MLD

FIFO Clock(min. 320.51 MHz)

515.625 MHzrecovered clocks

D100018 v1.0


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Interlaken

Interlaken is a scalable chip‐to‐chip interconnectprotocol designed to enable transmission speeds from10Gbps to 100Gbps and beyond. Using the latestSerDes technology and a flexible protocol layer,Interlaken minimizes the pin and power overhead ofchip‐to‐chip interconnect and provides a scalablesolution that can be used throughout an entire system.

In addition, Interlaken uses two levels of CRC checkingand a self‐synchronizing data scrambler to ensure dataintegrity and link robustness.

Speedster22i devices include a high‐performance, low‐power and flexible implementation of the InterlakenProtocol. The core is compliant with the InterlakenProtocol Definition, Revision 1.1, and offers a fast,turnkey Interlaken interface for chip‐to‐chipinterconnect.

One of the benefits of Interlaken is its scalability andflexibility to accommodate different system designs.

Features

The Interlaken core has the following features:

• Support for any serial data rate up to 12.75Gbps

• Up to 12 lanes wide per controller. (some deviceshave multiple controllers which can be combinedto provide up to 24 lanes)

• Data striping and de‐striping across 1 to 12 lanes

• Programmable BurstMax, BurstShort andMetaFrameSize parameters

• 64/67 encoding and decoding

• Automatic word and lane alignment

• Self‐synchronizing data scrambler

• Data bus width of 512 bits

• CRC24 generation and checking for burst dataintegrity

• CRC32 generation and checking for lane dataintegrity

• Data scrambling and disparity tracking to mini‐mize baseline wander and maintain DC balance

• Support for all Synchronization, Scrambler State,Diagnostic, and Skip Word Block Types

• Programmable Rate Limiting circuitry

• Robust error condition detection and recovery

• Channel‐level and link‐level flow control mecha‐nism

• Support for 256 different logical channels

• Segment‐mode and Packet‐mode transmission for‐mat

• Segment‐mode and Packet‐mode receive format

• BurstMax size can be programmed up to 256 bytes

• Support for BurstShort requirement of 32 bytes

• In‐band flow control

• Support for link‐level flow control

• Flow control mechanism supports stopping pack‐ets in mid‐stream – head of line blocking

• Rate matching with granularity of 1 Gbps

• Meta Frame Length programmable between 128 to8K words

• Support for status messaging

• Lane decommissioning and resiliency

The block diagram of the Interlaken core is shown inFigure 22:

Figure 22: Interlaken Block Diagram

PCS / LLC

20 bits

512 bits @ 470 MHz

10 GbpsSerDes

SerDes

SerDes

20 bits

20 bits

10 Gbps

10 Gbps

512 bits @ 470 MHz

D100001 v1.0


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DMA Engine

Direct Memory Access (DMA) is the process ofcopying large amounts of data efficiently between twodevices (typically the host ‘system’ memory and a busdevice, or ‘card’) with minimal host processorinvolvement.

DMA requires a dedicated hardware resource – a DMAEngine – to do the memory copy. The DMA Engine’sjob is to do the copy operation specified by software.When using a DMA Engine, the software only needs toimplement the control function of the copy (tell theDMA Engine where to copy from and to, etc.) ratherthan having to actually move the data itself to performthe copy.

There are two primary advantages of using DMA

• A DMA Engine is much better at copying memorythan software; DMA Engines can issue large bursttransactions (as large as the underlying hardwareprotocol allows) while the processor typically isonly capable of very small burst transactions; theprotocol efficiency, which is the ratio ofpayload_transferred / (payload_transferred +hardware_protocol_overhead), is typicallyextremely poor with the small payload size usedby the processor and very good with the largerpayload size used by a DMA Engine; a DMA

Engine may produce 10 to 100 times greaterthroughput than a non‐DMA software copy

• Software offloads the time‐consuming copy task tothe DMA Engine and thus frees the processor forother tasks for which software is better suited. Thecopy operation is a repetitive task requiring onlysimple decisions and is well suited for hardwareacceleration via DMA. Processor resources are bet‐ter utilized on tasks which software is better suitedfor such as running the user’s applications andprocessing (converting, parsing, displaying, etc.)the DMA data.

Features

The Hard IP DMA Engine included in Speedster22idevices is directly attached to the PCI expressController and thus to a host system. (as the PCIe Coreis typically a Slave, not Master). The DMA Engine usesthe ARM AXI bus standard for connecting with thelocal ‘card’ memory (DDR1/2/3) or any other FPGAresources that will be part of a DMA transaction.(Ethernet, Interlaken etc)

The DMA Engine block diagram is shown below inFigure 23.

Figure 23: DMA Engine Block Diagram

D100001 v1.0

DMA PCIe Interface

AXI Target Interface

AXI DMA C2S InterfaceAXI DMA C2S Interface

AXI DMA C2S InterfaceAXI DMA S2C Interface

AXI3/4 Master

AXI3/4 Master or AXI4-Stream Slave

AXI3/4 Master or AXI4-Stream Master

PCI Express Core Interface


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The DMA Engine consists of 3 main blocks

• AXI Target interface. Used when the SystemHost/Master is outside of the Speedster22i FPGAand the Host connects to the FPGA using PCIe. Inthis case the PCIe is acting as a slave and the DMAEngine translates accesses received via the PCIe toan AXI master, which can in turn access other AXIslaves within the FPGA.

• AXI DMA C2S. This is the engine that controlsCard to System (C2S) transfers, i.e. data flow fromthe user logic in the FPGA fabric, to the PCIe RootComplex via the FPGAs embedded PCIe endpointcontroller

• AXI DMA S2C. This is the engine that controls Sys‐tem to Card (S2C) transfers, i.e. the data flow fromthe PCIe Root complex to the User logic in theFPGA

The internal interfaces of the DMA block are fullycompliant with the ARM AXI 3 and AXI 4 speci‐fications. Bus Bridges to translate AXI transactions to the nativeformat of the other Speedster22i Hard IP are availablefrom Achronix. This allows a system designer toconnect all Hard IP using the AXI bus protocol,simplifying the IP interconnection process.


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Configuration Interface Speedster22i HD FPGA Family

Configuration InterfaceThe embedded programming and configuration logic is designed to support a variety of programming options.Figure 24 outlines the basic block diagram of the programming and configuration logic, including additional logicto implement security features. The configuration management unit controls the startup and shutdown sequencefrom configuration mode to the user mode and back. The configuration management unit includes the provisionsfor configuring the device with a secure bitstream using a 256‐bit Advanced Encryption Standard (AES) algorithmin Cipher Block Chaining (CBC) mode. The device contains a small non‐volatile memory for the storage of therequired AES key.

Supported Programming and Configuration Modes

Several programming and configuration modes areused to support FPGA development and deploymentphases. To avoid confusion, the term programmingrefers to the action of writing a bitstream to flash, sothat on the next power‐on cycle, the newly writtenbitstream can be used to configure the FPGA. The termconfiguration refers to the process of configuring theFPGA to implement the required user functionality.

Note: The recommended memory space to store the configuration data for the Speedster22iHD is 32 MB.

The supported programming modes are:

• Serial flash (SPI) programming (SFP)

The supported configuration modes are:

• JTAG FPGA configuration (JFC)

• Serial flash (SPI) FPGA configuration (SFC)

• External CPU FPGA configuration (EFC)

• Multiple Serial Flash (SPI) interfaces (MSF)

Note: All flash modes listed are master (where an external clock is routed to the flash memory from the FPGA, controlling the configuration timing).

A simplified diagram showing the supportedconfiguration modes is shown in Figure 25, page 29.

JTAG FPGA Configuration (JFC)

The JFC mode allows the FPGA to be configureddirectly via a JTAG download cable. This mode is usedduring user‐logic development and testing cycles.

Serial Flash Configuration (SFC)

The SFC mode allows serial flash PROMs to be used toconfigure the FPGA. In this mode the FPGA is themaster, and therefore supplies the clock to the PROM.

Figure 24: Configuration Logic Overview

Configuration Logic

FPGA

User Logic

JTAGUSB JTAG CableJTAG

Interface

External CPU CPU SlaveController

Serial (SPI)Flash

SPI FlashController

SerialData

ds001_25_v03

• •FPGA

ConfigurationManagement

Unit

SRAM ScanChain

AESDecode

AES NVKey

Storage

Mode and Status Pins


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Speedster22i HD FPGA Family Configuration Interface

External CPU FPGA Configuration (EFC)

The EFC mode configures the FPGA from an externalCPU after a system power‐up cycle. This mode can beused both during user‐logic development as well as ina production environment.

Multiple Serial Flash (SPI) Interfaces (MSF)

To reduce programming timing without adding thecomplexity of a parallel flash controller, a parallel arrayof four SPI flash devices can be used. A by‐four arrayreduces the data‐loading time to approximately 150 ms.

Figure 25: Simplified Configuration Diagram

Configuration Logic

FPGA

User LogicJTAGUSB JTAG Cable

JTAGInterface

Serial (SPI)Flash

SPI FlashController

SerialData

ConfigurationManager

ds001_26_v04

External CPU CPU SlaveController


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Configuration Interface Speedster22i HD FPGA Family

Configuration Pin Descriptions

Table 8 below describes the FPGA pins used for the various supported configuration modes. Dedicated pinsbetween modes can be shared (Serial Flash by 1, Serial Flash by 4, CPU modes) since the function is determined bythe static state selected by the CONFIG_MODESEL[2:0] inputs. Figure 26 through Figure 29, page 31 illustrateeach of the supported configuration interfaces.

Table 8: Pins Used for Support Configuration Modes

External Pin Name EFC SFC MSF JFC

SDI DQ[0] Serial data output to flash memory –

SDO[3] DQ[1] – Input of configu-ration data from flash –



SDO[0] DQ[4] Input of configuration data from flash –

HOLDN DQ[5] Hold output to flash –

CSN[3] DQ[6] – Active-low chip select –

CSN[2] DQ[7] – Active-low chip select –

CSN[1] Unused – Active-low chip select –

CSN[0] Active-low chip select –

CPU_CLK CPU clock – – –

CONFIG_RSTN Active-low configuration reset

CONFIG_DONE Open-drain configuration done output

CONFIG_STATUS Open-drain SRAM initialization complete output

CONFIG_MODESEL[2:0] Configuration mode select; must be ‘100’

Configuration mode select; must be ‘001’

Configuration mode select; must be ‘010’

Configuration mode select; Don't care

CONFIG_SYSCLK_BYPASSBypass configuration system clock. Don't-care

Bypass configuration system clock. Set to ‘0’ Bypass configuration system clock; Don't care

CONFIG_CLKSEL Selects configuration clock. set to ‘0’ Don’t care

Figure 26: JTAG Configuration Interface

JTAGController

TCK TCK

TMS TMS

TRSTN TRSTN

TDI TDI

TDO TDO

SpeedsterFPGA

ds001_27_v02

Figure 27: SPI Flash PROM Configuration Interface

SPIFlash

SCLK SCK

HOLDN HOLDN

DI SDI

CSN CSN[0]

DO SDO[0]

SpeedsterFPGA

ds001_28_v02


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Speedster22i HD FPGA Family Configuration Interface

Figure 30, page 31 shows a simplified block diagram of FPGA configuration control logic. Regardless of the configu‐ration control settings, if the programming hardware is connected to JTAG pins driving the FCU, the configu‐ration clock (CFG_CLK) is automatically driven by TCK. In single or multiple flash configuration mode, if not overridden by JTAG circuitry, users can select between internally generated (SYSCLK) or externally driven configuration clock (CPU_CLK) using CONFIG_SYSCLK_BYPASS pin.

Figure 28: Slave CPU Configuration Interface

CPU CPU_CLK CPU_CLK

CSN[0]

CSN[2]

CSN

DATA[7]

SpeedsterFPGA

ds001_29_v03

CSN[3]DATA[6]

HOLDNDATA[5]

SDO[0]DATA[4]

SDO[1]DATA[3]

SDO[2]DATA[2]

SDO[3]DATA[1]

SDIDATA[0]

Figure 29: By-Four SPI Flash Programming

SPIFlash

SCLK

HOLDN

DI

CSN

DO

SPIFlash

SCLK

HOLDN

DI

CSN

DO

SPIFlash

SCLK

HOLDN

DI

CSN

DO

SPIFlash

SCLK

HOLDN

DI

CSN

DO

SCK

HOLDN

SDI

SpeedsterFPGA

CSN[0]

SDO[0]

CSN[1]

SDO[1]

CSN[2]

SDO[2]

CSN[3]

SDO[3]

ds001_30_v02

Figure 30: FPGA Configuration Logic (Simplified View)

ds001_42_v01

CPU_CLK

SYSCLK

CONFIG_SYSCLK_BYPASS

CONFIG_CLKSELJTAG_CLKSEL

(from Interal FCU)

TCKCFG_CLK

1

0

1

0

1

0

3'b100

CONFIG_MODESEL[2]

CONFIG_MODESEL[1]

CONFIG_MODESEL[0]


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12.75 Gbps SerDes Speedster22i HD FPGA Family

12.75 Gbps SerDesOverview

All members of the Speedster22i family includeembedded SerDes, which can be used to implementprotocols running at between 1.0625 Gbps and 12.75Gbps per lane. Each SerDes can be used for:

• Chip‐to‐chip signaling

• Backplane signaling

• Line signaling (coax, twisted pair, etc.)

As clocking is typically embedded in the data, theSerDes receiver must extract the clock from the datastream. This activity is referred to as clock and datarecovery (CDR). For signaling across a backplane (or

other impaired medium) at about 5 Gbps or greater, acombination of transmit equalization and decisionfeedback equalization (DFE) is most likely required.

Block diagrams of the transmit and receive sectionsrespectively are shown in Figure 31 and Figure 32.

As shown in Figure 17 below, the traismit datapathconsists of both the Physical Media Access (PMA) andthe Physical Coding Sublayer (PCS). The PMA handlesthe low level data signaling, functions, while the PCShandles the interface to protocol controllers as well asany data encoding which may be required.

Figure 31: 12.75G SerDes – Transmit Section

Figure 32: 12.75G SerDes – Receive Section

PCS Features PMA Features

From Fabric(8/10/16/20 Bit)

Line-Rate Clock(From PLL)

FabricBoundaryInterface

Encoding8B/10B

64B/66B64B/67B

128B/130B

Parallel toSerial

Conversion

Pre-Emphasisand Multi-TapFeed-ForwardEqualization

OOBSignaling

andPowerdown

Conrol

DifferentialSignal

ds001_20_v04

WordAlignment

PCS Features

PMA Features

DifferentialSignal

Decoding8B/10B

64B/66B64B/67B

128B/130B

DeskewElastic Buffer

Line-Rate Clock(From PLL)

Serialto

ParallelConversion

Clock/DataRecovery

andDecisionFeedback

Equalization

OOBSignaling

andPowerdown

Conrol

ds001_21_v02

PCS Features

To Fabric(8/10/16/20 Bit)

Bit-Slider

FabricBoundaryInterface


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Speedster22i HD FPGA Family 12.75 Gbps SerDes

PMA Features

The PMA has the following feature set:

• Operating bitrate of 1.0625Gbps ‐ 12.75 Gbps per

lane

• DC coupling or external AC coupling

• Lock to reference clock or lock to data

• Data oversampling for capture of un‐encoded as

well as slower speed traffic

• DFE support for high‐speed operation over lossy

channels

• Auto‐calibration of DFE

• Rx scope function: Measurements of data‐eye

(width and height) and BER

• Tx de‐emphasis support

• Tx PLL for every serdes lane providing maximum

bitrate flexibility

• Locking of Tx serdes on same side of device to

common clock

• Built‐in self‐test (BIST) including near/far endloopback and prbs 7, 23 & 31 generation/checking

PCS Features

The PCS supports the following functions:

• Support for 8B/10B, 64B/66B, 64B/67B and

128B/130B encoding & decoding

• Symbol alignment

• Clock compensation

• Lane‐to‐Lane de‐skew

• Manual bit‐wise de‐skew

• Near and far end loopback

• Clocking and reset for interface to programmable

fabric

Control Plain Features

• Programmable interface for status monitoring anddynamic configuring of serdes operation

Transmit Datapath

On the transmit data path the PCS block receives 8/10or 16/20 bits of data per lane from the fabric and

delivers it to the PMA layer. The encoder can be in thepath or can be bypassed. If the encoder is used, theinterface to the fabric will be 8 or 16‐bits wide (with 1or 2 extra bits for the encoder to distinguish betweencontrol (K) and data (D) characters) and the interface tothe PMA will be 10 or 20‐bits wide. If the encoder isbypassed, the data width from the fabric to the PMAwill be identical.

The transmit data path consists of the followingfunctions:

• Polarity and bit reversal

• 8b/10b encoder

• 64b/66b encoder

• 64b/67b encoder

• 128b/130b encoder

• 66/16 gearbox (combined with 64/66 encoder‐ bothmodules are not separately accessible)

Polarity and bit reversal

This function can be used to optionally change thepolarity or bit‐ordering of the transmit data. There are2 instances of the polarity and bit reversal function thatcan be independently controlled.

Encoders

The encoder generates a encoded words from un‐encoded data at the PCS input. The encoders cansupport a single 8 bit or a double 16 bit word, with theencoders cascaded for the 16 bit case. The encoderoutput is passed to the PMA for serialization.

8b/10b encoder

The 8b/10b encoder function includes extra logic tofully support Gigabit Ethernet, XAUI and PCIe (gen1,gen2) protocols.

64b/66b encoder

The 64b/66b encoder function includes extra logic tofully support 10/40/100 GbE and other >=10Gbpsprotocols.

64b/67b encoder

The 64b/67b encoder function supports Interlaken.

128b/130b encoder

The 128b/130b encoder is specifically to support thePCIe gen3 protocol. The function will be compliant tothe PIPE specification from Intel Corp and will


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interoperate with the PCIe embedded IP to providegen3 support.

Other protocols that require a generic 8b/10b or128b/130b encoder can also make use of this functionalblock.

BIST pattern generation

The transmit datapath will include pattern generationlogic to be used in test mode for built‐in self test. Thepatterns supported are :

PRBS 7, 15, 20, 31

User defined pattern (up to 40‐bits that will berepeated continuously).

Receive Datapath

On the receive datapath the PCS receives 8/10/16/20‐bitdata from the PMA (except in the over‐sampling CDRmode which can perform 4x or 8x over‐sampling) andtransfers 8/10/16/20‐bits of data to the fabric interface.When the 8b/10b decoder is enabled the receivedatapath gets 10/20‐bits of data from the PMA andtransfers 8/16‐bits of data to the fabric (along with 1‐2control bits). If the 8b/10b decoder is not enabled thedatapath width to the fabric is identical to the datapathwidth to the PMA (except in the over‐sampling CDRmode).

A byte level de‐serializer can be implemented at thefabric interface to convert 16/20‐bit data to 32/40‐bitdata (to relax clock timing at the interface).

The receive datapath consists of the followingfunctions:

• Phase picking logic

• Polarity and bit reversal

• Symbol alignment

• 128b/130b block synchronization and decode

• Lane to lane de‐skew (up to 12 channels)

• Clock compensation

• 8b/10b decoder

• Transition density checker

• Bit slider

• Symbol‐slip mode allows data to be advanced ordelayed by 1 cycle in addition to general incrementof 1 cycle

Phase picking logic (PPL)

The phase picking logic, “PPL”, function is meant to beused in conjunction with the CDR over‐sampling modeof operation in the PMA. The PPL block accepts the

oversampled data from the PMA and implements analgorithm to extract the receive data bits. The PPLblock also provides feedback on the phase change rateto the PMA. This can be used to account for anyfrequency offset between the receive data on the lineand the over‐sampling clock. The following config‐urations are supported for over‐sampling.

• 4x over‐sampling, up to 6.25 Gbps

• 8x over‐sampling, up to 3.125 Gbps

Polarity and bit reversal

There will be 2 independently configurable polarityand bit reversal blocks in the receive datapath. Therewill also be an option to invert the Rx data from thePMA dynamically.

Symbol alignment

The parallel data output from the serdes PMA needs tobe aligned to byte boundaries before it can be used bydownstream logic. The transmit side typically sendsunique symbols that can be used for alignment. Thesymbol alignment block looks for these symbols andsets the byte boundary. The symbol alignment blocksupports alignment to 2 different symbols and can alsodetect a 4‐symbol sequence match.

• Manual mode

Aligns to a pre‐defined symbol for eachrequest from the fabric.

• Bit slip mode

Slips 1‐bit of data for each request from thefabric.

• Automatic alignment

Configurable state machine to automaticallyalign to a pre‐defined symbol, including op‐tional hysteresis to determine loss of align‐ment.

128b/130b decode

The 128b / 130b decode block is to support PCIe gen3protocol. It will be compliant to the PIPE specificationfrom Intel Corp.

Lane to lane de-skew

The PCS includes support for lane to lane de‐skewacross the serdes lanes on one side of the chip (up to 12lanes). De‐skew across lanes on different sides of thechip is not supported. The de‐skew function supportsup to 2 different de‐skew patterns (up to 5‐symbolslong each). The de‐skew function supports thefollowing modes:

• Automatic de‐skew


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• Manual de‐skew

• Symbol slip

Data in a given lane is advanced or delayed by1‐2 cycles.

Clock compensation

The receive data from the PMA is timed to therecovered clock that is output from the CDR (except inCDR over‐sampling mode). Some protocols need thisdata to be synchronized to an internal system clock(typically same as the transmit clock). The clockcompensation function uses an elastic buffer tocompensate for any frequency offset between therecovered clock and the internal system clock. Thisfunction uses a configurable skip or pad symbol thatcan be dropped or added at specific instances in thereceive data stream to compensate for any frequencyoff‐set.

8b/10b decoder

The 8B/10B decoder generates 8‐bit code groups and 1‐bit control from 10‐bit encoded data. It uses the codegroup mapping specified in IEEE 802.3 clause 36. If thefabric interface is 16‐bit data path, then 2 8B/10Bdecoders are cascaded to produce a 16‐bit width to thefabric.

The 8b/10b decoder includes error indication logic toprovide status of code word or running disparityerrors to downstream logic.

Bit slider

The bit slider is an 80‐bit barrel shifter that can be usedto control bit‐wise alignment from the fabric. Thisfeature can be used to implement any user specificalgorithm for bit‐level alignment or de‐skew acrossmultiple lanes. It can be used in conjunction with thesymbol slip mode of the de‐skew function to achieve awide range of de‐skew. If used stand alone thisfunction can provide up to 30 UI of de‐skew.

Transition density checker

This function monitors the Rx parallel data from thePMA and keeps track of consecutive 0s or 1s. If thenumber of consecutive 0s or 1s exceeds a pre‐configured threshold it sends a status indication to thedownstream logic.

Control plane interface

The PCS and PMA blocks have a parallel bus controlplane interface to allow user logic to configure the datapath and also to monitor the status of key blocks. Thecontrol plane interface is based on a simple request,acknowledge handshake protocol with an 8‐bit databus read, write data bus and 16‐bit address bus. Tominimize pin usage on the fabric side, a serializedversion of the control plane interface is supported foraccess from the fabric. A serial to parallel converter,parallel to serial converter is implemented in the LogicCore to interface the fabric to the PMA and PCS controlplane. Each serdes lane has its own control planeinterface.


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Support for Standard Protocols

Table 9 shows which standard protocols are supported. Any listed PCS feature can be bypassed if not needed.

Table 9: 12.75Gbps SerDes Supported Standards

Standard

General PCS PMA

Num

ber of Lanes

Gbps

(Per Lane)

Internal Bus Width

(Per Lane)

Coding

Word A

lignment

Lane Alignm

ent

Elastic Buffer

Spread Spectrum Clocking

Power-D

own

States

OO

B Signaling

PCIe 1.1 1 / 4 / 8 2.5 8 / 16 8B / 10B K28.5

PCIe 2.0 1 / 4 / 8 2.5 / 5.0 16 8B / 10B K28.5

PCIe 3.0 1 / 4 / 8 2.5 / 5.0 /8.0

16 128B / 130B

K28.5

SRIO 1 / 4 / 8 1.25/2.5/3.125/6.25

16 8B / 10B K28.5

Gigabit Ethernet 1 1.25 8 8B / 10B K28.5

10 Gigabit Ethernet (XAUI)

4 3.125 8 8B / 10B K28.5

10 Gigabit Ethernet (XFI)

1 10.3125 8 64B /66B

sync header

40 Gigabit Ethernet (XLAUI)

4 10.3125 8 64B /66B

sync header

100 Gigabit Ethernet (CAUI)

4 10.3125 8 64B /66B

sync header

SGMII 1 1.25 8 8B / 10B K28.5

Fibre Channel – 1 1 1.0625 8 8B / 10B K28.5



SATA Gen 1 1 1.5 10 8B / 10B K28.5

SATA Gen 2 1 3 10 8B / 10B K28.5

SATA Gen 3 1 6 10 8B / 10B K28.5

SAS 1 1.5 / 3.0 / 6.0

10 8B / 10B K28.5

Interlaken 6, 8, 10, 12, 24

4.6 – 12.75

20 64B / 67B

sync header (2)

CEI6 – SR 1 4.976 – 6.375

16

CEI6 – LR 1 4.976 – 6.375

16

CEI11 – SR 1 9.95 – 11.1

16

SPI–5 19 3.125 8 (2) (2)

SFI–5.1 (3) 19 2.488 – 3.125

8 (2) (2)


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SFI–5.2 (3) 19 9.95 - 11.1

8 (2) (2)

SFI–S (3) 19 9.95 - 11.1

8 (2) (2)

Infiniband 1 2.5 / 5.0 / 10.0

8 (2) (2)

OC48(1) 1 2.488 8 (2)

GPON 1 1.25 / 5.0 / 10.0

8 (2)

EPON 1 1.25 / 5.0 / 10.0

8 (2)

CPRI 1 1.228 / 2,456 . 3.072 / 6.144

8

(2)

OBSAI 1 1.536 / 2.456 / 6.144

8 (2)

Backplane Inter-connect (with DFE)

1–20 1.25 – 12.75 8/16

Notes: 1. Not supported by integrated PCS block (must be implemented in fabric).

2. Optional.

3. Bit slider is available for SFI Protocols

Table 9: 12.75Gbps SerDes Supported Standards (Continued)

Standard

General PCS PMA

Num

ber of Lanes

Gbps

(Per Lane)

Internal Bus Width

(Per Lane)

Coding

Word A

lignment

Lane Alignm

ent

Elastic Buffer

Spread Spectrum Clocking

Power-D

own

States

OO

B Signaling


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Programmable I/Os Speedster22i HD FPGA Family

Programmable I/OsI/O Types: Summary

Speedster22i device I/Os come in five categories, as shown in Table 10.

Programmable I/Os: Supported Standards

Each programmable I/O can be configured to conform to any of a large number of I/O standards, both single‐endedand differential, as summarized in Table 11, page 39. Each I/O can operate as an input, an output, or a bidirectionalI/O (Figure 33). Of course, a differential signal consumes two I/Os, whereas a single‐ended signal consumes only one.

Table 10: I/O Types

Full Name Description Count

Programmable I/O – Extended Feature

• User programmable• Complies with wide range of I/O standards• Low to medium bit rates• DLLs for input and output delay adjustments as required for

advanced memory and datapath interfaces

12 Nwhere N = byte-lane count (device/package dependent)

SerDes I/O • User programmable• Complies with wide range of SerDes-based standards• High bit rates

18 pins for a block of four SerDes (a Quad) composed of 16 data pins: (4 pins/lane 4 lanes) + 2 reference clock pins (shared by 4 lanes)

Clock I/O These I/O have connectivity to the “Global Clock Generator” in the corresponding corner.

24

Dedicated I/O Reserved for device configuration and test 23

Power / Ground Core power; I/O power; ground Device/package dependent

Figure 33: Programmable I/Os

a) Single-Ended Signaling b) Differential Signaling

Transmit Data

Receive Data

Transmit 3-State Control

I/O Pad Transmit Data

Transmit 3-State Control

Receive Data+

−

I/O Pad

I/O Pad

ds001_16_v05


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Speedster22i HD FPGA Family Programmable I/Os

Table 11: Programmable I/O: Supported Standards

Type Volts Class

Interface Applications and Standards

StandardMax Clock

Rate(MHz)

Max Data Rate

(Mbps)

Sing

le-E

nded

Diff

eren

tial

LVCMOS 1.8V –General Purpose

300 30LVCMOS 1.5V – 300 300LVCMOS 1.2V 300 300HSTL 1.8V Class I

QDR II SRAM / RLDRAM II533 1066

HSTL 1.8V Class II 533 1066HSTL 1.5V Class I

Memory and Switch Fabric533 1066

HSTL 1.5V Class II 533 1066SSTL 1.8V Class I

DDR SDRAM / RLDRAM II400 800

SSTL 1.8V Class II 400 800SSTL 1.5V Class I

DDR2 SDRAM / FCRAM II533 1066

SSTL 1.5V Class IIPOD 1.8V - 400 800POD 1.5V - 400 800LVDS 1.8V – SPI4.2, SFI4.1 800 1600Differential HSTL 1.8V Class I

QDRII SRAM / RLDRAM II533 1066

Differential HSTL 1.8V Class II 533 1066Differential HSTL 1.5V Class I

Memory and Switch Fabric533 1066

Differential HSTL 1.5V Class II 533 1066Differential HSTL 1.2V Class II 533 1066Differential SSTL 1.8V Class II DDR 2 SDRAM 533 1066Differential SSTL 1.5V Class II 800 1600Differential SSTL 1.2V Class II 1066 2133HT 1.0 0.6V – 800 800


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Programmable I/O Grouping: Banks and Byte Lanes

Programmable I/Os are deployed in banks. All I/Oswithin a bank must share:

• The same VDDO

• The same VREF

The same RREFs (used for controlled‐impedance I/Os,

as described in “Programmable I/O Features(Common to All Banks),” on page 23).

The following sections describe Byte‐Lane and I/OBanks

Byte-Lane

I/O Banks consist of Byte‐Lanes. Each byte‐laneconsists of following:

• 12 I/O Buffers consisting of 12 Bit‐Modules. Eachpair of two IO Buffers can be configured as twosingle‐ended IO Buffers or as one differential IOBuffer.

• 1 Master DLL and 12 slave delay elements – Thereis one slave delay element for each of the 12 bit‐modules.

• Appropriate Logical/Physical Structures for DQSpreamble enable & postamble shut‐off forDDR2/DDR3 SDRAM application.

• Write‐pointer and Read‐pointer logic for a Meso‐chronous Synchronizer.

• Muxes and Buffers for Source Synchronous clocknetworks

• 2 I/O Buffers in each byte‐lane are capable ofreceiving clocks from external devices. They can beused as one differential pair (e.g. to receive differ‐ential DQS for DDR2) or two single‐ended buffers(e.g. to receive clock CQ and CQn for QDR2). Theother 10 I/O buffers can be used as Data pins to belatched by the received clocks.

• Logic in each bit‐module to support SDR, DDR &QDR support for the input and output directions,plus output enable logic.

• VREF is integrated in the Byte‐Lane.

I/O Banks

I/O Buffers in Speedster22i have been grouped intomultiple Banks. There are three type of IO Banks – EFBank, Clock Bank and Configuration Bank.

Enhanced Function, “EF”, Bank

An EF bank consists of following:

• 4 byte‐lanes (48 I/Os)

• Common PVT calibration control and calibrationresistors for Driver Impedance

• Common PVT calibration control and calibrationresistors for on‐die parallel termination and on‐diedifferential termination impedance

• All IO buffers use a common I/O Voltage VDDO

• All IO buffers use a common Reference VoltageVREF

There are a total of 20 EF banks. 10 EF banks are on leftside, 10 EF banks are on right side.

Clock Bank

A Clock Bank consists of following:

• 6 IO Buffers for 6 single‐ended clocks or 3 differen‐tial clocks or any combination of single‐ended anddifferential clocks.

• All six IO buffers use a common IO Voltage VDDO

• All six IO buffers use a common Reference VoltageVREF

• Unlike the EF banks, the Clock Bank adds supportfor LVPECL 1.8V input clocks

• Unlike the EF banks, the Clock Bank does not havePVT calibration control.

There are a total of 4 Clock Banks, one in each cornerfor a total of 24 clock input pins. As the name suggestsclock banks are for clock interfaces.

Configuration Bank

The Configuration Bank is a special dedicated IO bankwhich sits on the bottom edge of Speedster22i. IObuffers in this bank are used for JTAG andConfiguration Interfaces. The total number of IObuffers in this bank is 36.

Figure 34 shows a conceptual floorplan of a devicewith ten banks. Clearly, the number of banks variesfrom device to device.

.


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Figure 34: I/O Banks (Bn = Bank #n; CBn = Clock Bank #n; CFG = Dedicated Configuration Bank)

ClockBank 0

EFBank 0

EFBank 1

EFBank 2

EFBank 9

ClockBank 1

ConfigBank

SerDes

SerDes

ClockBank 3

EFBank 19

EFBank 18

EFBank 17

EFBank 10

ClockBank 2

D100013 v1.0


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I/O Bank Resources

Each I/O Buffer has a Bit‐Module associated with it.The Bit‐Module consists of appropriate logic blocks tofacilitate I/O Buffer interface with the FPGA core. Thelogic in a Bit‐Module consist of following blocks.

Receive Data Path

The receive data‐path has structures to interface incomingdata from the IO Buffer to the fabric. The incoming datacan optionally pass through a delay element beforereaching any logic in the data‐path. The bit‐module in thereceive direction supports three modes:

• Combinatorial to the core ‐ In this mode the datacoming from the input buffer is directly forwardedto the FPGA core.

• SDR ‐ In this mode the data coming from the inputbuffer gets registered in the Bit‐Module before get‐ting forwarded to the FPGA core.

• DDR ‐ In this mode DDR data is received, and foreach bit, two‐bit data is forwarded to the Fabric.This mode has two versions:

The two bits are forwarded to the Fabric coreon different clock‐edges

Both bits are forwarded to the Fabric core atthe same clock edge.

Figure 35 below shows the Bit‐Module’s receive data‐path

Transmit Data Path

The transmit data‐path has structures to interface datafrom the fabric to the IO Buffer. The Bit‐Module in thetransmit direction supports three modes:

• Combinatorial ‐ In this mode the data coming fromFPGA core is directly forwarded to the output buf‐fer.

• SDR ‐ In this mode the data coming from FPGAcore gets registered in the Bit‐Module before get‐ting forwarded to the output buffer.

• DDR ‐ In this mode two bits of data coming fromthe fabric gets converted to DDR data before beingforwarded to output buffer.

In each of the above three modes, the transmit data‐pathcan optionally include a delay element.

Figure 35 below shows the Bit‐Module’s transmit data‐path

Figure 35: Recieve Data path

1

01

0

1

0 1

0

1

0

Delay element

SR

DQ

R

+/-

SRDQ

R

+/-

SR

DQ

R

+/-E

SRDQ

R

+/-

clk

Data_b_to_core

Data_a_to_core

D100014 v1.0


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All the Flops shown above can be configured to beeither positive or negative edge triggered. All the flopssupport an asynchronous or a synchronous reset. Theyalso have a common enable. When coming out of resetall the flops can be either set to “1” or reset to “0”.

Output Enable Path

The Output Enable path has the same choices as theTransmit Data‐Path:

• Combinatorial ‐ In this mode the enable comingfrom the FPGA fabric goes directly to the outputbuffer.

• SDR ‐ In this mode the enable coming from theFPGA fabric gets registered in the Bit‐Modulebefore being forwarded to the output buffer.

• DDR ‐ In this mode two bits of enable coming fromFPGA fabric get converted to DDR data beforebeing forwarded to the output buffer.

Figure 37 below shows the Bit‐Module’s OutputEnable data‐path.

All the Flops shown above can be configured to beeither positive or negative edge triggered. All the flopshave an asynchronous reset. When coming out of resetall the flops can be either set to “1” or reset to “0”.

Delay Element

Each Bit‐Module has a Delay Element which can beused in either the receive data‐path or in the transmitdata‐path. The delay of the Delay Element is set atconfiguration or dynamically during operation. When

Figure 36: Transmit Data path

1

0

SR

D Q

R

+/-_core

f1a

SR

D Q

R

+/-E

SR

D Q

R

+/-E

1

0

SR

D Q

R

+/-

f1b

1

0 10

32

Delay element

clk

_core

Figure 37: Output Enable path

1

0

D Q

R

+/-

D100016 v1

Output_enable_a_from_core

D Q

R

+/-E

D Q

R

+/-E

1

0

D Q

R

+/-

1

0 10

32

Delay element

ENB

clk

Output_enable_b_from_core


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using a DLL as a master over the Delay Element, thedelay element will maintain a set delay during PVTvariations. In addition, when using the DLL, the delay

can be adjusted in increments of 1/64 the period of theDLL’s reference clock.

Table 6‐1 below shows the full specifications of thedelay element.

Advanced I/O Logic Resources

The Bit‐Module has additional logic blocks to supportthe phy function of various Memory Interfaces (e.g.DDR2/DDR3 SDRAM, QDR2+ SRAM), NetworkInterfaces (e.g. SPI4.2) and other source synchronousinterfaces.

Mesochronous Synchronizer

The receive data‐path has an 8‐bit FIFO Synchronizerfor mesochronous applications utilizing the WindowMethod for moving data from the “capture clockdomain” over to the core clock domain. Windowmethod is used for DDR data application; this allowsboth positive‐edged and negative‐edged received datato be valid for 4T cycles after capture. This provides thecore a window of 4T to transfer captured data to itsclock‐domain. The synchronizer has a write‐pointer fordata written into the synchronizer, and a read‐pointerfor data to be read out of the synchronizer. The write‐pointer is clocked by the received Clock (e.g. DQS forDDR2, CQ/CQn for QDR2), whereas read‐pointer isclocked by core Clock. In mesochronous mode, thewpb_wr_ptr counter will be incremented with eachpositive edge of DQS, whereas the wpb_rd_ptr willonly be incremented when enabled by the core. Thecore enables this counter such that it samples thecaptured data in the middle of the window.

Phase Aligner

In many source‐synchronous interfaces, bus de‐skew isessential at the I/O for proper recovery of received

data. Data‐bits received across a bus may arrive at theFPGA at different times (called channel‐to‐channelskew). To de‐skew the channels and align the bus onproper word boundary, protocols, such as SPI4.2,typically require the transmitter to send a trainingpattern to the receiver during initialization and/or aftersome interval. Per‐bit skew is a way to effectivelyremove channel‐to‐channel skew and position the for‐warded clock at the center of the data eye for eachchannel. The Receive Data‐Path has a phase‐alignmentcircuit which, when used in conjunction with a trainingpattern and a delay element, can be used to achieve bit‐alignment using per‐bit skew.

Temperature Sensor

There is an on‐chip temperature sensing diode. Theanode and cathode for the internal temperaturesensing diode are connected to two dedicated pins(TEMP_DIODE_P and TEMP_DIODE_N).

In a typical application, the userʹs circuitry can monitorthe temperature and use the result as a decisioncriterion, for example:

• Selectively disabling circuits to reduce powerconsumption.

• Delay enabling selected circuits until a specifiedcondition is reached.

Parameter Value

Reference Clock Frequency Range 165MHz – 1066MHz

Reference Input Duty Range 40% - 60%

Number of outputs per lane 1

Number of lanes per master 12

Slave Delay Adjustment 0% - 100% of Reference Clock Cycle

Output Phase Resolution 8-bits

Output Phase Accuracy +/- 4% of Reference Clock Cycle

Maximum Period Jitter +/- 2% peak-to-peak of Reference Clock Cycle

Maximum Duty Cycle Variation 50% +/- 2% at Reference Clock Cycle

Minimum High Low Slave Pulse width 25% of Reference Clock Cycle

Maximum Lock Time 500 Reference Clock Cycles


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Speedster22i HD FPGA Family DC and Switching Characteristics

DC and Switching CharacteristicsRecommended Operating Conditions

Table 12: Recommended Operating Conditions(1)

Symbol DescriptionCommercial

UnitsMin Typical Max

TJ Junction temperature 85 °C

VDDL Supply voltage for Internal logic fabric 0.9 0.95 1.0 V

VDD_CFG Supply voltage for configuration bank 0.9 0.95 1.0 V

VDD_CFGWL Supply voltage for configuration word line 0.8 0.85 0.9 V

VCC Digital Power 0.9 0.95 1.0 V

VDD_BRAM Supply Voltage for BRAMs 0.95 V

VDDO_B00 Supply Voltage for IO bank 1.2 - 1.8 V


















VDDO_JCFG Supply Voltage for configuration I/O 1.7 1.8 1.9 V

VDDO_CBNE Supply Voltage for IO bank 1.2-1.8 V

VDDO_CBNW Supply Voltage for IO bank 1.2-1.8 V

VDDO_CBSE Supply Voltage for IO bank 1.2-1.8 V

VDDO_CBSW Supply Voltage for IO bank 1.2-1.8 V

VPA_VDD1 SerDes low voltage 0.95 V

VPA_VDD2 SerDes high voltage 1.8 V

VDD_NOM_E Nominal Analog Voltage 1 V

VDD_NOM_W Nominal Analog Voltage 1 V


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DC and Switching Characteristics Speedster22i HD FPGA Family

AVDD_PLL_NE0 Analog Supply Voltage for PLL 1.8 V




AVDD_PLL_NW0 Analog Supply Voltage for PLL 1.8 V




AVDD_PLL_SE0 Analog Supply Voltage for PLL 1.8 V




AVDD_PLL_SW0 Analog Supply Voltage for PLL 1.8 V




VREF_[B00 - B52] Reference Voltage for I/O Receivers [1] V

Notes: 1. 1/2 of corresponding VDDO

Table 12: Recommended Operating Conditions(1)

Symbol DescriptionCommercial

UnitsMin Typical Max


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Speedster22i HD FPGA Family I/O Electrical Specifications

I/O Electrical SpecificationsLVCMOS18

LVCMOS15

Table 13: LVCMOS18 Supply Voltage

Symbol Parameter Min Nom Max Units

VDDO Output supply voltage relative to GND 1.65 1.8 1.95 V

Table 14: LMCMOS18 DC Specifications

Symbol Description ConditionSpecification

UnitsMin Max

VIH Input High Voltage VOUT VOH 0.65 VDDO VDDO + 0.3 V

VIL Input Low Voltage VOUT VOL –0.3 0.35 VDDO V

VOH Output High Voltage

IOH = –4mA VDDO(min) – 0.4 V





VOL Output Low Voltage

IOL = 4mA 0.4 V

IOL = 6mA 0.4 V

IOL = 8mA 0.4 V

IOL = 12mA 0.4 V

IOL = 16mA 0.4 V

Table 15: LVCMOS15 Supply Voltages



Table 16: LVCMOS15 DC Specifications


UnitsMin Max










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I/O Electrical Specifications Speedster22i HD FPGA Family

LVCMOS12


IOL = 4mA 0.4 V

IOL = 6mA 0.4 V

IOL = 8mA 0.4 V

IOL = 12mA 0.4 V

IOL = 16mA 0.4 V

Table 17: LVCMOS12 Supply Voltages



Table 18: LVCMOS15 DC Specifications


UnitsMin Max










IOL = 4mA 0.4 V

IOL = 6mA 0.4 V

IOL = 8mA 0.4 V

IOL = 12mA 0.4 V

IOL = 16mA 0.4 V

Table 16: LVCMOS15 DC Specifications (Continued)


UnitsMin Max


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HSTL18

HSTL15

Table 19: HSTL18 General Specifications

Symbol Description Min Nom Max Units


VREF Output reference voltage 0.8 0.9 1.1 V

VTT(1) Termination voltage for Class I and II outputs VDDO/2 V

Notes: 1. VTT must track VREF of receiving device.

Table 20: HSTL18 DC Specifications


UnitsMin Max

VIH High input voltage(1) Single-ended VREF + 0.1 VDDO + 0.3 V

VIL Low input voltage(1) Single-ended –0.3 VREF – 0.1 V

VOH

High output voltage

Class I buffer IOH = 8 mA VDDO – 0.4 V

Class II buffer IOH = 16 mA VDDO – 0.4 V

VOL

Low output voltage

Class I buffer IOL = –8 mA 0.4 V

Class II buffer IOL = –16 mA 0.4 V

IDD Static Supply current mA

Notes: 1. Input buffer is single‐ended only.

Table 21: HSTL15 General Specifications




VTT(1) Termination voltage for Class I and II outputs VDDO/2 V

Notes: 1. VTT must track VREF of receiving device.


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Table 22: HSTL15 DC Specifications


UnitsMin Max

VIH High input voltage(1) Single-ended VREF + 0.1 VDDO + 0.3 V

VIL Low input voltage(1) Single- ended –0.3 VREF – 0.1 V

VOH

High output voltage

Class I buffer IOH = 8 mA VDDO – 0.4 V

Class II buffer IOH = 16 mA VDDO – 0.4 V

VOL

Low output voltage

Class I buffer IOL = –8 mA 0.4 V

Class II buffer IOL = –16 mA 0.4 V

IOZK Off-state leakage current(2) uA


Notes: 1. Input buffer is single‐ended only.

2. Bus Keeper Enabled


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SSTL18

Table 23: SSTL18 General Specifications




VTT Termination voltage 0.81 0.9 0.99 V

Table 24: SSTL18 DC Specifications

Symbol DescriptionSpecification

UnitsMin Max

VIH(DC) High DC input voltage VREF + 0.125 VDDO + 0.3 V

VIL(DC) Low DC input voltage –0.3 VREF – 0.125 V


Output Buffer RT = 25, RS = 20

IOH Output minimum source current(1) –13.4 mA

IOL Output minimum sink current(1) 13.4 mA

Notes: 1. VDDO = 1.7V, VOUT(MIN) = 833 mV, VTT = 40 mV

Table 25: SSTL18 AC Specifications


UnitsMin Max

VIH(AC) High AC input voltage VREF + 0.25 V

VIL(AC) Low AC input voltage VREF – 0.25 V

Class I Output Buffer RT = 50, RS = 25

VOH(AC) High AC output voltage(1) VTT + 0.57 V

VOL(AC) Low AC output voltage(1) VTT – 0.57 V

Class II Output Buffer RT = 25, RS = 25

VOH(AC) High AC output voltage(2) VTT + 0.76 V

VOL(AC) Low AC output voltage(2) VTT – 0.76 V

Notes: 1. Tested with RT = 50, RS = 20, CLOAD = 5 pF (JESD 8‐15 Figure 4).

2. Tested with RT = 50, RS = 20, CLOAD = 5 pF (JESD 8‐15 Figure 4).


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SSTL15Table 26: SSTL15 General Specifications



VREF Input reference voltage 0.7425 0.75 0.7575 V

VTT Termination voltage VREF -0.04 VREF VREF +0.04 V

Table 27: SSTL15 DC Specifications


UnitsMin Max

VIH(DC) High DC input voltage VREF + 0.100 V

VIL(DC) Low DC input voltage VREF – 0.100 V

VOH(DC) High DC output voltage 0.8 x VDDIO V

VOL(DC) Low DC output voltage 0.2 x VDDIO V

IOZK Off-state leakage current uA


Table 28: SSTL15 AC Specifications


UnitsMin Max


VIL(AC) Low AC input voltage VREF – 0.175 V

VOH(AC) High AC output voltage VTT + 0.1 x VDDQ V

VOL(AC) Low AC output voltage VTT – 0.1 x VDDQ V


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POD18

POD15

Table 29: POD18 General Specifications



VREF Output reference voltage 0.69*VDDO 0.70*VDDO 0.71*VDDO V

Table 30: POD18 DC Specifications


UnitsMin Max


VIL(DC) Low DC input voltage VREF - 0.15 V

IL Input Leakage -5 5 μA

VOL(DC) Output Logic Low 0.76 V

Table 31: POD18 AC Specifications


UnitsMin Max


VIL(AC) Low AC input voltage VREF -0.25 V

Table 32: POD15 General Specifications



VREF Output reference voltage 0.69*VDDO 0.70*VDDO 0.71*VDDO V

Table 33: POD15 DC Specifications


UnitsMin Max


VIL(DC) Low DC input voltage VREF - 0.12 V

IL Input Leakage TBD TBD μA

VOL(DC) Output Logic Low 0.62 V



UnitsMin Max



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VIL(AC) Low AC input voltage VREF -0.20 V



UnitsMin Max


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LVDS18

Table 35: LVDS18 Supply Voltages

Symbol Description Min Nom Max UnitsVDDO I/O supply voltage 1.7 1.8 1.9 V

Table 36: LVDS18 DC Specifications

Symbol Description Conditions Min Max Units

ReceiverVI Input voltage range, VIA/VIB 0 1.8 V

VIDTH Input differential threshold -100 +100 mV

VID Input differential voltage range 100 900 mV

VHYST Input differential hysteresis (VIDTHH–VIDTHL) TBD TBD mV

RIN Receiver diff input impedance Worst case: SS, 0°C 90 110

DriverVOH Output voltage High, VOA/VOB

RLOAD = 100 ± 1%

TBD TBD V

VOL Output voltage Low, VOA/VOB TBD TBD mV

|VOD| Output differential voltage TBD TBD mV

VOS Output offset voltage TBD TBD V

RO Output impedance, single endedVCM = 1.0V and 1.4V

TBD TBD

RO RO mismatch between A and B TBD TBD %

|VOD| Change in |VOD| between 0 and 1RLOAD = 100 ± 1%

TBD TBD mV

|VOS| Change in |VOS|| between 0 and 1 TBD TBD mV

ISA/ISB Output Current Driver shorted to ground TBD TBD mA

ISAB Output Current Drivers shorted together TBD TBD mA

IXA/IXB Power-off output leakage TBD TBD mA

VVREF Reference supply voltage TBD TBD V

IVREF Reference leakage current TBD TBD mA

Table 37: LVDS18 AC Specifications


ReceiverTPD Propagation delay TBD TBD ns

TSKEW Skew tolerable at receiver input to meet TSU/THOLD TBD TBD ps

DriverClock Clock signal duty cycle TBD TBD %TFALL VOD fall time, 20–80%

RLOAD = 100 ± 1%TBD TBD ps

TRISE VOD rise time, 20–80% TBD TBD ps

TSKEW1 |TPHLA – TPLHB| or |TPHLB – TPLHA|, differential skew Any differential pair on package TBD TBD ps

TSKEW2 |TPDIFF[M] – TPDIFF[N]| channel-to-channel skew Any two signals on package TBD TBD ps


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DHSTL18

Table 38: DHSTL18 Supply Voltages

Symbol Description Min Max UnitsVDDO I/O supply voltage TBD TBD VVDD Core supply voltage TBD TBD V

Table 39: DHSTL18 DC Specifications


ReceiverVI Input voltage range, VIA/VIB TBD TBD V

VIDTH Input differential threshold TBD TBD mV

VID Input differential voltage range TBD TBD mV


RIN Receiver diff input impedance Worst case: SS, 0°C TBD TBD


RLOAD = 100 ± 1%

TBD TBD V





TBD TBD



TBD TBD mV







Table 40: DHSTL18 AC Specifications










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DHSTL15



Table 42: DHSTL 15 DC Specifications








RLOAD = 100 ± 1%

TBD TBD V





TBD TBD



TBD TBD mV

















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DHSTL12



Table 45: DHSTL12 DC Specifications








RLOAD = 100 ± 1%

TBD TBD V





TBD TBD



TBD TBD mV





VVREF Reference supply voltage TBD TBD












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DSSTL18

Table 47: DSSTL18 Supply Voltages


Table 48: DSSTL18 DC Specifications








RLOAD = 100 ± 1%

TBD TBD V





TBD TBD



TBD TBD mV







Table 49: DSSTL18 AC Specifications










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DSSTL15











RLOAD = 100 ± 1%

TBD TBD V





TBD TBD



TBD TBD mV

















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DSSTL12











RLOAD = 100 ± 1%

TBD TBD V





TBD TBD



TBD TBD mV

















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HT 1.0

Table 56: HT 1.0 Specifications

Symbol Description Min Typical Max Units

VOD Differential output voltage 495 600 715 mV

ΔVOD Change in VOD amplitude -15 15 mV

VOCM Output common-mode voltage 495 600 715 mV

ΔVOCM Change in VOCM amplitude -15 15 mV

VID Input differential voltage 200 600 1000 mV

ΔVID Change in VID amplitude -15 15 mV

VICM Input common-mode voltage 440 600 780 mV

ΔVICM Change in VICM amplitude -15 15 mV


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I/O Leakage

Compensation and Termination

The EF banks in Speedster devices have compensation controller blocks to provide accurate process, voltage, andtemperature compensated driver output and receiver termination impedances. Some I/O standards requiretermination or compensation resistors for proper operation. Table 58 lists the external resistor values needed forthe driver compensation on DRVHI/DRVLO, and Table 59 lists the external resistor values for RTT termination

compensation on RTTHI/RTTLO.

Note: The resistor on DRVHI/RTTHI is connected to VSS, and the resistor on DRVLO/RTTLO is connected to VDDO.

Table 57: I/O Tri-state Leakage Currents

Symbol Description Condition Min Max Units

IOZ Off-state Leakage Current(1)

1.62 VDDO 1.986 TBD TBD μA



IOZKOff-state Leakage Current with Bus Keeper enabled(1)




Notes: 1. Includes input leakage current

Table 58: Compensation Resistor Values

Standard Resistor Value

HSTL18 Class I TBD

HSTL18 Class II TBD

DDR3 (SSTL15) TBD

DDR2 Class I (SSTL18) TBD

DDR2 Class II TBD

DDR1 Class I TBD

DDR1 Class II TBD

Table 59: Termination Resistor Values(1)

Resistor Value Resulting Termination

300 TBD

240 TBD

200 TBD

Notes: 1. The two different values of termination resistance for

the same value of external compensation resistor con‐nected to RTTHI/RTTLO is set via a configuration bit.

Table 59: Termination Resistor Values(1)

Resistor Value Resulting Termination


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Pin Descriptions Speedster22i HD FPGA Family

Pin DescriptionsTable 60: Speedster22i FPGA Pin Description

Pin Name Pin Group Type Description

12.75 Gbps SerDes (64 lanes)PA_VDD1 N12P75G Power Analog 0.95V Power Supply

PA_VDD2 N12P75G Power Analog 1.8V Power Supply

VREF_B[30,31,32,40,41,42,50,51,52]

N12P75G Power Analog input; Voltage Bias reference

PAD_TE_I_A_RXTERMV_LNUM[31:0]

N12P75G Power Receiver Termination Voltage Pad input

PAD_TE_I_BCK_REF_M/P_LNUM[15:0]

N12P75G Clock The 12.75 Gbps SerDes reference clock supplied from either a single-ended or differential external source. Each reference clock is buffered, distributed to two lanes, used by the clock multipli-cation unit (CMU) in each lane to generate the transmit bit clock and distributed to the respective data lanes. The requirements on the reference clock vary depending on the standard and data rate used. There is 1 differential pair for each of 2 , 12.75Gbps lane.

PAD_TE_I_BA_RX_P/M_LNUM[31:0]

N12P75G Input Receive differential inputs to the 12.75 Gbps SerDes. One pair for each lane.

PAD_TE_O_A_APROBE_LNUM[31:0]

N12P75G Output The 12.75 Gbps SerDes Analog DC test pad used for ATE and bench testing, one for each lane

PAD_TE_O_BA_TX_P/M_LNUM[31:0]

N12P75G Output Transmit differential outputs from the 12.75 Gbps SerDes. There is one differential pair per each 12.75Gbps lane.

PA_VDD1 S12P75G Power Analog 0.95V Power Supply

PA_VDD2 S12P75G Power Analog 1.8V Power Supply

VREF_B[10,11,12,20,21,22,30,31,32]

S12P75G Power Analog input; Voltage Bias reference

PAD_BE_I_A_RXTERMV_LNUM[31:0]

S12P75G Power Receiver Termination Voltage Pad input

PAD_BE_I_BCK_REF_M/P_LNUM[15:0]

S12P75G Clock The 12.75 Gbps SerDes reference clock supplied from either a single-ended or differential external source. Each reference clock is buffered, distributed to two lanes, used by the clock multipli-cation unit (CMU) in each lane to generate the transmit bit clock and distributed to the respective data lanes. The requirements on the reference clock vary depending on the standard and data rate used. There is 1 differential pair for each of 2 , 12.75Gbps lane

PAD_BE_I_BA_RX_P/M_LNUM[31:0]

S12P75G Input Receive differential inputs to the 12.75 Gbps SerDes. One pair for each lane

PAD_BE_O_A_APROBE_LNUM[31:0]

S12P75G Output The 12.75 Gbps SerDes Analog DC test pad used for ATE and

bench testing, one for each lane."

PAD_BE_O_BA_TX_P/M_LNUM[31:0]

S12P75G Output "Transmit differential outputs from the 12.75 Gbps SerDes. There is one differential pair per each 12.75Gbps lane.

IEEE1149.1 Interface


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Speedster22i HD FPGA Family Pin Descriptions

VDDO_JCFG CFG Power Supply voltage powering the I/O buffers for the IEEE 1149.1 JTAG interface. The value selected determine the output VOH level on TDO and set the input threshold VIL and VIH values appropriately. (TAP) controller state machine transitions. This input is captured on the rising edge of the test logic clock (TCK). This dedicated pin is equipped with a pull-up resistor to place the test logic in the Test-Logic-Reset state

TMS JTAG Input The Test Mode Select (TMS) input controlling the test access port (TAP) controller state machine transitions. This input is captured on the rising edge of the test logic clock (TCK). This dedicated pin is equipped with a pull-up resistor to place the test logic in the Test-Logic-Reset state

TCK JTAG Input IEEE 1149.1 JTAG interface dedicated test clock used to advance the TAP controller and clock in data on the TDI input and out on the TDO output. The maximum frequency for TCK is 100 MHz

TDI JTAG Input IEEE1149.1 JTAG interface serial input for instruction and test data. Data is captured on the rising edge of the test logic clock. This dedicated pin is equipped with a pull-up resistor

TRSTN JTAG Input IEEE 1149.1 JTAG interface asynchronous active-Low reset input used to initialize the TAP controller. This dedicated pin is equipped with a pull-up resistor

TDO JTAG Output IEEE 1149.1 JTAG serial output for data from the test logic. TDO is set to an inactive drive state (high impedance) when data scanning is not in progress. This pin is equipped with a pull-up resistor. TDO drives out valid data on the falling edge of the TCK input

Configuration Interface VDD_CFG CFG Power The supply voltage for the I/Os in the configuration bank.

VDD_CFGWL CFG Power Power Supply for Configuration Memory Cells.

CONFIG_STATUS CFG Open drain output

Pin asserted active-Low by the FCU should an error be detected during configuration

CONFIG_RSTN CFG Input Asynchronous active-Low reset input clearing the configuration memory in the device and the logic in the FPGA configuration unit (FCU). In JTAG mode, pulled up (to VDDO_JCFG)

CONFIG_MODESEL[2:0] CFG Open drain output

Configuration mode selection inputs to define the FPGA configu-ration unit (FCU) mode of operation: • 001: SPI x1 configuration mode• 010: SPI x4 configuration mode• 100: CPU configuration mode

PROGRAM_ENABLE[1:0] CFG input Pin enabling the programming of the eFuse for the AES encryption keys. This input pin active-High (to the VDDO_JCFG voltage level)

Table 60: Speedster22i FPGA Pin Description (Continued)



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CONFIG_DONE CFG Input with open-drain or active output

Pin asserted active-Low prior to the completion of device config-uration. After the device successfully completes configuration, this pin is either tri-stated or can optionally be driven High. The default behavior is open-drain, tri-stating the pin when the device is properly configured. If a device configuration error occurs, the CONFIG_DONE output for the device remains in active-Low. In the default mode of operation, an external pull-up resistor is needed to take the pin High. The device does not enter the functional mode until this pin is active-High. Holding this pin Low on the board can be used as a method to synchronize the start-up of multiple devices

CONFIG_CLKSEL CFG Input Pin controlling whether the FCU clock is sourced from the TCK input or the CPU_CLK input when CONFIG_SYSCLK_BYPASS is asserted active-High thus enabling the bypass of the internal SYS_CLK: • When this input is biased to '1', TCK is selected• When this input is biased to '0', CPU_CLK is selected

HOLDN CFG Output In the SPI mode of operation, the hold signal output for SPI flash devices. In CPU mode, this bit is the bidirectional data bit 5, DQ[5]."

CPU_CLK Maximum 25Mhz . Used as FCU clock under CONFIG_CLKSEL control

BYPASS_CLR_MEM CFG NOT Available for HD1000

SCK CFG Output Serial flash clock output. Default rate is set to 25 MHz. This output clock rate can be lowered by the bitstream during configuration

SDI CFG Output In the SPI modes of operation, the serial data output pins for command and programming data to the flash memory. These command and programming commands are sent via control registers writes done via the IEEE 1149.1 JTAG interface. In the CPU mode, this pin is the bidirectional data bit 0, DQ[0]

CSN[3:0] CFG Input/ Output

"In SPI Mode: The CSN[3:0] pins are active-Low chip select outputs. In the programming mode, individual serial flash devices are mapped to a linear addressing space. In the SPI x1 configu-ration mode only the CSN[0] output is used.In CPU Mode: CSN[3] is the bidirectional data bit 6, DQ[6]. CSN[2] is the bidirectional data bit 7. DQ[7]. CSN[1] is not used. CSN[0] is an active-Low chip select input

SDO[3:0] CFG Input "Input pins providing data input from the flash device(s). In SPI x4 configuration mode, all 4 SDO inputs are utilized. When in SPI x1 mode, only the SDO[0] input is used to input the configuration data In the CPU mode, these bits serve as the bidirectional data bits 1 through 4 (SDO3=DQ1, SDO2=DQ2, SDO1=DQ3, SDO0=DQ4)"

CONFIG_SYSCLK_BYPASS CFG "Pin statically enabling the bypass of the internal SYS_CLK.Thedefault clock for the FPGA configuration unit (FCU) is named SYS_CLK. An on-chip ring oscillator is the source for SYS_CLK. For debug purposes this clock can be bypassed and an external clock supplied. In the bypass mode, this pin can be connected to either the IEEE 1149.1 JTAG input pin for TCK or the CPU_CLK input pin

START_CONFIG_STARTUP CFG




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STAP_SEL CFG When asserted high, this allows the JTAG interface pins to be directly connected to the JTAG controller in Serdes PMA blocks allowing SerDes configuration, debug and performance monitoring directly from the JTAG interface. For bitstream download and chip debug using the JTAG interface, this pin must be held low

READ_STATE_ERR CFG (Not available for HD1000)

CONFIG_SCRUB_MULTIPLE_ERR

CFG (Not available for HD1000)

CONFIG_SCRUBBING_ENABLE


CONFIG_SCRUB_SINGLE_ERR


Power VDDL CVDD Power Power Supply for FPGA fabric core logic

VCC SVDD Power Power Supply for FPGA - hard IP blocks.

VCCRAM_EFUSE[2:1] EFUSE Power Efuse Power Supply normal / read operations. 1.0V

VCCFHV_EFUSE[2:1] FFUSE Power Efuse Power Supply for Fuse Program/ Erase operations 2.2V for program and 1.0V during Reads

VDDA_NOM_E EVDDA Power

VREG_CMN VREG_CMN Power Serdes - Analog Regulated Power Supply - Common Lanes

VREG_RX VREG_RX Power Serdes - Analog Regulated Power Supply - Receive Lanes

VREG_SYNTHX VREG_SYNTHX

Power Serdes - Analog Regulated Power Supply - Synthesizer and Trans-mitter lanes

VDDA_NOM_W WVDDA Power

VDD_BRAM VDD_BRAM Power Power Supply for Block RAMS in Fabric.

VSS VSS Power Ground

User Programmable I/O Interface VDDO_B[32] BES Power Bank I/O supply voltage. (1.2V, 1.5V, 1.8V)

RCOMP_TERM_B[30,31,32] BES Input Termination resistor input for Dynamic drive compensation for PVT and aging

RCOMP_DRV_B[30,31,32] BES

PAD_ES_BYTEIO[12:1]DQ[9:0]

BES Input/ output

A group of 12 byte lanes. Each byte lane has 12 bits ; 10 of these 12 bits for each of the byte lanes. Could be set for Single Ended , differential, LVCOMS/*STL/LVDS modes. Functionality/ connection details for each of the memory standards / SPI4.2 detailed in respective user guides

PAD_ES_BYTEIO[12:1]DQS BES Input/ output

A group of 12 byte lanes. Each byte lane has 12 bits ; 11ith bit of 12 bits for each of the byte lanes. Could be set for Single Ended , differential, LVCOMS/*STL/LVDS modes. Functionality/ connection details for each of the memory standards / SPI4.2 detailed in respective user guides. In DDR3 mode carries a Synchronous strobe signal ( positive polarity differential clock) for referencing DQ[9:0]




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PAD_ES_BYTEIO[12:1]DQSN

BES Input/ output

A group of 12 byte lanes. Each byte lane has 12 bits ; 11ith bit of 12 bits for each of the byte lanes. Could be set for Single Ended , differential, LVCOMS/*STL/LVDS modes. Functionality/ connection details for each of the memory standards / SPI4.2 detailed in respective user guides. In DDR3 mode carries a Synchronous strobe signal ( negative polarity differential clock) for referencing DQ[9:0]

VDDO_B[42] BEC Power Bank I/O supply voltage. (1.2V, 1.5V, 1.8V)

RCOMP_TERM_B[40,41,42] BEC Input Termination resistor input for Dynamic drive compensation for PVT and aging

RCOMP_DRV_B[40,41,42] BEC

PAD_EC_BYTEIO[12:1]DQ[9:0]

BEC Input/ output


PAD_EC_BYTEIO[12:1]DQS BEC Input/ output


PAD_EC_BYTEIO[12:1]DQSN

BEC Input/ output


VDDO_B[52] BEN Power Bank I/O supply voltage. (1.2V, 1.5V, 1.8V)

RCOMP_TERM_B[50,51,52] BEN Termination resistor input for Dynamic drive compensation for PVT and aging

RCOMP_DRV_B[50,51,52] BEN

PAD_EN_BYTEIO[12:1]DQ[9:0]

BEN Input/ output


PAD_EN_BYTEIO[12:1]DQS BEN Input/ output





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PAD_EN_BYTEIO[12:1]DQSN

BEN Input/ output


VDDO_B[02] BWS Power Bank I/O supply voltage. (1.2V, 1.5V, 1.8V)

RCOMP_TERM_B[00,01,02] BWS Termination resistor input for Dynamic drive compensation for PVT and aging

RCOMP_DRV_B[00,01,02] BWS

PAD_WS_BYTEIO[12:1]DQ[9:0]

BWS Input/ output


PAD_WS_BYTEIO[12:1]DQS

BWS Input/ output


PAD_WS_BYTEIO[12:1]DQSN

BWS Input/ output


VDDO_B[12] BWC Power Bank I/O supply voltage. (1.2V, 1.5V, 1.8V)

RCOMP_TERM_B[10,11,12] BWC Termination resistor input for Dynamic drive compensation for PVT and aging

RCOMP_DRV_B[10,11,12] BWC

PAD_WC_BYTEIO[12:1]DQ[9:0]

BWC Input/ output


PAD_WC_BYTEIO[12:1]DQS

BWC Input/ output





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PAD_EC_BYTEIO[12:1]DQSN

BWC Input/ output


VDDO_B[22] BWN Power Bank I/O supply voltage. (1.2V, 1.5V, 1.8V)

RCOMP_TERM_B[20,21,22] BWN Input Termination resistor input for Dynamic drive compensation for PVT and aging

RCOMP_DRV_B[20,21,22] BWN

PAD_WN_BYTEIO[12:1]DQ[9:0]

BWN Input/ output


PAD_WN_BYTEIO[12:1]DQS

BWN Input/ output


PAD_WN_BYTEIO[12:1]DQSN

BWN Input/ output


Miscellaneous NB NB There is no solder ball at this grid location on the package

CORE_TESIN1 DBG Debug Interface used for testing the fabric

EDM No Connect For Factory Use/ Test purposes

TEMP_DIODE_P/N Die temperature monitoring diode connections (P and N).

EFUSE_PROG EFUSE Output HD1000's Efuse Erase/Program sequencer controls this signal. When high, Efuse (user bank) can be erased/ programmed and requires a higher voltage level - 2.2V on VDDO_FHV. When low this level is 1.0V

Notes: N12P75G : North SerDes LanesS12P75G : South SerDes LanesB(E/W)(N/C/S) : Enhanced I/O banks (East/West) (North/Center/South) SVDD : Synchronous VDD CVDD : Core VDD




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Speedster22i HD FPGA Family Pinouts

Pinouts2597-Pin Fine Ball Grid Array (FG2597)

Table 61: FG2597 52.5mm x 52.5mm Package Pin Out

Pin Pin Name Pin Group

A1 NB NB

A10 VSS VSS

A11 PA_VDD1 S12P75G

A12 PAD_BE_O_BA_TX_P_LNUM1 S12P75G

A13 PA_VDD1 S12P75G


A15 PA_VDD1 S12P75G


A17 PA_VDD1 S12P75G


A19 PA_VDD1 S12P75G

A2 VSS VSS


A21 PA_VDD1 S12P75G


A23 PA_VDD1 S12P75G


A25 PA_VDD1 S12P75G


A27 PA_VDD1 S12P75G


A29 PA_VDD1 S12P75G

A3 VSS VSS


A31 PA_VDD1 S12P75G


A33 PA_VDD1 S12P75G


A35 PA_VDD1 S12P75G


A37 PA_VDD1 S12P75G


A39 PA_VDD1 S12P75G

A4 PAD_WS_BYTEIO9_DQ7 BWS



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Pinouts Speedster22i HD FPGA Family

A41 PA_VDD1 S12P75G


A43 VSS VSS

A44 VSS VSS

A45 VSS VSS

A46 VSS VSS

A47 VSS VSS

A48 PAD_ES_BYTEIO9_DQ7 BES

A49 VSS VSS

A5 VSS VSS

A50 VSS VSS

A51 NB NB

A6 VSS VSS

A7 VSS VSS

A8 VSS VSS

A9 VSS VSS

AA1 PAD_WC_BYTEIO11_DQ4 BWC

AA10 PAD_WS_BYTEIO2_DQ2 BWS



AA13 RCOMP_DRV_B21 BES

AA14 RCOMP_TERM_B21 BES

AA15 VREF_B21 S12P75G

AA16 VDDO_B21 BWS

AA17 VDDO_B21 BWS

AA18 VCC SVDD

AA19 VDDL CVDD

AA2 PAD_WC_BYTEIO11_DQ6 BWC

AA20 VDDL CVDD

AA21 VDDL CVDD

AA22 VDDL CVDD

AA23 VDDL CVDD

AA24 VDDL CVDD

AA25 VDDL CVDD

AA26 VCFG CFG

AA27 VCFGWL CFG

AA28 VDDL CVDD

AA29 VDDL CVDD

AA3 PAD_WS_BYTEIO1_DQS BWS




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AA30 VDDL CVDD

AA31 VDDL CVDD

AA32 VDDL CVDD

AA33 VDDL CVDD

AA34 VCC SVDD

AA35 VDDO_B31 BES

AA36 VDDO_B31 BES

AA37 VREF_B31 S12P75G

AA38 RCOMP_DRV_B31 BWN

AA39 RCOMP_TERM_B31 BWN

AA4 PAD_WS_BYTEIO1_DQSN BWS

AA40 PAD_ES_BYTEIO0_DQ4 BES




AA44 PAD_EC_BYTEIO12_DQSN BEC

AA45 PAD_EC_BYTEIO12_DQS BEC

AA46 PAD_EC_BYTEIO10_DQSN BEC

AA47 PAD_EC_BYTEIO10_DQS BEC

AA48 PAD_ES_BYTEIO1_DQSN BES

AA49 PAD_ES_BYTEIO1_DQS BES

AA5 PAD_WC_BYTEIO10_DQS BWC

AA50 PAD_EC_BYTEIO11_DQ6 BEC

AA51 PAD_EC_BYTEIO11_DQ4 BEC

AA6 PAD_WC_BYTEIO10_DQSN BWC

AA7 PAD_WC_BYTEIO12_DQS BWC

AA8 PAD_WC_BYTEIO12_DQSN BWC


AB1 PAD_WC_BYTEIO11_DQ0 BWC

AB10 PAD_WS_BYTEIO2_DQ6 BWS



AB13 RCOMP_DRV_B20 BES

AB14 RCOMP_TERM_B20 BES

AB15 VDDA_NOM_W WVDDA

AB16 VDDO_B20 BWS

AB17 VDDO_B20 BWS

AB18 VCC SVDD

AB19 VSS VSS




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AB20 VSS VSS

AB21 VSS VSS

AB22 VSS VSS

AB23 VSS VSS

AB24 VSS VSS

AB25 VSS VSS

AB26 VCFG CFG

AB27 VSS VSS

AB28 VSS VSS

AB29 VSS VSS


AB30 VSS VSS

AB31 VSS VSS

AB32 VSS VSS

AB33 VSS VSS

AB34 VCC SVDD

AB35 VDDO_B30 BES

AB36 VDDO_B30 BES

AB37 VDDA_NOM_E EVDDA

AB38 RCOMP_TERM_B30 BWN

AB39 RCOMP_DRV_B30 BWN


AB40 PAD_ES_BYTEIO0_DQ1 BES




AB44 PAD_EC_BYTEIO12_DQ2 BEC















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AC1 PAD_WC_BYTEIO7_DQ1 BWC






AC15 VREF_B20 S12P75G

AC16 VSS VSS

AC17 VDDO_B20 BWS

AC18 VSS VSS

AC19 VDDL CVDD


AC20 VDD_BRAM VDD_BRAM

AC21 VDDL CVDD

AC22 VDDL CVDD

AC23 VDDL CVDD


AC25 VDDL CVDD

AC26 VDDL CVDD

AC27 VDDL CVDD


AC29 VDDL CVDD


AC30 VDDL CVDD

AC31 VDDL CVDD


AC33 VDDL CVDD

AC34 VSS VSS

AC35 VDDO_B30 BES

AC36 VSS VSS

AC37 VREF_B30 S12P75G

AC38 PAD_EC_BYTEIO1_DQ8 BEC










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AD1 PAD_WC_BYTEIO7_DQ5 BWC

AD10 VSS VSS


AD12 VSS VSS


AD14 VSS VSS

AD15 VDDA_NOM_W WVDDA

AD16 VDDO_B20 BWS

AD17 VDDO_B20 BWS

AD18 VSS VSS

AD19 VSS VSS

AD2 VSS VSS

AD20 VSS VSS

AD21 VSS VSS

AD22 VSS VSS

AD23 VSS VSS

AD24 VSS VSS

AD25 VSS VSS

AD26 VSS VSS

AD27 VSS VSS

AD28 VSS VSS

AD29 VSS VSS


AD30 VSS VSS

AD31 VSS VSS

AD32 VSS VSS




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AD33 VSS VSS

AD34 VSS VSS

AD35 VDDO_B30 BES

AD36 VDDO_B30 BES

AD37 VDDA_NOM_E EVDDA

AD38 VSS VSS

AD39 PAD_EC_BYTEIO1_DQ9 BEC

AD4 VSS VSS

AD40 VSS VSS


AD42 VSS VSS


AD44 VSS VSS


AD46 VSS VSS


AD48 VSS VSS



AD50 VSS VSS


AD6 VSS VSS


AD8 VSS VSS


AE1 PAD_WC_BYTEIO7_DQ3 BWC


AE11 PAD_WC_BYTEIO2_DQSN BWC

AE12 PAD_WC_BYTEIO2_DQS BWC



AE15 VREF_B12 S12P75G

AE16 VDDO_B12 BWC

AE17 VDDO_B12 BWC

AE18 VCC SVDD

AE19 VDDL CVDD


AE20 VDDL CVDD

AE21 VDDL CVDD




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AE22 VDDL CVDD

AE23 VDDL CVDD

AE24 VDDL CVDD

AE25 VDDL CVDD

AE26 VCFG CFG

AE27 VCFGWL CFG

AE28 VDDL CVDD

AE29 VDDL CVDD


AE30 VDDL CVDD

AE31 VDDL CVDD

AE32 VDDL CVDD

AE33 VDDL CVDD

AE34 VCC SVDD

AE35 VDDO_B42 BEC

AE36 VDDO_B42 BEC

AE37 VREF_B42 S12P75G

AE38 PAD_EC_BYTEIO1_DQ2 BEC



AE40 PAD_EC_BYTEIO2_DQS BEC

AE41 PAD_EC_BYTEIO2_DQSN BEC



AE44 PAD_EC_BYTEIO3_DQS BEC

AE45 PAD_EC_BYTEIO3_DQSN BEC









AE7 PAD_WC_BYTEIO3_DQSN BWC

AE8 PAD_WC_BYTEIO3_DQS BWC


AF1 PAD_WC_BYTEIO7_DQ7 BWC

AF10 PAD_WC_BYTEIO4_DQS BWC




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AF13 PAD_WC_BYTEIO1_DQS BWC

AF14 PAD_WC_BYTEIO1_DQSN BWC

AF15 VDDA_NOM_W WVDDA

AF16 VSS VSS

AF17 VDDO_B12 BWC

AF18 VCC SVDD

AF19 VSS VSS


AF20 VSS VSS

AF21 VSS VSS

AF22 VSS VSS

AF23 VSS VSS

AF24 VSS VSS

AF25 VSS VSS

AF26 VCFG CFG

AF27 VSS VSS

AF28 VSS VSS

AF29 VSS VSS


AF30 VSS VSS

AF31 VSS VSS

AF32 VSS VSS

AF33 VSS VSS

AF34 VCC SVDD

AF35 VDDO_B42 BEC

AF36 VSS VSS

AF37 VDDA_NOM_E EVDDA

AF38 PAD_EC_BYTEIO1_DQSN BEC

AF39 PAD_EC_BYTEIO1_DQS BEC


AF40 PAD_EC_BYTEIO2_DQ2 BEC


AF42 PAD_EC_BYTEIO4_DQS BEC

AF43 PAD_EC_BYTEIO4_DQSN BEC







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AF9 PAD_WC_BYTEIO4_DQSN BWC

AG1 VSS VSS

AG10 PAD_WC_BYTEIO4_DQ1 BWC

AG11 VSS VSS


AG13 VSS VSS


AG15 VREF_B11 S12P75G

AG16 VDDO_B12 BWC

AG17 VDDO_B12 BWC

AG18 VSS VSS

AG19 VDDL CVDD


AG20 VDD_BRAM VDD_BRAM

AG21 VDDL CVDD

AG22 VDDL CVDD

AG23 VDDL CVDD


AG25 VDDL CVDD

AG26 VDDL CVDD

AG27 VDDL CVDD


AG29 VDDL CVDD

AG3 VSS VSS

AG30 VDDL CVDD

AG31 VDDL CVDD


AG33 VDDL CVDD

AG34 VSS VSS

AG35 VDDO_B42 BEC




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AG36 VDDO_B42 BEC

AG37 VREF_B41 S12P75G

AG38 PAD_EC_BYTEIO1_DQ0 BEC

AG39 VSS VSS



AG41 VSS VSS


AG43 VSS VSS


AG45 VSS VSS


AG47 VSS VSS


AG49 VSS VSS

AG5 VSS VSS


AG51 VSS VSS


AG7 VSS VSS


AG9 VSS VSS

AH1 PAD_WC_BYTEIO7_DQS BWC

AH10 PAD_WC_BYTEIO4_DQ6 BWC





AH15 VDDA_NOM_W WVDDA

AH16 VDDO_B11 BWC

AH17 VDDO_B11 BWC

AH18 VSS VSS

AH19 VSS VSS

AH2 PAD_WC_BYTEIO7_DQSN BWC

AH20 VSS VSS

AH21 VSS VSS

AH22 VSS VSS

AH23 VSS VSS

AH24 VSS VSS




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AH25 VSS VSS

AH26 VSS VSS

AH27 VSS VSS

AH28 VSS VSS

AH29 VSS VSS


AH30 VSS VSS

AH31 VSS VSS

AH32 VSS VSS

AH33 VSS VSS

AH34 VSS VSS

AH35 VDDO_B41 BEC

AH36 VDDO_B41 BEC

AH37 VDDA_NOM_E EVDDA

AH38 PAD_EC_BYTEIO1_DQ4 BEC









AH46 PAD_EC_BYTEIO9_DQS BEC

AH47 PAD_EC_BYTEIO9_DQSN BEC










AJ1 PAD_WC_BYTEIO7_DQ6 BWC








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AJ15 VREF_B10 S12P75G

AJ16 VSS VSS

AJ17 VDDO_B11 BWC

AJ18 VCC SVDD

AJ19 VDDL CVDD


AJ20 VDDL CVDD

AJ21 VDDL CVDD

AJ22 VDDL CVDD

AJ23 VDDL CVDD

AJ24 VDDL CVDD

AJ25 VDDL CVDD

AJ26 VCFG CFG

AJ27 VCFGWL CFG

AJ28 VDDL CVDD

AJ29 VDDL CVDD


AJ30 VDDL CVDD

AJ31 VDDL CVDD

AJ32 VDDL CVDD

AJ33 VDDL CVDD

AJ34 VCC SVDD

AJ35 VDDO_B41 BEC

AJ36 VSS VSS

AJ37 VREF_B40 S12P75G

AJ38 PAD_EC_BYTEIO1_DQ1 BEC
















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AK1 PAD_WC_BYTEIO6_DQ9 BWC

AK10 PAD_WN_BYTEIO10_DQ7 BWN



AK13 VSS VSS

AK14 VDDA_NOM_W WVDDA

AK15 VDDA_NOM_W WVDDA

AK16 VDDO_B11 BWC

AK17 VDDO_B11 BWC

AK18 VCC SVDD

AK19 VSS VSS


AK20 VSS VSS

AK21 VSS VSS

AK22 VSS VSS

AK23 VSS VSS

AK24 VSS VSS

AK25 VSS VSS

AK26 VCFG CFG

AK27 VSS VSS

AK28 VSS VSS

AK29 VSS VSS


AK30 VSS VSS

AK31 VSS VSS

AK32 VSS VSS

AK33 VSS VSS

AK34 VCC SVDD

AK35 VDDO_B41 BEC

AK36 VDDO_B41 BEC

AK37 VDDA_NOM_E EVDDA

AK38 VDDA_NOM_E EVDDA




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AK39 VSS VSS


AK40 PAD_EN_BYTEIO1_DQ2 BEN








AK48 PAD_EC_BYTEIO5_DQ3 BEC









AL1 PAD_WC_BYTEIO6_DQ8 BWC

AL10 VSS VSS

AL11 PAD_WN_BYTEIO1_DQ3 BWN

AL12 VSS VSS

AL13 RCOMP_TERM_B12 BEC

AL14 RCOMP_DRV_B12 BEC

AL15 VREF_B02 S12P75G

AL16 VDDO_B10 BWC

AL17 VDDO_B10 BWC

AL18 VSS VSS

AL19 VDDL CVDD

AL2 VSS VSS

AL20 VDD_BRAM VDD_BRAM

AL21 VDDL CVDD

AL22 VDDL CVDD

AL23 VDDL CVDD


AL25 VDDL CVDD

AL26 VDDL CVDD

AL27 VDDL CVDD




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AL29 VDDL CVDD

AL3 PAD_WC_BYTEIO5_DQ9 BWC

AL30 VDDL CVDD

AL31 VDDL CVDD


AL33 VDDL CVDD

AL34 VSS VSS

AL35 VDDO_B40 BEC

AL36 VDDO_B40 BEC

AL37 VREF_B52 S12P75G

AL38 RCOMP_TERM_B42 BWC

AL39 RCOMP_DRV_B42 BWC

AL4 VSS VSS

AL40 VSS VSS

AL41 PAD_EN_BYTEIO1_DQ3 BEN

AL42 VSS VSS


AL44 VSS VSS


AL46 VSS VSS


AL48 VSS VSS

AL49 PAD_EC_BYTEIO5_DQ9 BEC


AL50 VSS VSS

AL51 PAD_EC_BYTEIO6_DQ8 BEC

AL6 VSS VSS


AL8 VSS VSS


AM1 PAD_WC_BYTEIO6_DQ7 BWC

AM10 PAD_WN_BYTEIO10_DQ5 BWN



AM13 RCOMP_TERM_B11 BEC

AM14 RCOMP_DRV_B11 BEC

AM15 VDDA_NOM_W WVDDA

AM16 VSS VSS




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AM17 VDDO_B10 BWC

AM18 VSS VSS

AM19 VSS VSS


AM20 VSS VSS

AM21 VSS VSS

AM22 VSS VSS

AM23 VSS VSS

AM24 VSS VSS

AM25 VSS VSS

AM26 VSS VSS

AM27 VSS VSS

AM28 VSS VSS

AM29 VSS VSS


AM30 VSS VSS

AM31 VSS VSS

AM32 VSS VSS

AM33 VSS VSS

AM34 VSS VSS

AM35 VDDO_B40 BEC

AM36 VSS VSS

AM37 VDDA_NOM_E EVDDA

AM38 RCOMP_TERM_B41 BWC

AM39 RCOMP_DRV_B41 BWC


AM40 PAD_EN_BYTEIO1_DQ0 BEN




AM44 PAD_EN_BYTEIO11_DQS BEN

AM45 PAD_EN_BYTEIO11_DQSN BEN



AM48 PAD_EC_BYTEIO5_DQ5 BEC








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AM7 PAD_WN_BYTEIO11_DQSN BWN

AM8 PAD_WN_BYTEIO11_DQS BWN


AN1 PAD_WC_BYTEIO6_DQ5 BWC

AN10 PAD_WN_BYTEIO10_DQS BWN

AN11 PAD_WN_BYTEIO1_DQSN BWN


AN13 RCOMP_TERM_B10 BEC

AN14 RCOMP_DRV_B10 BEC

AN15 VREF_B01 S12P75G

AN16 VDDO_B10 BWC

AN17 VDDO_B10 BWC

AN18 VSS VSS

AN19 VDDL CVDD


AN20 VDDL CVDD

AN21 VDDL CVDD

AN22 VDDL CVDD

AN23 VDDL CVDD

AN24 VDDL CVDD

AN25 VDDL CVDD

AN26 VCFG CFG

AN27 VCFGWL CFG

AN28 VDDL CVDD

AN29 VDDL CVDD


AN30 VDDL CVDD

AN31 VDDL CVDD

AN32 VDDL CVDD

AN33 VDDL CVDD

AN34 VSS VSS

AN35 VDDO_B40 BEC

AN36 VDDO_B40 BEC

AN37 VREF_B51 S12P75G

AN38 RCOMP_TERM_B40 BWC

AN39 RCOMP_DRV_B40 BWC


AN40 PAD_EN_BYTEIO1_DQS BEN




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AN41 PAD_EN_BYTEIO1_DQSN BEN



AN44 PAD_EN_BYTEIO11_DQ8 BEN

AN45 PAD_EN_BYTEIO11_DQ9 BEN



AN48 PAD_EC_BYTEIO5_DQ2 BEC






AN7 PAD_WN_BYTEIO11_DQ9 BWN

AN8 PAD_WN_BYTEIO11_DQ8 BWN


AP1 VSS VSS

AP10 PAD_WN_BYTEIO10_DQ6 BWN

AP11 VSS VSS


AP13 RCOMP_TERM_B02 BEN

AP14 RCOMP_DRV_B02 BEN

AP15 VDDA_NOM_W WVDDA

AP16 VDDO_B02 BWN

AP17 VDDO_B02 BWN

AP18 VCC SVDD

AP19 VSS VSS

AP2 PAD_WC_BYTEIO6_DQ3 BWC

AP20 VSS VSS

AP21 VSS VSS

AP22 VSS VSS

AP23 VSS VSS

AP24 VSS VSS

AP25 VSS VSS

AP26 VCFG CFG

AP27 VSS VSS

AP28 VSS VSS

AP29 VSS VSS

AP3 VSS VSS




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AP30 VSS VSS

AP31 VSS VSS

AP32 VSS VSS

AP33 VSS VSS

AP34 VCC SVDD

AP35 VDDO_B52 BEN

AP36 VDDO_B52 BEN

AP37 VDDA_NOM_E EVDDA

AP38 RCOMP_TERM_B52 BWS

AP39 RCOMP_DRV_B52 BWS

AP4 PAD_WC_BYTEIO5_DQ6 BWC

AP40 PAD_EN_BYTEIO1_DQ6 BEN

AP41 VSS VSS


AP43 VSS VSS


AP45 VSS VSS


AP47 VSS VSS

AP48 PAD_EC_BYTEIO5_DQ6 BEC

AP49 VSS VSS

AP5 VSS VSS

AP50 PAD_EC_BYTEIO6_DQ3 BEC

AP51 VSS VSS


AP7 VSS VSS


AP9 VSS VSS

AR1 PAD_WC_BYTEIO6_DQSN BWC

AR10 PAD_WN_BYTEIO10_DQ0 BWN



AR13 RCOMP_TERM_B01 BEN

AR14 RCOMP_DRV_B01 BEN

AR15 VREF_B00 S12P75G

AR16 VSS VSS

AR17 VDDO_B02 BWN

AR18 VCC SVDD

AR19 VCC SVDD




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AR2 PAD_WC_BYTEIO6_DQS BWC

AR20 VDD_BRAM VDD_BRAM

AR21 VSS VSS

AR22 VSS VSS

AR23 VSS VSS


AR25 VSS VSS

AR26 VSS VSS

AR27 VSS VSS


AR29 VSS VSS

AR3 PAD_WC_BYTEIO5_DQSN BWC

AR30 VSS VSS

AR31 VSS VSS


AR33 VCC SVDD

AR34 VCC SVDD

AR35 VDDO_B52 BEN

AR36 VSS VSS

AR37 VREF_B50 S12P75G

AR38 RCOMP_TERM_B51 BWS

AR39 RCOMP_DRV_B51 BWS

AR4 PAD_WC_BYTEIO5_DQS BWC

AR40 PAD_EN_BYTEIO1_DQ9 BEN








AR48 PAD_EC_BYTEIO5_DQS BEC

AR49 PAD_EC_BYTEIO5_DQSN BEC


AR50 PAD_EC_BYTEIO6_DQS BEC

AR51 PAD_EC_BYTEIO6_DQSN BEC







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AT1 PAD_WC_BYTEIO6_DQ2 BWC

AT10 PAD_WN_BYTEIO10_DQ2 BWN



AT13 RCOMP_TERM_B00 BEN

AT14 RCOMP_DRV_B00 BEN

AT15 VDDO_CBNW PLL_NW

AT16 VDDO_B02 BWN

AT17 VDDO_B02 BWN

AT18 VREF_CLK_BANK_NW PLL_NW

AT19 VCC SVDD


AT20 VCC SVDD

AT21 VCC SVDD

AT22 VCC SVDD

AT23 VCC SVDD

AT24 VCC SVDD

AT25 VCC SVDD

AT26 VCC SVDD

AT27 VCC SVDD

AT28 VCC SVDD

AT29 VCC SVDD


AT30 VCC SVDD

AT31 VCC SVDD

AT32 VCC SVDD

AT33 VCC SVDD

AT34 VREF_CLK_BANK_NE PLL_NE

AT35 VDDO_B52 BEN

AT36 VDDO_B52 BEN

AT37 VSS VSS

AT38 RCOMP_TERM_B50 BWS

AT39 RCOMP_DRV_B50 BWS


AT40 PAD_EN_BYTEIO1_DQ5 BEN







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AT48 PAD_EC_BYTEIO5_DQ0 BEC









AU1 PAD_WC_BYTEIO0_DQ1 BWC

AU10 PAD_WN_BYTEIO2_DQ7 BWN



AU13 VSS VSS

AU14 VSS VSS

AU15 VDDO_CBNW PLL_NW

AU16 VDDO_B01 BWN

AU17 VDDO_B01 BWN

AU18 VSS VSS

AU19 RCOMP_TERM_CLK_BANK_NW PLL_NW

AU2 PAD_WC_BYTEIO0_DQ8 BWC

AU20 VSS VSS

AU21 VSS VSS

AU22 VSS VSS

AU23 PA_VREG_RX VREG_RX

AU24 PA_VREG_SYNTHX VREG_SYNTHX

AU25 VSS VSS



AU28 VSS VSS




AU31 VSS VSS

AU32 VSS VSS




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AU33 RCOMP_TERM_CLK_BANK_NE PLL_NE

AU34 VSS VSS

AU35 VDDO_B51 BEN

AU36 VDDO_B51 BEN

AU37 VDDO_CBNE PLL_NE

AU38 VDDO_CBNE PLL_NE

AU39 VSS VSS


AU40 PAD_EN_BYTEIO0_DQ8 BEN











AU50 PAD_EC_BYTEIO0_DQ8 BEC

AU51 PAD_EC_BYTEIO0_DQ1 BEC





AV1 PAD_WC_BYTEIO0_DQ7 BWC

AV10 VSS VSS

AV11 PAD_WN_BYTEIO0_DQ7 BWN

AV12 VSS VSS

AV13 VSS VSS

AV14 PAD5_CLK_BANK_NW PLL_NW

AV15 VSS VSS

AV16 VSS VSS

AV17 VDDO_B01 BWN

AV18 VSS VSS

AV19 RCOMP_DRV_CLK_BANK_NW PLL_NW

AV2 VSS VSS

AV20 VSS VSS

AV21 VSS VSS




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AV22 VSS VSS

AV23 VSS VSS

AV24 PA_VREG_CMN VREG_CMN

AV25 VSS VSS

AV26 VSS VSS


AV28 VSS VSS

AV29 VSS VSS



AV31 VSS VSS

AV32 VSS VSS

AV33 RCOMP_DRV_CLK_BANK_NE PLL_NE

AV34 VSS VSS

AV35 VDDO_B51 BEN

AV36 VSS VSS

AV37 PAD4_CLK_BANK_NE PLL_NE

AV38 PAD5_CLK_BANK_NE PLL_NE

AV39 VSS VSS

AV4 VSS VSS

AV40 VSS VSS

AV41 PAD_EN_BYTEIO0_DQ7 BEN

AV42 VSS VSS


AV44 VSS VSS


AV46 VSS VSS


AV48 VSS VSS



AV50 VSS VSS

AV51 PAD_EC_BYTEIO0_DQ7 BEC

AV6 VSS VSS


AV8 VSS VSS


AW1 PAD_WC_BYTEIO0_DQ5 BWC

AW10 PAD_WN_BYTEIO2_DQ2 BWN




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AW11 PAD_WN_BYTEIO0_DQSN BWN

AW12 PAD_WN_BYTEIO0_DQS BWN

AW13 VSS VSS

AW14 PAD4_CLK_BANK_NW PLL_NW

AW15 VSS VSS

AW16 VDDO_B01 BWN

AW17 VDDO_B01 BWN

AW18 VSS VSS

AW19 VSS VSS

AW2 PAD_WC_BYTEIO0_DQ9 BWC

AW20 VSS VSS

AW21 VSS VSS

AW22 PAD_TE_I_BCK_REF_M_LNUM[0-1] N12P75G


AW24 VSS VSS



AW27 VSS VSS




AW30 VSS VSS



AW33 VSS VSS

AW34 VSS VSS

AW35 VDDO_B51 BEN

AW36 VDDO_B51 BEN

AW37 PAD2_CLK_BANK_NE PLL_NE

AW38 PAD3_CLK_BANK_NE PLL_NE

AW39 VSS VSS


AW40 PAD_EN_BYTEIO0_DQS BEN

AW41 PAD_EN_BYTEIO0_DQSN BEN

AW42 PAD_EN_BYTEIO2_DQ2 BEN








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AW50 PAD_EC_BYTEIO0_DQ9 BEC

AW51 PAD_EC_BYTEIO0_DQ5 BEC





AY1 PAD_WC_BYTEIO0_DQSN BWC

AY10 PAD_WN_BYTEIO2_DQS BWN

AY11 PAD_WN_BYTEIO0_DQ3 BWN

AY12 PAD_WN_BYTEIO0_DQ2 BWN

AY13 VSS VSS

AY14 PAD3_CLK_BANK_NW PLL_NW

AY15 VSS VSS

AY16 VDDO_B00 BWN

AY17 VDDO_B00 BWN

AY18 VSS VSS

AY19 VSS VSS

AY2 PAD_WC_BYTEIO0_DQS BWC

AY20 VSS VSS

AY21 VSS VSS

AY22 PAD_TE_I_BCK_REF_P_LNUM[0-1] N12P75G


AY24 VSS VSS



AY27 VSS VSS



AY3 PAD_WN_BYTEIO9_DQSN BWN

AY30 VSS VSS



AY33 VSS VSS

AY34 VSS VSS

AY35 VDDO_B50 BEN




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AY36 VDDO_B50 BEN

AY37 PAD0_CLK_BANK_NE PLL_NE

AY38 PAD1_CLK_BANK_NE PLL_NE

AY39 VSS VSS


AY40 PAD_EN_BYTEIO0_DQ2 BEN

AY41 PAD_EN_BYTEIO0_DQ3 BEN

AY42 PAD_EN_BYTEIO2_DQS BEN

AY43 PAD_EN_BYTEIO2_DQSN BEN








AY50 PAD_EC_BYTEIO0_DQS BEC

AY51 PAD_EC_BYTEIO0_DQSN BEC





B1 VSS VSS

B10 VSS VSS

B11 PAD_BE_O_BA_TX_P_LNUM0 S12P75G

B12 PAD_BE_O_BA_TX_M_LNUM1 S12P75G








B2 PAD_WS_BYTEIO10_DQ1 BWS









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B43 VSS VSS

B44 PAD_ES_BYTEIO12_DQ9 BES








B51 VSS VSS




B9 EDM

BA1 VSS VSS

BA10 PAD_WN_BYTEIO2_DQ0 BWN

BA11 VSS VSS


BA13 VSS VSS




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BA14 PAD2_CLK_BANK_NW PLL_NW

BA15 VSS VSS

BA16 VSS VSS

BA17 VDDO_B00 BWN

BA18 VSS VSS

BA19 VSS VSS

BA2 PAD_WC_BYTEIO0_DQ6 BWC

BA20 VSS VSS

BA21 VSS VSS

BA22 VSS VSS

BA23 VSS VSS

BA24 VSS VSS

BA25 VSS VSS

BA26 VSS VSS

BA27 VSS VSS

BA28 VSS VSS

BA29 VSS VSS

BA3 VSS VSS

BA30 VSS VSS

BA31 VSS VSS

BA32 VSS VSS

BA33 VSS VSS

BA34 VSS VSS

BA35 VDDO_B50 BEN

BA36 VSS VSS

BA37 VSS VSS

BA38 VSS VSS

BA39 VSS VSS


BA40 PAD_EN_BYTEIO0_DQ0 BEN

BA41 VSS VSS


BA43 VSS VSS


BA45 VSS VSS


BA47 VSS VSS


BA49 VSS VSS




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BA5 VSS VSS

BA50 PAD_EC_BYTEIO0_DQ6 BEC

BA51 VSS VSS


BA7 VSS VSS


BA9 VSS VSS

BB1 PAD_WC_BYTEIO0_DQ3 BWC

BB10 PAD_WN_BYTEIO2_DQ6 BWN



BB13 VSS VSS

BB14 PAD1_CLK_BANK_NW PLL_NW

BB15 VSS VSS

BB16 VDDO_B00 BWN

BB17 VDDO_B00 BWN

BB18 VSS VSS

BB19 AVDD_PLL_NW3 PLL_NW

BB2 PAD_WC_BYTEIO0_DQ2 BWC

BB20 AVDD_PLL_NW2 PLL_NW

BB21 VSS VSS

BB22 PAD_TE_I_BCK_REF_M_LNUM[4-5] N12P75G


BB24 VSS VSS



BB27 VSS VSS




BB30 VSS VSS



BB33 VSS VSS

BB34 VSS VSS

BB35 VDDO_B50 BEN

BB36 VDDO_B50 BEN

BB37 AVDD_PLL_NE3 PLL_NE

BB38 AVDD_PLL_NE2 PLL_NE




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BB39 VSS VSS


BB40 PAD_EN_BYTEIO0_DQ1 BEN











BB50 PAD_EC_BYTEIO0_DQ2 BEC

BB51 PAD_EC_BYTEIO0_DQ3 BEC





BC1 PAD_WC_BYTEIO0_DQ4 BWC

BC10 PAD_WN_BYTEIO2_DQ3 BWN



BC13 VSS VSS

BC14 PAD0_CLK_BANK_NW PLL_NW

BC15 VSS VSS

BC16 VSS VSS

BC17 VSS VSS

BC18 VSS VSS

BC19 AVDD_PLL_NW1 PLL_NW

BC2 PAD_WC_BYTEIO0_DQ0 BWC

BC20 AVDD_PLL_NW0 PLL_NW

BC21 VSS VSS

BC22 PAD_TE_I_BCK_REF_P_LNUM[4-5] N12P75G


BC24 PAD_TE_I_A_RXTERMV_LNUM[12-15] N12P75G







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BC30 VSS VSS



BC33 VSS VSS

BC34 VSS VSS


BC36 VSS VSS

BC37 AVDD_PLL_NE1 PLL_NE

BC38 AVDD_PLL_NE0 PLL_NE



BC40 PAD_EN_BYTEIO0_DQ5 BEN











BC50 PAD_EC_BYTEIO0_DQ0 BEC

BC51 PAD_EC_BYTEIO0_DQ4 BEC





BD1 PAD_WN_BYTEIO8_DQ5 BWN

BD10 VSS VSS

BD11 PAD_TE_O_BA_APROBE_LNUM[0-3] N12P75G

BD12 VSS VSS

BD13 PAD_TE_I_A_RXTERMV_LNUM[0-3] N12P75G

BD14 VSS VSS


BD16 VSS VSS




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BD18 VSS VSS



BD20 VSS VSS


BD22 VSS VSS


BD24 VSS VSS

BD25 VSS VSS

BD26 VSS VSS


BD28 VSS VSS

BD29 VSS VSS


BD30 VSS VSS


BD32 VSS VSS


BD34 VSS VSS


BD36 VSS VSS

BD37 VSS VSS

BD38 VSS VSS



BD40 VSS VSS

BD41 VSS VSS

BD42 VSS VSS

BD43 VSS VSS

BD44 PAD_EN_BYTEIO3_DQ3 BEN












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BD9 VSS VSS

BE1 PAD_WN_BYTEIO8_DQ9 BWN

BE10 VSS VSS

BE11 PA_VDD2 N12P75G

BE12 PAD_TE_I_BA_RX_P_LNUM1 N12P75G






























BE4 VSS VSS





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BE43 VSS VSS

BE44 VSS VSS

BE45 PAD_EN_BYTEIO3_DQ7 BEN

BE46 VSS VSS


BE48 VSS VSS





BE6 VSS VSS


BE8 VSS VSS

BE9 VSS VSS

BF1 VSS VSS

BF10 VSS VSS

BF11 PAD_TE_I_BA_RX_P_LNUM0 N12P75G

BF12 PAD_TE_I_BA_RX_M_LNUM1 N12P75G








BF2 PAD_WN_BYTEIO8_DQ3 BWN











BF3 PAD_WN_BYTEIO7_DQSN BWN




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BF4 PAD_WN_BYTEIO7_DQS BWN




BF43 VSS VSS

BF44 PAD_EN_BYTEIO3_DQ2 BEN




BF48 PAD_EN_BYTEIO7_DQS BEN

BF49 PAD_EN_BYTEIO7_DQSN BEN



BF51 VSS VSS




BF9 VSS VSS

BG1 PAD_WN_BYTEIO8_DQSN BWN

BG10 VSS VSS

BG11 PAD_TE_I_BA_RX_M_LNUM0 N12P75G

BG12 PA_VDD2 N12P75G











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BG2 PAD_WN_BYTEIO8_DQS BWN











BG3 PAD_WN_BYTEIO7_DQ4 BWN















BG43 VSS VSS

BG44 PAD_EN_BYTEIO3_DQS BEN

BG45 PAD_EN_BYTEIO3_DQSN BEN

BG46 PAD_EN_BYTEIO6_DQ2 BEN





BG50 PAD_EN_BYTEIO8_DQS BEN

BG51 PAD_EN_BYTEIO8_DQSN BEN


BG7 PAD_WN_BYTEIO3_DQSN BWN

BG8 PAD_WN_BYTEIO3_DQS BWN




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BG9 VSS VSS

BH1 PAD_WN_BYTEIO8_DQ2 BWN

BH10 VSS VSS

BH11 VSS VSS

BH12 VSS VSS

BH13 VSS VSS

BH14 VSS VSS

BH15 VSS VSS

BH16 VSS VSS

BH17 VSS VSS

BH18 VSS VSS

BH19 VSS VSS


BH20 VSS VSS

BH21 VSS VSS

BH22 VSS VSS

BH23 VSS VSS

BH24 VSS VSS

BH25 VSS VSS

BH26 VSS VSS

BH27 VSS VSS

BH28 VSS VSS

BH29 VSS VSS

BH3 VSS VSS

BH30 VSS VSS

BH31 VSS VSS

BH32 VSS VSS

BH33 VSS VSS

BH34 VSS VSS

BH35 VSS VSS

BH36 VSS VSS

BH37 VSS VSS

BH38 VSS VSS

BH39 VSS VSS


BH40 VSS VSS

BH41 VSS VSS

BH42 VSS VSS

BH43 VSS VSS




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BH44 PAD_EN_BYTEIO3_DQ0 BEN

BH45 VSS VSS


BH47 VSS VSS


BH49 VSS VSS

BH5 VSS VSS




BH7 VSS VSS


BH9 VSS VSS

BJ1 VSS VSS

BJ10 VSS VSS

BJ11 PAD_TE_O_BA_TX_M_LNUM0 N12P75G

BJ12 PA_VDD1 N12P75G








BJ2 PAD_WN_BYTEIO8_DQ1 BWN


















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BJ43 VSS VSS

BJ44 PAD_EN_BYTEIO3_DQ1 BEN


BJ46 PAD_EN_BYTEIO6_DQS BEN

BJ47 PAD_EN_BYTEIO6_DQSN BEN



BJ5 PAD_WN_BYTEIO6_DQSN BWN


BJ51 VSS VSS

BJ6 PAD_WN_BYTEIO6_DQS BWN



BJ9 VSS VSS

BK1 VSS VSS

BK10 VSS VSS

BK11 PAD_TE_O_BA_TX_P_LNUM0 N12P75G

BK12 PAD_TE_O_BA_TX_M_LNUM1 N12P75G








BK2 PAD_WN_BYTEIO8_DQ6 BWN






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BK43 VSS VSS

BK44 PAD_EN_BYTEIO3_DQ4 BEN








BK51 VSS VSS




BK9 VSS VSS

BL1 NB NB

BL10 VSS VSS




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BL11 PA_VDD1 N12P75G

BL12 PAD_TE_O_BA_TX_P_LNUM1 N12P75G








BL2 VSS VSS











BL3 VSS VSS











BL4 PAD_WN_BYTEIO7_DQ7 BWN


BL41 PA_VDD1 S12P75G


BL43 VSS VSS

BL44 VSS VSS

BL45 VSS VSS

BL46 VSS VSS




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BL47 VSS VSS

BL48 PAD_EN_BYTEIO7_DQ1 BEN

BL49 VSS VSS

BL5 VSS VSS

BL50 VSS VSS

BL51 NB NB

BL6 VSS VSS

BL7 VSS VSS

BL8 VSS VSS

BL9 VSS VSS

C1 VSS VSS

C10 VSS VSS

C11 PAD_BE_O_BA_TX_M_LNUM0 S12P75G

C12 PA_VDD1 S12P75G


C14 PA_VDD1 S12P75G


C16 PA_VDD1 S12P75G


C18 PA_VDD1 S12P75G


C2 PAD_WS_BYTEIO10_DQ6 BWS

C20 PA_VDD1 S12P75G


C22 PA_VDD1 S12P75G


C24 PA_VDD1 S12P75G


C26 PA_VDD1 S12P75G


C28 PA_VDD1 S12P75G



C30 PA_VDD1 S12P75G


C32 PA_VDD1 S12P75G


C34 PA_VDD1 S12P75G





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C36 PA_VDD1 S12P75G


C38 PA_VDD1 S12P75G


C4 VSS VSS

C40 PA_VDD1 S12P75G


C42 PA_VDD1 N12P75G

C43 VSS VSS

C44 VSS VSS

C45 PAD_ES_BYTEIO12_DQ1 BES

C46 VSS VSS


C48 VSS VSS




C51 VSS VSS

C6 VSS VSS


C8 VSS VSS

C9 VCCRAM_EFUSE3 EFUSE

D1 PAD_WS_BYTEIO10_DQS BWS

D10 VSS VSS

D11 VSS VSS

D12 VSS VSS

D13 VSS VSS

D14 VSS VSS

D15 VSS VSS

D16 VSS VSS

D17 VSS VSS

D18 VSS VSS

D19 VSS VSS

D2 PAD_WS_BYTEIO10_DQSN BWS

D20 VSS VSS

D21 VSS VSS

D22 VSS VSS

D23 VSS VSS

D24 VSS VSS




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D25 VSS VSS

D26 VSS VSS

D27 VSS VSS

D28 VSS VSS

D29 VSS VSS

D3 PAD_WS_BYTEIO9_DQ5 BWS

D30 VSS VSS

D31 VSS VSS

D32 VSS VSS

D33 VSS VSS

D34 VSS VSS

D35 VSS VSS

D36 VSS VSS

D37 VSS VSS

D38 VSS VSS

D39 VSS VSS

D4 PAD_WS_BYTEIO9_DQ4 BWS

D40 VSS VSS

D41 VSS VSS

D42 VSS VSS

D43 VSS VSS

D44 PAD_ES_BYTEIO12_DQSN BES

D45 PAD_ES_BYTEIO12_DQS BES



D48 PAD_ES_BYTEIO9_DQ4 BES

D49 PAD_ES_BYTEIO9_DQ5 BES







D9 VCCFHV_EFUSE3 EFUSE

E1 PAD_WS_BYTEIO10_DQ2 BWS

E10 VSS VSS

E11 PAD_BE_I_BA_RX_M_LNUM0 S12P75G

E12 PA_VDD2 S12P75G





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E14 PA_VDD2 S12P75G


E16 PA_VDD2 S12P75G


E18 PA_VDD2 S12P75G



E20 PA_VDD2 S12P75G


E22 PA_VDD2 S12P75G


E24 PA_VDD2 S12P75G


E26 PA_VDD2 S12P75G


E28 PA_VDD2 S12P75G



E30 PA_VDD2 S12P75G


E32 PA_VDD2 S12P75G


E34 PA_VDD2 S12P75G


E36 PA_VDD2 S12P75G


E38 PA_VDD2 S12P75G



E40 PA_VDD2 S12P75G


E42 PA_VDD2 S12P75G

E43 VSS VSS

E44 PAD_ES_BYTEIO12_DQ3 BES









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E9 VCCRAM_EFUSE2 EFUSE

F1 VSS VSS

F10 VSS VSS

F11 PAD_BE_I_BA_RX_P_LNUM0 S12P75G

F12 PAD_BE_I_BA_RX_M_LNUM1 S12P75G








F2 PAD_WS_BYTEIO10_DQ8 BWS











F3 VSS VSS













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F43 VSS VSS

F44 PAD_ES_BYTEIO12_DQ8 BES

F45 VSS VSS


F47 VSS VSS


F49 VSS VSS

F5 VSS VSS


F51 VSS VSS


F7 VSS VSS


F9 VCCFHV_EFUSE2 EFUSE

G1 PAD_WS_BYTEIO10_DQ7 BWS

G10 VSS VSS

G11 PA_VDD2 S12P75G

G12 PAD_BE_I_BA_RX_P_LNUM1 S12P75G

G13 PA_VDD2 S12P75G


G15 PA_VDD2 S12P75G


G17 PA_VDD2 S12P75G


G19 PA_VDD2 S12P75G



G21 PA_VDD2 S12P75G


G23 PA_VDD2 S12P75G


G25 PA_VDD2 S12P75G


G27 PA_VDD2 S12P75G




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G29 PA_VDD2 S12P75G

G3 PAD_WS_BYTEIO9_DQS BWS


G31 PA_VDD2 S12P75G


G33 PA_VDD2 S12P75G


G35 PA_VDD2 S12P75G


G37 PA_VDD2 S12P75G


G39 PA_VDD2 S12P75G

G4 PAD_WS_BYTEIO9_DQSN BWS


G41 PA_VDD2 S12P75G


G43 VSS VSS

G44 PAD_ES_BYTEIO12_DQ7 BES




G48 PAD_ES_BYTEIO9_DQSN BES

G49 PAD_ES_BYTEIO9_DQS BES







G9 VCCRAM_EFUSE1 EFUSE

H1 PAD_WS_BYTEIO10_DQ0 BWS

H10 VSS VSS

H11 PAD_BE_O_BA_APROBE_LNUM[0-3] S12P75G

H12 VSS VSS

H13 PAD_BE_I_A_RXTERMV_LNUM[0-3] S12P75G

H14 VSS VSS


H16 VSS VSS




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H18 VSS VSS



H20 VSS VSS


H22 VSS VSS


H24 VSS VSS


H26 VSS VSS


H28 VSS VSS



H30 VSS VSS


H32 VSS VSS


H34 VSS VSS


H36 VSS VSS


H38 VSS VSS



H40 VSS VSS

H41 VSS VSS

H42 VSS VSS

H43 VSS VSS

H44 PAD_ES_BYTEIO12_DQ5 BES












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H9 VCCFHV_EFUSE1 EFUSE

J1 PAD_WS_BYTEIO4_DQ9 BWS




J13 TCK JTAG

J14 CONFIG_RSTN CFG

J15 CSN1 CFG

J16 CONFIG_DONE CFG

J17 CONFIG_MODESEL2 CFG

J18 BYPASS_CLR_MEM CFG

J19 TMS JTAG


J20 CONFIG_SCRUB_SINGLE_ERR CFG

J21 VSS VSS

J22 AVDD_PLL_SW3 PLL_SW

J23 AVDD_PLL_SW2 PLL_SW

J24 VSS VSS

J25 PAD_BE_I_BCK_REF_P_LNUM[4-5] S12P75G


J27 VSS VSS




J30 VSS VSS



J33 VSS VSS



J36 VSS VSS

J37 AVDD_PLL_SE3 PLL_SE

J38 AVDD_PLL_SE2 PLL_SE

J39 PAD_BE_I_A_RXTERMV_LNUM[28-31] S12P75G


J40 PAD_ES_BYTEIO8_DQ4 BES




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K1 PAD_WS_BYTEIO4_DQ7 BWS

K10 VSS VSS


K12 VSS VSS

K13 HOLDN CFG

K14 START_CFG_STARTUP CFG

K15 PROGRAM_ENABLE0 CFG

K16 TDO JTAG

K17 TDI JTAG

K18 CPU_CLK CFG

K19 CONFIG_SCRUBBING_ENABLE CFG

K2 VSS VSS

K20 CORE_TESTIN1 DBG

K21 VSS VSS

K22 AVDD_PLL_SW1 PLL_SW

K23 AVDD_PLL_SW0 PLL_SW

K24 VSS VSS

K25 PAD_BE_I_BCK_REF_M_LNUM[4-5] S12P75G


K27 VSS VSS







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K30 VSS VSS



K33 VSS VSS



K36 VSS VSS

K37 AVDD_PLL_SE1 PLL_SE

K38 AVDD_PLL_SE0 PLL_SE

K39 VSS VSS

K4 VSS VSS

K40 VSS VSS

K41 PAD_ES_BYTEIO8_DQ2 BES

K42 VSS VSS


K44 VSS VSS


K46 VSS VSS


K48 VSS VSS



K50 VSS VSS


K6 VSS VSS


K8 VSS VSS


L1 PAD_WS_BYTEIO4_DQ5 BWS




L13 SDI CFG

L14 SD3 CFG

L15 VDDO_JCFG CFG

L16 TRSTN JTAG

L17 CONFIG_MODESEL0 CFG

L18 CONFIG_MODESEL1 CFG

L19 STAP_SEL CFG




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L20 VSS VSS

L21 VSS VSS

L22 VSS VSS

L23 VSS VSS

L24 VSS VSS

L25 VSS VSS

L26 VSS VSS

L27 VSS VSS

L28 VSS VSS

L29 VSS VSS


L30 VSS VSS

L31 VSS VSS

L32 VSS VSS

L33 VSS VSS

L34 VSS VSS

L35 VSS VSS

L36 VSS VSS

L37 VSS VSS

L38 VSS VSS

L39 VSS VSS


L40 PAD_ES_BYTEIO8_DQ5 BES






L46 PAD_ES_BYTEIO5_DQSN BES

L47 PAD_ES_BYTEIO5_DQS BES



L5 PAD_WS_BYTEIO5_DQS BWS



L6 PAD_WS_BYTEIO5_DQSN BWS






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M1 PAD_WS_BYTEIO4_DQS BWS

M10 PAD_WS_BYTEIO7_DQ1 BWS



M13 SD2 CFG

M14 SD1 CFG

M15 VDDO_JCFG CFG

M16 CONFIG_STATUS CFG

M17 CONFIG_CLKSEL CFG

M18 VSS VSS

M19 PROGRAM_ENABLE1 CFG

M2 PAD_WS_BYTEIO4_DQSN BWS

M20 CONFIG_SCRUB_MULTIPLE_ERR CFG

M21 VSS VSS

M22 VSS VSS

M23 VSS VSS

M24 VSS VSS

M25 PAD_BE_I_BCK_REF_P_LNUM[0-1] S12P75G


M27 VSS VSS




M30 VSS VSS



M33 VSS VSS



M36 VSS VSS

M37 PAD0_CLK_BANK_SE PLL_SE

M38 PAD1_CLK_BANK_SE PLL_SE

M39 VSS VSS


M40 PAD_ES_BYTEIO8_DQ1 BES







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M44 PAD_ES_BYTEIO6_DQSN BES

M45 PAD_ES_BYTEIO6_DQS BES






M50 PAD_ES_BYTEIO4_DQSN BES

M51 PAD_ES_BYTEIO4_DQS BES


M7 PAD_WS_BYTEIO6_DQS BWS

M8 PAD_WS_BYTEIO6_DQSN BWS


N1 VSS VSS

N10 PAD_WS_BYTEIO7_DQ4 BWS

N11 VSS VSS


N13 SCK CFG

N14 SD0 CFG

N15 VSS VSS

N16 READ_STATE_ERR CFG

N17 CSN2 CFG

N18 CONFIG_SYS_CLK_BYPASS CFG

N19 CSN3 CFG


N20 CSN0 CFG

N21 VSS VSS

N22 VSS VSS

N23 VSS VSS

N24 VSS VSS

N25 PAD_BE_I_BCK_REF_M_LNUM[0-1] S12P75G


N27 VSS VSS



N3 VSS VSS

N30 VSS VSS






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N33 VSS VSS



N36 VSS VSS

N37 PAD2_CLK_BANK_SE PLL_SE

N38 PAD3_CLK_BANK_SE PLL_SE

N39 VSS VSS


N40 PAD_ES_BYTEIO8_DQ6 BES

N41 VSS VSS


N43 VSS VSS


N45 VSS VSS


N47 VSS VSS


N49 VSS VSS

N5 VSS VSS


N51 VSS VSS


N7 VSS VSS


N9 VSS VSS

P1 PAD_WS_BYTEIO4_DQ4 BWS

P10 PAD_WS_BYTEIO7_DQSN BWS

P11 PAD_WS_BYTEIO8_DQS BWS


P13 VSS VSS

P14 PAD5_CLK_BANK_SW PLL_SW







P20 VSS VSS

P21 RCOMP_DRV_CLK_BANK_SW PLL_SW




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P22 VSS VSS

P23 VSS VSS

P24 PA_VREG_CMN VREG_CMN

P25 VSS VSS

P26 VSS VSS


P28 VSS VSS

P29 VSS VSS



P31 VSS VSS

P32 VSS VSS

P33 RCOMP_DRV_CLK_BANK_SE PLL_SE

P34 VSS VSS

P35 VSS VSS

P36 VDDO_CBSE PLL_SE

P37 PAD4_CLK_BANK_SE PLL_SE

P38 PAD5_CLK_BANK_SE PLL_SE

P39 VSS VSS


P40 PAD_ES_BYTEIO8_DQSN BES

P41 PAD_ES_BYTEIO8_DQS BES



P44 PAD_ES_BYTEIO6_DQ3 BES













R1 PAD_WS_BYTEIO4_DQ2 BWS





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R13 VSS VSS

R14 VSS VSS

R15 VSS VSS

R16 VSS VSS

R17 VSS VSS

R18 VDDO_CBSW PLL_SW

R19 VDDO_CBSW PLL_SW


R20 VSS VSS

R21 RCOMP_TERM_CLK_BANK_SW PLL_SW

R22 VSS VSS

R23 PA_VREG_RX VREG_RX

R24 PA_VREG_SYNTHX VREG_SYNTHX

R25 VSS VSS



R28 VSS VSS




R31 VSS VSS

R32 VSS VSS

R33 RCOMP_TERM_CLK_BANK_SE PLL_SE

R34 VSS VSS

R35 VSS VSS

R36 VSS VSS

R37 VDDO_CBSE PLL_SE

R38 TEMP_DIODE_N TEMP

R39 TEMP_DIODE_P TEMP


R40 PAD_ES_BYTEIO8_DQ8 BES










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T1 PAD_WC_BYTEIO11_DQ8 BWC

T10 PAD_WS_BYTEIO2_DQ7 BWS



T13 VSS VSS

T14 EFUSE_PROG EFUSE

T15 VSS VSS

T16 VDDO_B22 BWS

T17 VDDO_B22 BWS

T18 VREF_CLK_BANK_SW PLL_SW

T19 VCC SVDD


T20 VCC SVDD

T21 VCC SVDD

T22 VCC SVDD

T23 VCC SVDD

T24 VCC SVDD

T25 VCC SVDD

T26 VCC SVDD

T27 VCC SVDD

T28 VCC SVDD

T29 VCC SVDD


T30 VCC SVDD

T31 VCC SVDD

T32 VCC SVDD

T33 VCC SVDD

T34 VREF_CLK_BANK_SE PLL_SE

T35 VDDO_B32 BES




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T36 VDDO_B32 BES

T37 VSS VSS

T38 VSS VSS

T39 VSS VSS


T40 PAD_ES_BYTEIO0_DQ8 BES




T44 PAD_EC_BYTEIO12_DQ5 BEC













U1 PAD_WC_BYTEIO11_DQ7 BWC

U10 VSS VSS

U11 PAD_WS_BYTEIO0_DQ5 BWS

U12 VSS VSS

U13 VSS VSS

U14 VSS VSS

U15 VSS VSS

U16 VSS VSS

U17 VDDO_B22 BWS

U18 VCC SVDD

U19 VCC SVDD

U2 VSS VSS

U20 VDDL CVDD

U21 VDDL CVDD

U22 VDDL CVDD

U23 VDDL CVDD

U24 VSS VSS




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U25 VSS VSS

U26 VCFG CFG

U27 VCFGWL CFG

U28 VSS VSS

U29 VSS VSS


U30 VDDL CVDD

U31 VDDL CVDD

U32 VDDL CVDD

U33 VCC SVDD

U34 VCC SVDD

U35 VDDO_B32 BES

U36 VSS VSS

U37 VSS VSS

U38 VSS VSS

U39 VSS VSS

U4 VSS VSS

U40 VSS VSS

U41 PAD_ES_BYTEIO0_DQ5 BES

U42 VSS VSS


U44 VSS VSS

U45 PAD_EC_BYTEIO12_DQ9 BEC

U46 VSS VSS


U48 VSS VSS



U50 VSS VSS


U6 VSS VSS


U8 VSS VSS


V1 PAD_WC_BYTEIO11_DQ5 BWC

V10 PAD_WS_BYTEIO2_DQSN BWS

V11 PAD_WS_BYTEIO0_DQ6 BWS


V13 VSS VSS




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V14 VSS VSS

V15 VDDA_NOM_W WVDDA

V16 VDDO_B22 BWS

V17 VDDO_B22 BWS

V18 VCC SVDD

V19 VSS VSS


V20 VSS VSS

V21 VSS VSS

V22 VSS VSS

V23 VSS VSS

V24 VSS VSS

V25 VSS VSS

V26 VCFG CFG

V27 VSS VSS

V28 VSS VSS

V29 VSS VSS


V30 VSS VSS

V31 VSS VSS

V32 VSS VSS

V33 VSS VSS

V34 VCC SVDD

V35 VDDO_B32 BES

V36 VDDO_B32 BES

V37 VDDA_NOM_E EVDDA

V38 VSS VSS

V39 VSS VSS


V40 PAD_ES_BYTEIO0_DQ9 BES


V42 PAD_ES_BYTEIO2_DQSN BES

V43 PAD_ES_BYTEIO2_DQS BES

V44 PAD_EC_BYTEIO12_DQ6 BEC









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V9 PAD_WS_BYTEIO2_DQS BWS

W1 PAD_WC_BYTEIO11_DQS BWC

W10 PAD_WS_BYTEIO2_DQ5 BWS

W11 PAD_WS_BYTEIO0_DQS BWS

W12 PAD_WS_BYTEIO0_DQSN BWS

W13 VSS VSS

W14 VSS VSS

W15 VREF_B22 S12P75G

W16 VDDO_B21 BWS

W17 VDDO_B21 BWS

W18 VSS VSS

W19 VDDL CVDD

W2 PAD_WC_BYTEIO11_DQSN BWC

W20 VDD_BRAM VDD_BRAM

W21 VDDL CVDD

W22 VDDL CVDD

W23 VDDL CVDD


W25 VDDL CVDD

W26 VDDL CVDD

W27 VDDL CVDD


W29 VDDL CVDD


W30 VDDL CVDD

W31 VDDL CVDD


W33 VDDL CVDD

W34 VSS VSS

W35 VDDO_B31 BES

W36 VDDO_B31 BES

W37 VREF_B32 S12P75G

W38 VSS VSS




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W39 VSS VSS


W40 PAD_ES_BYTEIO0_DQSN BES

W41 PAD_ES_BYTEIO0_DQS BES

W42 PAD_ES_BYTEIO2_DQ5 BES


W44 PAD_EC_BYTEIO12_DQ7 BEC






W5 PAD_WC_BYTEIO10_DQ5 BWC

W50 PAD_EC_BYTEIO11_DQSN BEC

W51 PAD_EC_BYTEIO11_DQS BEC





Y1 VSS VSS

Y10 PAD_WS_BYTEIO2_DQ4 BWS

Y11 VSS VSS


Y13 RCOMP_DRV_B22 BES

Y14 RCOMP_TERM_B22 BES

Y15 VDDA_NOM_W WVDDA

Y16 VSS VSS

Y17 VDDO_B21 BWS

Y18 VSS VSS

Y19 VSS VSS

Y2 PAD_WC_BYTEIO11_DQ1 BWC

Y20 VSS VSS

Y21 VSS VSS

Y22 VSS VSS

Y23 VSS VSS

Y24 VSS VSS

Y25 VSS VSS

Y26 VSS VSS

Y27 VSS VSS




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Y28 VSS VSS

Y29 VSS VSS

Y3 VSS VSS

Y30 VSS VSS

Y31 VSS VSS

Y32 VSS VSS

Y33 VSS VSS

Y34 VSS VSS

Y35 VDDO_B31 BES

Y36 VSS VSS

Y37 VDDA_NOM_E EVDDA

Y38 RCOMP_DRV_B32 BWN

Y39 RCOMP_TERM_B32 BWN


Y40 PAD_ES_BYTEIO0_DQ7 BES

Y41 VSS VSS


Y43 VSS VSS

Y44 PAD_EC_BYTEIO12_DQ4 BEC

Y45 VSS VSS


Y47 VSS VSS


Y49 VSS VSS

Y5 VSS VSS


Y51 VSS VSS


Y7 VSS VSS


Y9 VSS VSS




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Ordering Information Speedster22i HD FPGA Family

Ordering Information

Device

Company ID

Modifier

Package Type

Speed Grade

Package Size Temperature GradeC = 0°C to +70°CI = –40°C to +85°C

A C 2 2 I H D 1 0 0 0 – F 5 3 C 3 E S

HD210, HD680, HD1000, HD1500

F = Fine Ball Grid Array

ds001_33_v06

Family

53 = 52.5 x 52.5, 2597 Pin Package45 = 45 x 45, 1936 Pin Package

ES = Engineering Samples

1 = Fastest2 3


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DS004 Rev. 1.8– Sept 24, 2012 Speedster22i HD FPGA Family

Revision HistoryThe following table lists the revision history of this document.

Version Revision

1.5 Initial public release

1.6 Minor Updates and Corrections

1.7 Updated part numbers. Updated Pin listing to G32375-001_r1p0 release. Updated figure 28.

1.8 Updated Voltages and tolerance information. Updates device resource counts.

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Achronix Semiconductor Corporation

2953 Bunker Hill Lane, Suite 101Santa Clara, CA, 95045USA

Phone : 877.GHZ.FPGA (877.449.3742)Fax : 408.286.3645E‐mail : [email protected]

Copyright © 2012 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation. All othertrademarks are the property of their prospective owners. All specifications subject to change without notice.

NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable. However, Achronix Semiconductor Corporation does not give any representationsor warranties as to the completeness or accuracy of such information and shall have no liability for the use of the information contained herein. Achronix Semiconductor Corporation reservesthe right to make changes to this document and the information contained herein at any time and without notice. All Achronix trademarks, registered trademarks, and disclaimers are listedat http://www.achronix.com and use of this document and the Information contained therein is subject to such terms.

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mailto:[email protected]

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Documents

Speedster22i HD FPGA Family