SpectreRF Workshop

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January 2010 Product Version 7.2.0

SpectreRF Workshop

Noise Aware PLL Design Flow

MMSIM 7.2.0

January 2010


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January 2010 Product Version 7.2.0 2

Contents

Introduction to Noise-Aware PLL Design Flow ...........................................................................3

Downloading GPDK180 .............................................................................................................6

Integer-N PLL design flow........................................................................................................10

Creating a CMI Model for the VCO/Divider..............................................................................10

Creating a Model for the PFD/CP..............................................................................................20

(optional) Creating a Model for the Divider ...............................................................................28

Fractional-N PLL Design Flow .................................................................................................51

Creating a CMI Model for the VCO/Divider..............................................................................51

Creating a Model for the PFD/CP..............................................................................................57

Simulating a Fractional-N PLL..................................................................................................57

Noise Aware PLL flow FAQs ...................................................................................................66


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Introduction to Noise-Aware PLL Design

Flow

Phase-locked loops (PLLs) are used to implement a variety of timing-related functions,

such as frequency synthesis, clock and data recovery, and clock de-skewing. Any jitter or

phase noise in the output of the PLL degrades the performance margins of the system in

which they are used and so are of great concern to designers. Jitter and phase noise are

different ways of referring to an undesired variation in the timing of events at the output

of the PLL. They are difficult to predict with traditional circuit simulators because the

PLL generates repetitive switching events as an essential part of its operation, and the

noise performance must be evaluated in the presence of this large-signal behavior.

The Spectre RF MMSIM 6.2 release introduces a tool for predicting the phase noise of a

PLL-based frequency synthesizer using a simulation method that is both accurate and

efficient. The methodology first partitions the PLL design into a few basic building

blocks, then uses transistor-level RF noise simulation to characterize the phase noise

behavior of the blocks that make up the PLL. For each block, the phase noise is extracted

and applied to a phase-domain model for the entire PLL. The next figure illustrates the

idea.


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As an example, the following PLL design is partitioned into a few building blocks:

VCO+Divider, PFD+CP, and the LPF, which is usually an out-of-chip component.

RVPF CP VCO

N÷FV

Closed Loop PLL Noise

100 nV/ √ H 200 nV/ √ H

500 nV/ √ H 1 µ V √ H 2 µ V √ H

5 µ V √ H 10 µ V √ H 20 µ V

√ H

50 µ V √ H

1 10 100 1 MHz 10 100

Automatically

generate model

Compute

Jitter

PSS-PNoise

ADE testbench and

Analysis


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Spectre RF provides a collection of testbenches for the partitioned building blocks. The

specialized VCO/Prescaler testbench supports single-ended VCO outputs, phase

sensitivity to tuning voltage, and positive or negative power supply connects. The simple

divide by N is built-in for a faster simulation but does not carry noise properties. The

PFD and CP are combined together in the same testbench. Only a tri-state PFD circuit

topology is supported. Fundamentally, the models are single-ended and produce voltages.

There are two types of models created: C Model Interface (CMI) models, which are not

editable or viewable, and Verilog-A modules, which are viewable and editable. The

VCO/Prescaler model in this workshop is created as a CMI model and the PFD/CP model

is created as a Verilog-A module.


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Downloading GPDK180

To prepare for the workshop, you first need to complete the database by downloading the

Cadence 0.18um CMOS Generic Process Design Kit (GPDK180). To get a copy of

GPDK180,

Action 2-1: Go to pdk.cadence.com.

Action 2-2: Register as a new user, then log in.

Action 2-3: Click Downloads.

Action 2-4: Specify Generic for Foundry, 0.18 for Size, and MS/RF for Mode.

Action 2-5: Click SEARCH to search for a pdk matching the above attributes.


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Action 2-6: Download gpdk180_v3.3.tar.gz to ./PLL_workshop.

Action 2-7: Move into the ./PLL_workshop directory.

Action 2-8: Unpack the workshop.

tar –zxf gpdk180_v3.3.tar.gz

Action 2-9: Create a symbolic link to gpdk180 from whatever version of the design kit

you downloaded. For example,

ln –s gpdk180_v3.3 gpdk180


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Before Starting

Note: To use the noise-aware PLL flow shown in this workshop, you must have MMSIM

72 or later and one of the following IC versions:

• IC 5.10.41.ISR141

• IC 6.1.3.ISR17

• IC 6.1.4 ISR1

• or later

Action 3-1: Move into the ./PLL_workshop directory.

Action 3-2: View the cds.lib file. This file defines the path for the pllMMLib

library, which is located at:

<CDS_HOME>/tools/dfII/samples/artist/pllMMLib

Action 3-3: View the .cdsinit file. Notice the following line added for this

workshop:

envSetVal("spectre.envOpts" "controlMode" 'string "batch")

This script makes the Spectre simulator run in batch mode from ADE.

Action 3-4: Run the virtuoso tool.

Action 3-5: In the CIW, choose Tools – Library Manager.

This library contains the appropriate testbench for each block.


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Integer-N PLL design flow

Creating a CMI Model for the VCO/Divider

Action 4-1-1: In the Library Manager window, open the schematic view of the

vco_bench in the library PLL_workshop.

The VCO testbench, vco_twin_bench, is copied from the pllMMLib library. The

transistor level design of the VCO and divide-by-2 is inserted in this testbench. You

can modify other port parameters based on your design needs except the cell name

and instance name of the port in this testbench otherwise the simulation will be error

out.

Note: The probe VCO_vss connected to the node Vss is now temporarily used for

PLL_drive node PPV characterization. The following schematic shows the voltage

probe is converted to the current and injected into the LC tank.


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Action 4-1-2: In the Virtuoso Schematic Editing window, choose Launch – ADE L.

Action 4-1-3: (Optional) Choose Session – Load State in the Virtuoso Analog Design

Environment window, change the Load State Option to Cellview, choose state

spectre_state1, click OK, then skip to Action 4-1-6.


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Action 4-1-4: In the Choosing Analyses window, select pss in the Analysis field and set

up the form as follows:


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Note: no sweep is set in PSS analysis. And the sweep will be set in the PLL Macro

Model Wizard window.

Action 4-1-5: Set up the Pnoise analysis by clicking pnoise in the Choosing Analyses

form and setting up the form as follows:


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The PLL simulation flow handles both white and flicker noise. The sweep frequency

range of the Pnoise analysis is chosen so that the total noise at frequencies outside

the range is negligible.

Action 4-1-6: In the Virtuoso Analog Design Environment window, select Tools –RF –

PLL … and set up the form as follows:

For the VCO Template field,

Normal: VCO macro-model with VCO output for integer-N PLL

Fast: VCO macro-model without VCO output for integer-N PLL

Frac-N: VCO macro-model with VCO output for fractional-N PLL

Fast Frac-N: VCO macro-model without VCO output for fractional-N PLL


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For the VCO Multiphase field,

1: One output is created for the VCO model.

2: Two outputs are created for the VCO model. These two ouputs are the

differential outputs each other.

4: Four outputs are created for the VCO model. These four outputs are the

differential or orthogonal outputs.

For the VCO Sweep field,

VTUNE: Sweep VCO control voltage

VDD: Sweep VDD

VSS: Sweep VSS

Disable: No VDD or VSS sweep

VCO macro-model is a table model that is obtained by sweeping the input control

voltage. The VTUNE sweep range should be between Vmin and Vmax. A sweep

grid that uses small steps increases the accuracy of the macro-model at the cost of

increased extraction time. It is not necessary to have very small grid to create model.

The user can add specfic points to realize coarse sweep in whole sweep range and

fine sweep around target Vtune. When this model is used in future simulation, the

model looks up values in the table according to the input controlv oltage, VDD and

VSS and calculates the output.

Action 4-1-7: The Virtuoso Analog Design Environment window looks like this:


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Action 4-1-8: In the Virtuoso Analog Design Environment, choose Simulation – Netlist

and Run to start the simulation or click the Netlist and Run icon in the Virtuoso

Analog Design Environment window.

The simulation takes a few minutes to complete. When the simulation finishes, a cell

named oscmm is added to the PLL_workshop library.


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In the macro model oscmm, any noise or change at node VTUNE, VDD and VSS will be

treated as perturbation and it is impact in large signal and small signal behavior will be

calculated by spectre. However, if there is big change in VDD or VSS, it cannot be

treated as perturbation. In this case, the user needs to add one more dimension in the table

model by sweeping VDD or VSS. For example, the wizard might be set up as follows to

create a new model.


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named oscmm_vdd is added to the PLL_workshop library.


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Creating a Model for the PFD/CP


pfd_cp_bench in the library PLL_workshop.

The PFD-CP testbench is copied from the pllMMLib library. The transistor level

design of the Phase Frequency Detector (PFD) and of the Charge Pump (CP) is

inserted in this testbench. You can modify other port parameters based on your

design needs except the cell name and instance name of the port in this testbench

otherwise the simulation will be error out.

The jitter of the PFD-CP is dependent on the phase difference between the input

reference clock and the feedback clock from the divider. The vsource delay

parameter may be used to set the phase difference between Vref and Vfb. The delay

difference of Vfb and Vref can be arbitrary.


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Action 4-2-3: (Optional) In the Virtuoso Analog Design Environment window, choose

Session – Load State, change the Load State Option to Cellview, select state

spectre_state1, click OK, then skip to Action 4-2-6.


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Action 4-2-4: In the Choosing Analyses window, select pss in the Analysis field of the

window and set up the Periodic Steady State Analysis form as follows:


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Generally the PFD-CP is very nonlinear so that achieving convergence with HB is

difficult. Consequently, Cadence recommends that you not use Harmonic Balance to


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extract the PFD-CP macro-model. In addition, it is more accurate to measure tr and

td by using the time domain waveform that is directly generated by the transient

analysis when the shooting engine is used. HB is not accurate for these

measurements because it cuts off high frequency harmonics.

Action 4-2-5: Set up the Periodic Noise analysis by clicking pnoise in the Choosing

Analyses form and setting up the Periodic Noise Analysis form as follows:

The output frequency sweep range of the Pnoise analysis is chosen so that the total noise

at frequencies outside the range is negligible. The noise should be at least 40 dB down


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and dropping at the highest frequency simulated. Choose the lower limit of integration by

considering what value is below the system bandwidth and the amount of validity in the

flicker noise model, which can grow unbounded as the frequency decreases.



For PFD/CP Sweep field,

Disable: jitter and the current is measured at 0.1*T and -0.1*T, where T is the

reference clock period.

fine: jitter and output current is measured at phase difference equals 0.1*T,

0.01*T, 0.001*T, 0.000*T, 0, -0.0001*T, -0.001*T,

-0.01*T, -0.1*T respectively.

coarse: jitter and output current is measured at the points where the phase

difference equals 0.1*T, -0.1*T and 0.


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For Load Voltage Sweep field,

The optional Load Voltage Sweep option can be used for simulating the load Voltage

effect on the jitter and output current.


Action 4-2-8: In the Virtuoso Analog Design Environment window, choose Simulation

– Netlist and Run or click the Netlist and Run icon to start the simulation.

The simulation takes a couple of minutes to complete. When the simulation finishes, a

cell named pllTTpcd_cp is added to the PLL_workshop library.


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(optional) Creating a Model for the Divider

To create macro model for the divider, the user can copy the cell divider_bench

from pllMMLib. The schematic view of the divider_bench in the PLL_workshop

library is an example of testbench setup.

The simulation state spectre_state1 shows the recommended setup for model extraction.

Before setup PSS/Pnoise analysis, the input signal should be set to square waves.

PNOISE sweep upper frequency should be set to f0/2, where f0 is input signals

frequency. The noise type should be set to "jitter" in PNOISE.

After setup PSS/Pnoise analysis , In the ADE PLL wizard, the user can select Divider

Bench and specify a Library Name and a Cell Name to contain the divider macro-model.

After simulation, the model will be created automatically. A file which contains divider

model information will be attached to this cell, The main content in this file is jitterpower

spectrum. However, this model doesn't contains the divide ratio information, the user

should still specify this information in the cell oscmm.

Usually divider simulation will be very memory hungary. If the divider ratio is high, it is

recommeded to separate the divider to 2 parts and simulate indivudually. The following

testbench pll_bnech_dividermodel shows the pll top level testbench setup with divider

simulated seperately in two parts.


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The major noise contributor in a PLL loop will be VCO and PFD/CP. It is not

recommended to extract divider model. The user can simulate the PLL as shown in next

section.


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Simulating an Integer PLL

Action 4-3-1: In the Library Manager window, open the schematic view of the pll_bench

in the PLL_workshop library.

The pll_bench testbench is copied from the pllMMLib library. The CMI model of

VCO/Prescaler and the Verilog-A model of the PFD/CP are inserted in this testbench.

You can modify other port parameters based on your design needs (except for the cell

name and instance names of the port in this testbench otherwise the simulation will error

out).

Action 4-3-2: Inspect the schematic. It is already set up with the correct modeling block

association. The PFD/CP (pllTTpfd_cp) and VCO/Prescaler (oscmm)

blocks that were previously created are in the schematic. For the PFD/CP

block, it was necessary to copy the veriloga view to the cell. For the

VCO block, the CMI model is associated in the properties form of the

VCO setup.


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Action 4-3-3: Inspect the oscmm object properties. Set the parameters as shown in the

following picture.

In the list of parameters,


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Divider Ratio: The divider is integrated into the oscmm, so this parameter is the divider

ratio.

Low Output Voltage: The output low level for the divider.

High Output Voltage: The output high level for the divider.

Sample Points per Period: To calculate the phase accurately, oscmm bounds the time

step. The maximum time step of the tran simulation is calculated as

1/(vco frequency)) / sample points per period

For faster simulation, set Sample Points per Period to 1. If you are inspecting and

calibrating the actual frequency versus time without aliasing, set the value to 50. If you

are looking at spectral harmonics or at an eye diagram after lock, set the Sample Points

per Period to 1. This workshop uses the value 20 to accurately calculate the noise.

Start Time of Jitter Injection: Specifies when to begin injecting VCO jitter information.

Generally, the value set is larger than the settling time of PLL so that the locked PLL

noise is calculated.

VCO Jitter: Specifies the jitter number to inject into the model. The value set here

overwrites the one shown in the CMI model.

PPV Model File: The oscmm is based on ppv. This PPV Model File parameter

specifies the file containing the ppv information. The file is generated after extracting

VCO. The default file name is oscPPVmodel.mat and is located in the path

./PLL_workshop/PLL_workshop/oscmm. Alternatively, you can specify a

different file name here, then define the relative path in the Virtuoso Analog Design

Environment window.

noiseseed: The seed for the random number generator.

divtrtf: The rise or fall time of the divider

osctrtf: The rise or fall time of VCO


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Action 4-3-4: Inspect the pllTTpdf_cp object properties with the CDF Parameter of

view set to veriloga. There are seven parameters, which are captured

during model creation. You can put a new value in the form to overwrite

the one in the Verilog-A model. Parameter Vtrans is not extracted into

the Verilog-A file. It must be set based on your own design. For this

example, you can set it as shown in the following picture.


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In the list of parameters:

Imax: The pfd-cp output current when the inputs have phase mismatch.

Vtrans: Threshold voltage of the transition of the reference clock and of the fb clock

from low to high. The default value is 1.

dir: Triggers the cross event using a rising edge (if the value is 1) or a falling edge (if the

value is -1). The default value is 1.

jitter: The period jitter of the pfd-cp.

Imis: Mismatch between the up current and down current, defined by:

maxI

III

downup

mis

−=

, 2max

downup III

+=

.

Ioffset: Output current offset.

refdelay: Delay time from reference clock input to up current output.

fbdelay: Delay time from feedback clock input to down current output.

uptr: Up current rise or fall time.

downtr: Down current rise or fall time.

modelfiel: The noise model file of pfd-cp

noisestart: Specifies when to begin injecting pfd-cp jitter information. Generally, the

value set is larger than the settling time of PLL so that the locked PLL noise is calculated.

noiseseed: The seed for the random number generator.


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Action 4-3-5: Inspect the vco_freq object properties with the CDF Parameter of

view set to veriloga. This instance measures the periods of VCO

output (vco_p and vco_n) or divider output (div_p and div_n) in

response to rising cross events and writes the periods into a file. After a

transient analysis, a plug-in searches this instance and the file and

calculates the phase noise power spectrum density (PSD) from the periods

in the file. The parameters are explained below.

Vthup: Threshold voltage to determine the rise edge of the input waveform. The input

waveform period is determined by two adjacent rise edges.

ttol: The tolerance of the time where the rise edge is determined.


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outStart: The time when freq_meter starts to output the measured waveform's period to

the 'outfile'. Default is 0. To get accurate phase noise measurement, you need set it to past

the time when the PLL is locked or when the oscillator is at the designed for frequency.

outfile: The name of a file to contain time-dependent periods for the PSD calculation.

Specify just the file name, not a path. If outfile is left blank, the default name is

periods.txt.


Action 4-3-7: (Optional) Choose Session – Load State in the Virtuoso Analog Design

Environment window, change the Load State Option to Cellview, click

OK, choose state spectre_state1, then skip to Action 6-11.


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Action 4-3-8: In the Choosing Analyses window, select tran in the Analysis field and

set up the form as follows:


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– Netlist and Run or click the Netlist and Run icon to start the

simulation.

The simulation takes about 30 minutes. If you prefer, you can skip the simulation and

load the provided simulation results. To do that, in the ADE window, select Tools –

Waveform. After the Graph Window appears, click Trace – Load, under

./traces_saved, load the following curves (one at a time). The following plot shows

the Vtune changes during the lock period.

tran_ppv_pll_no_inj.vcsv – PLL transient simulation with no injection

psd_ppv_pll_no_inj.vcsv – PLL phase noise with no injection


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If you run a tran simulation on the transistor level design, and overlay that result on the

result of the behavioral model, as in the following screen capture, you find that they

match exactly.


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Action 4-3-12: In the Virtuoso Analog Design Environment window, choose Results –

Direct Plot – Main Form.

Action 4-3-13: In the Direct Plot Form, select PLL Noise PSD and click Plot.


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Action 4-3-14: In the new subwindow, change the x-axis scaling to Log.

The following plot shows the PLL noise PSD.

Now that you are familiar with the basic operations of PPV PLL flow, continue through

the following actions to see the impact of injection pulling on PLL performance. A noise

current is injected into one side of the differential VCO LC tank. In the workshop, a

voltage source, vsin, is marked in the following schematic and attached to the VCO, and

can be converted to current in PPV model.


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Action 4-3-15: Select the previously open ADE window with the pll_bench design.

Select Variables – Edit. Select the InoiseAmp variable. Change the

Value to 1m. Click OK to close it.


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In the list of design variables,

InoiseFreq: The injected noise voltage frequency. Set the frequency close to the VCO

LC tank frequency.

InoiseAmp: The injected noise voltage amplitude (0 for no injection, 1m for 1mV

injection, and so on).



simulation.


load the provided simulation results. To do that, select Tools – Waveform. After the

Graph Window appears, click Trace – Load, under ./traces_saved, load the

following curve.

psd_ppv_pll_v_inj_1mV_4p7GHz.vcsv – PLL phase noise 1mV noise current

Note: For an FM signal:


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cos(w0*t + sin(w1*t))

with

w1 = w_natural – w_inj

The side spurs locations are:

w0 + n*w1, n = (+/-) 1, 2, 3, …

In our case,

w1 = 2480M*2 – 4700M = 260MHz

Injection pulling contributes spurs in the phase noise spectrum.

The next actions demonstrate the power supply noise rejection of the PLL. In the

workshop, a voltage source, vsin, is marked in the following schematic and attached

with VCO, and can be converted to current in the PPV model.


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Action 4-3-17: Select the previously opened ADE widow with the pll_bench design.

Select Variables – Edit. Select the InoiseAmp variable and change the

Value to 0m.Select the VnoiseAmp variable and change the Value to

1m. Click OK to close it.


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In the list of design variables:

VnoiseFreq: the injected supply noise voltage frequency.

VnoiseAmp: the injected supply noise voltage amplitude (0 for no injection, 1m for 1mV

injection, and so on).



simulation.




following curve.

psd_ppv_pll_v_inj_1mV_10MHz.vcsv – PLL noise with supply noise injection

Note: Unlike the LC tank noise current injection mentioned previously, this is a common

mode injection on a differential VCO.

The spur generation mechanism: Power supply noise — AM modulation on VCO LC

tank output — FM modulation after VCO buffers.


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No “beat” frequency is generated (the injection noise at 10M generates the spur at 10M).

Action 4-3-19: To sweep non-linear behavior for PLL, in the pll_bench schematic,

change the cell name for the VCO model from oscmm to oscmm_vdd,

then choose Design – Check and Save.

Action 4-3-20: Select the ADE window that is already open with the pll_bench

design. Select Variables – Edit. Select the InoiseAmp variable and

change the Value to 0m. Select the VnoiseAmp variable and change the

Value to 100m. Click OK to close it.


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simulation.




following curve.

psd_ppv_pll_v_inj_nonlinear.vcsv – PLL noise with supply noise injection


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Fractional-N PLL Design Flow

Creating a CMI Model for the VCO/Divider


vco_bench in the library PLL_workshop.


Action 5-1-3: (Optional) In the Virtuoso Analog Design Environment window, choose

Session – Load State, change the Load State Option to Cellview,

choose state fractional, click OK, then skip to Action 5-1-6.


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Action 5-1-4: In the Choosing Analyses window, select pss in the Analysis field and set

up the form as follows:


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Action 5-1-5: Set up the Pnoise analysis by clicking pnoise in the Choosing Analyses

form and setting up the form as follows:


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Action 5-1-8: In the Virtuoso Analog Design Environment, choose Simulation – Netlist

and Run to start the simulation or click the Netlist and Run icon in the

Virtuoso Analog Design Environment window.


named oscmm_frac is added to the PLL_workshop library.


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Creating a Model for the PFD/CP

The PFD/CP modeling of the fractional-N PLL is the same as that of the integer-N PLL,

so the cell pllTTpfd_cp is used to simulate the fractional-N PLL.

Simulating a Fractional-N PLL


pll_frac_bench in the PLL_workshop library.


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Action 5-3-2: Consider the oscmm_frac module. Set the parameters as shown in the

following picture.


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There is the similar CDF parameters definition except the following parameters list:


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mappingmode: Specifies VCO divide ratio mode. Possible values are parammapping,

signalmapping, or filemapping.

Divider Ratio List: Specifies values for vco divide ratio.

mapping_file: Specifies file name for VCO divide ratio.

High Divider Control Voltage: Specifies high voltage value of divider.

Low Divider Control Voltage: Specifies low voltage value of divider.

Action 5-3-3: Consider the SDM_MASH_3rd_111_macro module.

Open the CDF form of the block SDM_MASH_3rd_111_macro and set up the form as

follows:


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Vtrans: CP trigger threshold

BIT: Set the ADC bit in the module

outOffset: Output value of the sigma-delta is in range of -3+

Action 5-3-4: Consider the adc_3bit_ideal module. This module is an ADC. It converts

the delta-sigma modulator's output into the digital signal that controls

the VCO divide ratio.

The extractions of the PFD-CP model and of the VCO model are exactly the same as in

the previous lab. The noise of the divider is not included in this testbench. The ideal

behavior of the divider is represented by the above two Verilog-A modules. In a real

case, you can use your own Verilog-A modules in the simulation.

Action 5-3-5: In the Library Manager window, open the spectre_state1 view of

the PLL_MM_frac cell in the PLL_workshop library. The ADE

window appears.

Action 5-3-6: In the ADE window, choose Simulation – Netlist and Run or click the

Netlist and Run icon to start the simulation.




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following two curves.

PLL_MM_frac_Tran.vcsv – The Vtune changes during the lock period

PLL_MM_frac_PSD.vcsv – PLL noise PSD

Action 5-3-7: In the Virtuoso Analog Design Environment window, choose Results –

Direct Plot – Main Form.

Action 5-3-8: Select Voltage in the Direct Plot Form, select the net vtune in the

schematic, then click Plot in the Direct Plot Form.

Action 5-3-9: In the Direct Plot Form, select PLL Noise PSD and click Plot.


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Action 5-3-10: In the new subwindow, change the x-axis scaling to Log.

The following plot shows the PLL noise PSD.


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As in the integer-N simulation, this setup injects a noise current into one side of the

differential VCO LC tank and allows you to see the impact of injection pulling on the

PLL performance.




following curve.

PLL_MM_frac_PSD_Tank.vcsv – PLL phase noise 1mV noise current

As with the integer-N simulation, this setup injects noise from the power supply VDD

and allows you to see how well the PLL rejects the noise.




following curve.

PLL_MM_frac_PSD_Supply.vcsv – PLL noise with supply noise injection


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Noise Aware PLL flow FAQs

Why do we need nonlinear oscillator models? What is the PPV model?

It is well known that the LTI model, based on Lesson theory, only works in the condition

of the Linear Time-Invariant operation point. Linear oscillator models often fail to

accurately predict oscillation amplitude and phase deviations under perturbations.

In recent years, the nonlinear effects in RF oscillators play more important roles and are

given much more attention. The sensitive states of this sort of oscillators are described

with Linear Periodic Time-Varying system. Many noise models based on LPTV, both in

time-domain and frequency-domain, are reported. Among these models are the Impulse

Sensitive Function (ISF) model proposed by Harjimiri&Lee [2][3] and the nonlinear

Perturbation Project Vectors (PPV) model proposed by Demir&Mehrotra which are both

widely used [4].

The two models in fact are tightly related by further observing the definitions of ISF and

PPV. ISF defines the phase sensitivity to state variables. PPV represents the time

sensitivity to the state variables. ISF could be obtained with PPV by multiplying the

angle frequency, and vice versa. For most cases the two models could be equivalent. At

near carrier, they have different behaviors. The phase noise obtained from PPV converges

to a constant and total power density is fixed, while the phase noise obtained from ISF

diverges to infinite and power density too.

PPV is used to provide the delta-changes which are necessary for iterations in simulation,

thus making the output of VCO/DIVIDER trace the reference frequency. With this non-

linear vco model, you can simulate the capture of the nonlinear effect of oscillators such

as injection locking, power supply interference, cycle slipping, all of which can not be

performed by traditional non-linear models.

SpectreRF can generate a ppv file of an autonomous circuit from pss/pnoise simulation.

Once the vco_bench in the PLL wizard outlined in this tutorial is selected, on the Periodic

Noise Options form, the button use=ppv for osc will be enabled automatically and the

ppv will be output by default.

My PLL wizard is greyed out, how can I fix that?

In order to use the correct PLL wizard, you should have the correct version of MMSIM

and IC installed. The version information for each release is documented in session 3..


________________________________________________________________________


Even with the correct versions of MMSIM and IC, some companies with internal

wrappers to configure a design environment may still have problems.

If the wizard is greyed out, this means that IC can not locate the correct feature file from

the simulator.

To resolve this problem:

setenv SPECTRE_FEATURE_FILE <spectre install

dir>/tools.lnx86/spectre/etc/files/spectre.dat

Once you see the GUI, the button shown on the PLL Wizard should guide the simulator

to find the correct pll related .so files. Sometimes you may still experience the following

error message when you choose the VCO Bench from ADE->tools->RF->Wizards-

>PLL:

"Unable to find VCO plugin in simulator library directory PLL Macro Model will be

disable"

To resolve this problem, add an additional line in your .cdsinit file in your working

directory:

_pll_gloabl_spectre_path = <spectre install dir>/tools.lnx86/spectre

If I want to simulate a VCO with noise from power supply or substrate

using transient noise, is it possible to use the pll_bench to get PSD plot?

Yes.

To use this approach:

1. Set up your oscillator testbench circuit for a transient noise analysis (Attached is a

transient noise app note - note however that it doesn't cover the phase noise

measurement but addresses setting up the simulation analysis).

2. In the testbench circuit add the block freq_meter from the library pllMMLib

($CDSHOME/tools//dfII/samples/artist/pllMMLib)

Connect the vin_p and vin_n pins to the output of the oscillator circuit (if a single

ended oscillator output, connect to vin_p pin and ground the vin_n pin). Place a

noConn cell from the basic library on the out_freq pin.

The parameters for this block are (set Tools Filter to veriloga in the CDF parameter

form):


________________________________________________________________________


Vthup: Threshold voltage to determine the rise edge of the input waveform. The input

waveform period is determined by two adjacent rise edges. Default is 0.

ttol: The tolerance of the time where the rise edge is determined. Default is 1p.

outStart: The time-dependent period of the input waveform is output to the outfile

when the time is greater than outStart. Default is 0. To get accurate phase noise

measurement, set this to passed the time when the oscillator is fully powered up and

oscillating at the designed for frequency.

outfile: The name of a file to contain time-dependent periods for use in later PSD

calculations. Specify just the file name, not a path. If the outfile is left blank, the

default name is periods.txt.

Also, the instance name for this block has to be 'vco_freq'.

3. Before starting the sim, in the ADE window, select Tools->RF->PLL. In the PLL

Macro Model Wizard window, enable PLL Macro Model and select PLL Bench as

the Bench Type. Then OK this form.

4. Run the simulation. Currently the simulation must run successfully to completion in

order to get to the phase noise results.

5. In the direct plot form transient noise, there should be a PLL PSD Noise option. This

will allow you to plot the phase noise results. If a message is displayed saying that the

PLL Noise PSD data is not available, make sure 'Vthup' and 'outStart' are reasonble

and check 3) and 4). After any corrections you will need to re-run the simulation.

The phase noise plot will extend from fmin = 4/tstop to fmax = fosc/2, where tstop is

the transient noise simulation stop time and fosc is the oscillation frequency of the

circuit.

I ran the transient ( or transient noise ) simulation on pll_bench

successfully, but when I try to plot the PSD results from Direct Plot

form, the button appears but when I select it, the Direct Plot form

informs me that the PLL Noise PSD data is not available.

In order to understand this problem, we need to first understand how the flow works.

Since the PLL noise performance is of interest in this case, a freq_meter instance is added

to the test bench. This instance measures the periods of VCO output (vco_p and vco_n)

or vco output (div_p div_n) in response to rise cross events and writes the periods into a

file named in 'outfile' (default is periods.txt). After a transient analysis, a plugin searches

this instance, and the file, and calculates the phase noise power spectrum density (PSD)

from the periods in the file and make it available for the Direct Plot Form.


________________________________________________________________________


The most likely reason for this is that the parameter 'outStart' in the CDF of the

freq_meter is greater than the transient simulation time so that no data is saved in the

"outfile". For example, in the workshop, we set 600u for tran stop time, and

'outStart'=300u in the CDF. Then after simulation the data between 300u and 600u will

be taken to do post processing and generate PSD.

Another reason is that with some incorrect setting (for example, errpreset=liberal), the

vco, if it is in schematic view, doesn't start to oscillate at all, and there is no periodic

signal detected, thus no data is created in the periods.txt file.

Can I only extract VCO model and use it in the pll_bench while keep

PFD/CP in transistor level design or extracted view?

Yes, we support this use model and the PLL wizard can still be used to plot PSD.

However, in order to take the noise contribution from PFD/CP into account, you need to

run tran noise instead of tran only.

I know that there is a VCO testbench for 4 phases of output. How do I

setup the pnoise analysis for 4 output phases?

Once you select 4 phases of output in the PLL wizard, since they correspond to the ports

in the testbench, the simulator will smartly switch one by one.

Can we modify the VCO testbench template to accomodate multiple

inputs? We have 2 inputs.

It is very normal for the VCO to have two inputs or two controls, say coarse control (for

example, we can call it as Vcoarse) and fine control: Vfine. You can connect the Vcoarse

to the Vtune in the current vco bench and connect Vfine to VDD. The real VDD just

connects to the power supply directly, and it does not need a pin in the testbench.

In other words, the 3 sweep variables (Vtune, VDD, CSS) in the PLL wizard are the

"false" names, and you can simply call them sweep variable1, 2 and 3. They are equal in

terms of tuning curve, ppv, and pnoise. Those 3 nodes can take perturbation from

external circuitry (for example, PFD/CP or Power supply).

There are 2 versions available for each extraction model to create, i.e.

normal and fast. How are they different in terms of speed and

accuracy?


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There is no accuracy difference. By selecting "fast" mode, the extracted model will not

output the VCO waveform. As there is no small transient step caused by this high

frequency, the top pll_bench simulation will be faster. For no VCO output, you can not

probe the VCO phase noise. However, the noise information is still available in the

model.

Plotting the PLL Noise PSD shows the whole system Noise PSD. Is there any way

we can see the individual contribution, i.e. as a percentage of the total jitter?

It is very difficult to quantatively measure the contribution from each building block

since it is a feedback loop and each block has impact to other blockers. However, you

can force a model (say VCO) to be noise-less by specifying parameter VCO Jitter of

oscmm as 0. Then you can simulate the PLL and compare PSD with that of PLL with

nonzero VCO jitter.

What is the meaning of Sample Points per Period in oscmm? What number should I

specify for my simulation?

The minimum sample points per VCO period, is used to restore the VCO output

waveform. The waveform's periods will be measured by 'freq_meter' for PSD calculation.

For the 'freq_meter', capture the rise edge; the sample point number should large enough

to draw the rise edge. By default, the rise time is 5 percent of VCO period, so 20 points is

enough for PSD calculation. For locking observation, 1 point is enough.

There are phase jitter number and period jitter number availe on the top of the PSD

plot. How Spectre calculates those numbers.

After tran simulation on the pll_bench, the freq_meter will extract the period of the

output using the time when the output cross the threashold voltage (Vthup) specified in

freq_meter. The period information is in periods.txt under

./simulation/pll_bench/spectre/schematic/netlist/periods.txt

Based on the data in periods.txt:

T1

T2

…..

TN


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The periods of PLL output can be calculated using

∑=i

iTN

T1

Then period jitter is ( )

2

1

1∑

=

−=n

i

ip TTN

J

, this is also called cycle jitter.

From the period information, we can also get ∑ ×=

i

ii TT0

2πφ

Phase noise (PSD) will be ( ) ( )fsiFFT

i=− 2

2πφ

Another common defintion for jitter known as rms phase jitter

is therefore related to the phase noise according to


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References

[1] Noise Aware PLL Flow User Guide

[2] Hajimiri A, Lee T H. A General Theory of Phase Noise in Electrical Oscillators, IEEE

Journal of Solid-State Circuits, 1998, 33(2): 179~194

[3] Lee T H, Hajimiri A. Oscillator Phase Noise: A Tutorial. IEEE Journal of Solid-State

Circuits, 2002, 35(3): 326~336

[4] Demir A, Liu E W Y, and Sangiovanni-Vincentelli A L. Time-domain non Monte-

Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. IEEE

Transactions for Computer-Aided Design, 1996, 15(5): 493~505

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